Re: [PATCH] RISC-V: Fix selection of pipeline model for sifive-7-series

[Kito Cheng <kito.cheng@gmail.com>]

LGTM, thank you for catching that!!

On Wed, Nov 9, 2022 at 3:50 PM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote:
>
> A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a
> while now, due to the pipeline model for sifive-7-series not being
> selected despite -mtune=sifive-7-series.  The root cause is that the
> respective RISCV_TUNE entry points to generic instead.  Fix this.
>
> Fixes 97d1ed67fc6 ("RISC-V: Support --target-help for -mcpu/-mtune")
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-cores.def (RISCV_TUNE): Update
>           sifive-7-series to point to the sifive_7 pipeline
>           description.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
>
>  gcc/config/riscv/riscv-cores.def | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
> index b84ad999ac1..31ad34682c5 100644
> --- a/gcc/config/riscv/riscv-cores.def
> +++ b/gcc/config/riscv/riscv-cores.def
> @@ -36,7 +36,7 @@
>  RISCV_TUNE("rocket", generic, rocket_tune_info)
>  RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
>  RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
> -RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info)
> +RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
>  RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
>  RISCV_TUNE("size", generic, optimize_size_tune_info)
>
> --
> 2.34.1
>