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From: Haochen Jiang <haochen.jiang@intel.com>
To: gcc-patches@gcc.gnu.org
Subject: [wwwdocs] gcc-13: Mention Intel new ISA and march support.
Date: Thu, 10 Nov 2022 14:01:43 +0800	[thread overview]
Message-ID: <20221110060143.28132-1-haochen.jiang@intel.com> (raw)

Hi all,

This patch aims to mention newly added Intel ISA and march support.

Ok for trunk?

BRs,
Haochen

---
 htdocs/gcc-13/changes.html | 50 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index bd11cbec..0daf921b 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -240,6 +240,56 @@ a work-in-progress.</p>
   <code>__bf16</code> type to x86 psABI. Users need to adjust their
   AVX512BF16-related source code when upgrading GCC12 to GCC13.
   </li>
+  <li>New ISA extension support for Intel AVX-IFMA was added to GCC.
+      AVX-IFMA intrinsics are available via the <code>-mavxifma</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AVX-VNNI-INT8 was added to GCC.
+      AVX-VNNI-INT8 intrinsics are available via the <code>-mavxvnniint8</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AVX-NE-CONVERT was added to GCC.
+      AVX-NE-CONVERT intrinsics are available via the
+      <code>-mavxneconvert</code> compiler switch.
+  </li>
+  <li>New ISA extension support for Intel CMPccXADD was added to GCC.
+      CMPccXADD intrinsics are available via the <code>-mcmpccxadd</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel AMX-FP16 was added to GCC.
+      AMX-FP16 intrinsics are available via the <code>-mamx-fp16</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel PREFETCHI was added to GCC.
+      PREFETCHI intrinsics are available via the <code>-mprefetchi</code>
+      compiler switch.
+  </li>
+  <li>New ISA extension support for Intel RAO-INT was added to GCC.
+      RAO-INT intrinsics are available via the <code>-mraoint</code>
+      compiler switch.
+  </li>
+  <li>GCC now supports the Intel CPU named Raptor Lake through
+    <code>-march=raptorlake</code>.
+    Raptor Lake is based on Alder Lake.
+  </li>
+  <li>GCC now supports the Intel CPU named Meteor Lake through
+    <code>-march=meteorlake</code>.
+    Meteor Lake is based on Alder Lake.
+  </li>
+  <li>GCC now supports the Intel CPU named Sierra Forest through
+    <code>-march=sierraforest</code>.
+    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and
+    CMPccXADD ISA extensions.
+  </li>
+  <li>GCC now supports the Intel CPU named Grand Ridge through
+    <code>-march=grandridge</code>.
+    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD
+    and RAO-INT ISA extensions.
+  </li>
+  <li>GCC now supports the Intel CPU named Granite Rapids through
+    <code>-march=graniterapids</code>.
+    The switch enables the AMX-FP16 and PREFETCHI ISA extensions.
+  </li>
 </ul>
 
 <!-- <h3 id="mips">MIPS</h3> -->
-- 
2.18.1


             reply	other threads:[~2022-11-10  6:03 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-10  6:01 Haochen Jiang [this message]
2022-11-14  1:36 ` Hongtao Liu
2022-11-14 13:55 ` Gerald Pfeifer
2022-11-16  1:30   ` Jiang, Haochen

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