From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: Jeff Law <jlaw@ventanamicro.com>,
Vineet Gupta <vineetg@rivosinc.com>,
Kito Cheng <kito.cheng@gmail.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Palmer Dabbelt <palmer@rivosinc.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v2 0/8] RISC-V: Backend support for XVentanaCondOps/ZiCondops
Date: Sun, 13 Nov 2022 22:20:21 +0100 [thread overview]
Message-ID: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> (raw)
Both the XVentanaCondOps (a vendor-defined extension from Ventana
Microsystems) and the proposed ZiCondOps extensions define a
conditional-zero(-or-value) instruction, which is similar to the
following C construct:
rd = rc ? rs : 0
This functionality can be tied back into if-convertsion and also match
some typical programming idioms. This series includes backend support
for XVentanaCondops and infrastructure to handle conditional-zero
constructions in if-conversion.
Tested against SPEC CPU 2017.
Changes in v2:
- Restore a (during rebase) dropped line to xventanacondops.md
- Include the change to add xventanacondops to the VT1 code definition]
as a separate patch.
Philipp Tomsich (8):
RISC-V: Recognize xventanacondops extension
RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion
RISC-V: Support noce_try_store_flag_mask as vt.maskc<n>
RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
RISC-V: Recognize bexti in negated if-conversion
RISC-V: Support immediates in XVentanaCondOps
RISC-V: Ventana-VT1 supports XVentanaCondOps
ifcvt: add if-conversion to conditional-zero instructions
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/predicates.md | 12 +
gcc/config/riscv/riscv-cores.def | 2 +-
gcc/config/riscv/riscv-opts.h | 3 +
gcc/config/riscv/riscv.cc | 14 ++
gcc/config/riscv/riscv.md | 27 +++
gcc/config/riscv/riscv.opt | 3 +
gcc/config/riscv/xventanacondops.md | 151 ++++++++++++
gcc/ifcvt.cc | 214 ++++++++++++++++++
.../gcc.target/riscv/xventanacondops-and-01.c | 16 ++
.../gcc.target/riscv/xventanacondops-and-02.c | 15 ++
.../gcc.target/riscv/xventanacondops-eq-01.c | 11 +
.../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++
.../riscv/xventanacondops-ifconv-imm.c | 19 ++
.../gcc.target/riscv/xventanacondops-le-01.c | 16 ++
.../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++
.../gcc.target/riscv/xventanacondops-lt-03.c | 16 ++
.../gcc.target/riscv/xventanacondops-ne-01.c | 10 +
.../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++
.../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++
.../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++
21 files changed, 600 insertions(+), 1 deletion(-)
create mode 100644 gcc/config/riscv/xventanacondops.md
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
--
2.34.1
next reply other threads:[~2022-11-13 21:20 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-13 21:20 Philipp Tomsich [this message]
2022-11-13 21:20 ` [PATCH v2 1/8] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 2/8] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 3/8] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 4/8] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 5/8] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 6/8] RISC-V: Support immediates in XVentanaCondOps Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 7/8] RISC-V: Ventana-VT1 supports XVentanaCondOps Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 8/8] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
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