From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: Jeff Law <jlaw@ventanamicro.com>,
Vineet Gupta <vineetg@rivosinc.com>,
Kito Cheng <kito.cheng@gmail.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Palmer Dabbelt <palmer@rivosinc.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH v2 7/8] RISC-V: Ventana-VT1 supports XVentanaCondOps
Date: Sun, 13 Nov 2022 22:20:28 +0100 [thread overview]
Message-ID: <20221113212030.4078815-8-philipp.tomsich@vrull.eu> (raw)
In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu>
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_CORE): Update the
Ventana-VT1 definition to include the xventanacondops
extension.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
Changes in v2:
- New in v2.
gcc/config/riscv/riscv-cores.def | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index aef1e92ae24..9e38e9dc72e 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series")
RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series")
RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series")
-RISCV_CORE("ventana-vt1", "rv64imafdc_zba_zbb_zbc_zbs_zifencei", "ventana-vt1")
+RISCV_CORE("ventana-vt1", "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops", "ventana-vt1")
#undef RISCV_CORE
--
2.34.1
next prev parent reply other threads:[~2022-11-13 21:20 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-13 21:20 [PATCH v2 0/8] RISC-V: Backend support for XVentanaCondOps/ZiCondops Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 1/8] RISC-V: Recognize xventanacondops extension Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 2/8] RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if-conversion Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 3/8] RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 4/8] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 5/8] RISC-V: Recognize bexti in negated if-conversion Philipp Tomsich
2022-11-13 21:20 ` [PATCH v2 6/8] RISC-V: Support immediates in XVentanaCondOps Philipp Tomsich
2022-11-13 21:20 ` Philipp Tomsich [this message]
2022-11-13 21:20 ` [PATCH v2 8/8] ifcvt: add if-conversion to conditional-zero instructions Philipp Tomsich
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