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From: Christoph Muellner <christoph.muellner@vrull.eu>
To: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>,
	Jeff Law <jeffreyalaw@gmail.com>,
	Vineet Gupta <vineetg@rivosinc.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH 2/7] riscv: bitmanip/zbb: Add prefix/postfix and enable visiblity
Date: Mon, 14 Nov 2022 00:05:16 +0100	[thread overview]
Message-ID: <20221113230521.712693-3-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20221113230521.712693-1-christoph.muellner@vrull.eu>

From: Christoph Müllner <christoph.muellner@vrull.eu>

INSNs are usually postfixed by a number representing the argument count.
Given the instructions will be used in a later commit, let's make them
visible, but add a "riscv_" prefix to avoid conflicts with standard
INSNs.

gcc/ChangeLog:

	* config/riscv/bitmanip.md (*<optab>_not<mode>): Rename INSN.
	(riscv_<optab>_not<mode>3): Rename INSN.
	(*xor_not<mode>): Rename INSN.
	(xor_not<mode>3): Rename INSN.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/bitmanip.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 3dbe6002974..d6d94e5cdf8 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -119,7 +119,7 @@ (define_insn "*slliuw"
 
 ;; ZBB extension.
 
-(define_insn "*<optab>_not<mode>"
+(define_insn "riscv_<optab>_not<mode>3"
   [(set (match_operand:X 0 "register_operand" "=r")
         (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
                             (match_operand:X 2 "register_operand" "r")))]
@@ -128,7 +128,7 @@ (define_insn "*<optab>_not<mode>"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
 
-(define_insn "*xor_not<mode>"
+(define_insn "riscv_xor_not<mode>3"
   [(set (match_operand:X 0 "register_operand" "=r")
         (not:X (xor:X (match_operand:X 1 "register_operand" "r")
                       (match_operand:X 2 "register_operand" "r"))))]
-- 
2.38.1


  parent reply	other threads:[~2022-11-13 23:05 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-13 23:05 [PATCH 0/7] riscv: Improve builtins expansion Christoph Muellner
2022-11-13 23:05 ` [PATCH 1/7] riscv: bitmanip: add orc.b as an unspec Christoph Muellner
2022-11-14 16:51   ` Jeff Law
2022-11-14 17:53     ` Jeff Law
2022-11-14 19:05     ` Philipp Tomsich
2022-11-13 23:05 ` Christoph Muellner [this message]
2022-11-14 16:55   ` [PATCH 2/7] riscv: bitmanip/zbb: Add prefix/postfix and enable visiblity Jeff Law
2022-11-13 23:05 ` [PATCH 3/7] riscv: Enable overlap-by-pieces via tune param Christoph Muellner
2022-11-14  2:48   ` Vineet Gupta
2022-11-14  7:59     ` Philipp Tomsich
2022-11-14  8:29       ` Christoph Müllner
2022-11-14 19:04         ` Jeff Law
2022-11-14 19:07           ` Christoph Müllner
2022-11-13 23:05 ` [PATCH 4/7] riscv: Move riscv_block_move_loop to separate file Christoph Muellner
2022-11-14 16:56   ` Jeff Law
2022-11-13 23:05 ` [PATCH 5/7] riscv: Use by-pieces to do overlapping accesses in block_move_straight Christoph Muellner
2022-11-14 17:16   ` Jeff Law
2022-11-14 19:01     ` Christoph Müllner
2022-11-14 19:05       ` Jeff Law
2022-11-13 23:05 ` [PATCH 6/7] riscv: Add support for strlen inline expansion Christoph Muellner
2022-11-14 18:17   ` Jeff Law
2022-11-14 21:07     ` Christoph Müllner
2022-11-13 23:05 ` [PATCH 7/7] riscv: Add support for str(n)cmp " Christoph Muellner
2022-11-14 19:28   ` Jeff Law
2022-11-14 21:49     ` Christoph Müllner
2022-11-15  0:22       ` Jeff Law
2022-11-15  0:46   ` Kito Cheng
2022-11-15  0:53     ` Palmer Dabbelt
2022-11-15  1:55       ` Kito Cheng
2022-11-15  3:41       ` Jeff Law
2022-11-15 22:22     ` Christoph Müllner
2022-11-16  0:15     ` Philipp Tomsich
2022-11-21  3:24       ` Kito Cheng

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