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* [PATCH] [x86] Fix incorrect implementation for mm_cvtsbh_ss.
@ 2022-11-23 12:28 liuhongt
  2022-11-23 12:40 ` Jakub Jelinek
  0 siblings, 1 reply; 8+ messages in thread
From: liuhongt @ 2022-11-23 12:28 UTC (permalink / raw)
  To: gcc-patches; +Cc: crazylht, hjl.tools, ubizjak

After supporting real __bf16 type, implementation of mm_cvtsbh_ss went wrong.
The patch supports extendbfsf2/truncsfbf2 with pslld/psrld,
and then refined the intrinsic with implicit conversion.

Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}.
Ok for trunk?

gcc/ChangeLog:

	PR target/107748
	* config/i386/avx512bf16intrin.h (_mm_cvtsbh_ss): Refined.
	* config/i386/i386.md (extendbfsf2): New define_insn.
	(truncsfbf2): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/extendbfsf.c: New test.
	* gcc.target/i386/avx512bf16-cvtsbh2ss-1.c: Adjust testcase.
---
 gcc/config/i386/avx512bf16intrin.h            |  4 +--
 gcc/config/i386/i386.md                       | 33 ++++++++++++++++++-
 .../gcc.target/i386/avx512bf16-cvtsbh2ss-1.c  |  3 +-
 gcc/testsuite/gcc.target/i386/extendbfsf.c    | 16 +++++++++
 4 files changed, 50 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/extendbfsf.c

diff --git a/gcc/config/i386/avx512bf16intrin.h b/gcc/config/i386/avx512bf16intrin.h
index ea1d0125b3f..4a071bcd75a 100644
--- a/gcc/config/i386/avx512bf16intrin.h
+++ b/gcc/config/i386/avx512bf16intrin.h
@@ -46,9 +46,7 @@ extern __inline float
 __attribute__ ((__gnu_inline__, __always_inline__, __artificial__))
 _mm_cvtsbh_ss (__bf16 __A)
 {
-  union{ float a; unsigned int b;} __tmp;
-  __tmp.b = ((unsigned int)(__A)) << 16;
-  return __tmp.a;
+  return __A;
 }
 
 /* vcvtne2ps2bf16 */
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 01faa911b77..f5215596d44 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4961,6 +4961,21 @@ (define_insn "*extendhf<mode>2"
    (set_attr "prefix" "evex")
    (set_attr "mode" "<MODE>")])
 
+(define_insn "extendbfsf2"
+  [(set (match_operand:SF 0 "register_operand"   "=x,Yw")
+	(float_extend:SF
+	  (match_operand:BF 1 "register_operand" " 0,Yw")))]
+ "TARGET_SSE2"
+ "@
+  pslld\t{$16, %0|%0, 16}
+  vpslld\t{$16, %1, %0|%0, %1, 16}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "TI")
+   (set_attr "memory" "none")])
 
 (define_expand "extend<mode>xf2"
   [(set (match_operand:XF 0 "nonimmediate_operand")
@@ -5177,7 +5192,23 @@ (define_insn "*trunc<mode>hf2"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "evex")
    (set_attr "mode" "HF")])
-\f
+
+(define_insn "truncsfbf2"
+  [(set (match_operand:BF 0 "register_operand"   "=x,Yw")
+	(float_truncate:BF
+	  (match_operand:SF 1 "register_operand" " 0,Yw")))]
+ "TARGET_SSE2"
+ "@
+  psrld\t{$16, %0|%0, 16}
+  vpsrld\t{$16, %1, %0|%0, %1, 16}"
+  [(set_attr "isa" "noavx,avx")
+   (set_attr "type" "sseishft")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix_data16" "1,*")
+   (set_attr "prefix" "orig,vex")
+   (set_attr "mode" "TI")
+   (set_attr "memory" "none")])
+
 ;; Signed conversion to DImode.
 
 (define_expand "fix_truncxfdi2"
diff --git a/gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c b/gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c
index 8e929e6f159..edf30b583b9 100644
--- a/gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c
@@ -1,8 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-mavx512bf16 -O2" } */
 /* { dg-additional-options "-fno-PIE -mfpmath=sse" { target ia32 } } */
-/* { dg-final { scan-assembler-times "sall\[ \\t\]+\[^\{\n\]*16" 1 } } */
-/* { dg-final { scan-assembler-times "movl" 1 } } */
+/* { dg-final { scan-assembler-times "pslld" 1 } } */
 
 #include <immintrin.h>
 
diff --git a/gcc/testsuite/gcc.target/i386/extendbfsf.c b/gcc/testsuite/gcc.target/i386/extendbfsf.c
new file mode 100644
index 00000000000..f1b4c218742
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/extendbfsf.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-msse2 -O2" } */
+/* { dg-final { scan-assembler-times "pslld" 1 } } */
+/* { dg-final { scan-assembler-times "psrld" 1 } } */
+
+float
+extendsfbf (__bf16 a)
+{
+  return a;
+}
+
+__bf16
+truncsfbf (float a)
+{
+  return a;
+}
-- 
2.27.0


^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-11-25  9:18 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-23 12:28 [PATCH] [x86] Fix incorrect implementation for mm_cvtsbh_ss liuhongt
2022-11-23 12:40 ` Jakub Jelinek
2022-11-23 12:59   ` Hongtao Liu
2022-11-24  1:22   ` [PATCH v2] [x86] Fix incorrect _mm_cvtsbh_ss liuhongt
2022-11-24  8:53     ` Jakub Jelinek
2022-11-24 11:30       ` Hongtao Liu
2022-11-25  5:39         ` [PATCH V3] " liuhongt
2022-11-25  9:18           ` Jakub Jelinek

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