[PATCH v2] RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)

[PATCH v2] RISC-V: Add support for AIA ISA extensions (Ssaia and Smaia)

[Christoph Muellner]

From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch adds support for the two AIA ISA extensions Ssaia and Smaia.
They are not relelvant for the compiler, but the assembler might want
to validate the CSRs. Therefore, all this patch does is recognize the
extension name, emit a feature macro (incl. a test).

Changes for v2:
- Imply "ssaia" with "smaia"
- Adding comment to invoke.texi as requested by Palmer

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/common/config/riscv/riscv-common.cc |  4 ++++
 gcc/doc/invoke.texi                     |  4 ++++
 gcc/testsuite/gcc.target/riscv/smaia.c  | 18 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/ssaia.c  | 13 +++++++++++++
 4 files changed, 39 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/smaia.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/ssaia.c

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 4b7f777c103..a1e7d9c3787 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -108,6 +108,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"zhinx", "zhinxmin"},
   {"zhinxmin", "zfinx"},
 
+  {"smaia", "ssaia"},
+
   {NULL, NULL}
 };
 
@@ -219,6 +221,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
 
   {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"smaia", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"ssaia", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svinval", ISA_SPEC_CLASS_NONE, 1, 0},
   {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0},
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 202388b3fb8..a24c6fe2499 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -28662,6 +28662,10 @@ If both @option{-march} and @option{-mcpu=} are not specified, the default for
 this argument is system dependent, users who want a specific architecture
 extensions should specify one explicitly.
 
+Note, that AIA support (@samp{Smaia} and @samp{Ssaia}) is based on an AIA
+specification, which is frozen but contains draft chapters ("Duo-PLIC" and
+"IOMMU Support").
+
 @item -mcpu=@var{processor-string}
 @opindex mcpu
 Use architecture of and optimize the output for the given processor, specified
diff --git a/gcc/testsuite/gcc.target/riscv/smaia.c b/gcc/testsuite/gcc.target/riscv/smaia.c
new file mode 100644
index 00000000000..497b4133c22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/smaia.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_smaia" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_smaia" { target { rv32 } } } */
+
+#ifndef __riscv_smaia
+#error Feature macro not defined
+#endif
+
+// Smaia implies Ssaia
+#ifndef __riscv_ssaia
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/ssaia.c b/gcc/testsuite/gcc.target/riscv/ssaia.c
new file mode 100644
index 00000000000..b20e0eb10f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/ssaia.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_ssaia" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_ssaia" { target { rv32 } } } */
+
+#ifndef __riscv_ssaia
+#error Feature macro not defined
+#endif
+
+int
+foo (int a)
+{
+  return a;
+}
-- 
2.38.1