[PATCH] RISC-V: Change vlmul printing rule

[PATCH] RISC-V: Change vlmul printing rule

[juzhe.zhong]

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

This patch is preparing patch for the following patch (VSETVL PASS)
support since the current vlmul printing rule is not appropriate
information for VSETVL PASS. I split this fix in a single patch.

gcc/ChangeLog:

        * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Pass through VLMUL enum instead of machine mode.
        * config/riscv/riscv-vector-builtins-bases.cc: Ditto.
        * config/riscv/riscv.cc (riscv_print_operand): Print LMUL by enum vlmul instead of machine mode.

---
 gcc/config/riscv/riscv-v.cc                   |  2 +-
 .../riscv/riscv-vector-builtins-bases.cc      |  2 +-
 gcc/config/riscv/riscv.cc                     | 52 ++++++++++---------
 3 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 4992ff2470c..13ee33938bb 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -115,7 +115,7 @@ emit_vlmax_vsetvl (machine_mode vmode)
 
   emit_insn (
     gen_vsetvl_no_side_effects (Pmode, vl, RVV_VLMAX, gen_int_mode (sew, Pmode),
-				gen_int_mode ((unsigned int) vmode, Pmode),
+				gen_int_mode (get_vlmul (vmode), Pmode),
 				const1_rtx, const1_rtx));
   return vl;
 }
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 231b63a610d..ffeb1b25fbc 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -73,7 +73,7 @@ public:
 			 gen_int_mode (GET_MODE_BITSIZE (inner_mode), Pmode));
 
     /* LMUL.  */
-    e.add_input_operand (Pmode, gen_int_mode ((unsigned int) mode, Pmode));
+    e.add_input_operand (Pmode, gen_int_mode (get_vlmul (mode), Pmode));
 
     /* TA.  */
     e.add_input_operand (Pmode, gen_int_mode (1, Pmode));
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2d380aa42cb..ff07d4a3843 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4272,30 +4272,34 @@ riscv_print_operand (FILE *file, rtx op, int letter)
 	  }
 	else if (code == CONST_INT)
 	  {
-	    /* The value in the operand is the unsigned int value
-	       converted from (enum machine_mode).
-	       This RTX is generated as follows:
-
-	       machine_mode mode = XXXmode;
-	       operand = gen_int_mode ((unsigned int)mode, Pmode);
-
-	       So we convert it back into machine_mode and then calculate
-	       the LMUL according to GET_MODE_SIZE.  */
-
-	    machine_mode rvv_mode = (machine_mode) UINTVAL (op);
-	    /* For rvv mask modes, we can not calculate LMUL simpily according
-	       to BYTES_PER_RISCV_VECTOR. When rvv_mode = VNx4BImode.
-	       Set SEW = 8, LMUL = 1 by default if TARGET_MIN_VLEN == 32.
-	       Set SEW = 8, LMUL = 1 / 2 by default if TARGET_MIN_VLEN > 32.  */
-	    bool bool_p = GET_MODE_CLASS (rvv_mode) == MODE_VECTOR_BOOL;
-	    poly_int64 m1_size = BYTES_PER_RISCV_VECTOR;
-	    poly_int64 rvv_size
-	      = bool_p ? GET_MODE_NUNITS (rvv_mode) : GET_MODE_SIZE (rvv_mode);
-	    bool fractional_p = known_lt (rvv_size, BYTES_PER_RISCV_VECTOR);
-	    unsigned int factor
-	      = fractional_p ? exact_div (m1_size, rvv_size).to_constant ()
-			     : exact_div (rvv_size, m1_size).to_constant ();
-	    asm_fprintf (file, "%s%d", fractional_p ? "mf" : "m", factor);
+	    /* If it is a const_int value, it denotes the VLMUL field enum.  */
+	    unsigned int vlmul = UINTVAL (op);
+	    switch (vlmul)
+	      {
+	      case riscv_vector::LMUL_1:
+		asm_fprintf (file, "%s", "m1");
+		break;
+	      case riscv_vector::LMUL_2:
+		asm_fprintf (file, "%s", "m2");
+		break;
+	      case riscv_vector::LMUL_4:
+		asm_fprintf (file, "%s", "m4");
+		break;
+	      case riscv_vector::LMUL_8:
+		asm_fprintf (file, "%s", "m8");
+		break;
+	      case riscv_vector::LMUL_F8:
+		asm_fprintf (file, "%s", "mf8");
+		break;
+	      case riscv_vector::LMUL_F4:
+		asm_fprintf (file, "%s", "mf4");
+		break;
+	      case riscv_vector::LMUL_F2:
+		asm_fprintf (file, "%s", "mf2");
+		break;
+	      default:
+		gcc_unreachable ();
+	      }
 	  }
 	else
 	  output_operand_lossage ("invalid vector constant");
-- 
2.36.3

Re: [PATCH] RISC-V: Change vlmul printing rule

[Jeff Law]

On 12/13/22 23:57, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> This patch is preparing patch for the following patch (VSETVL PASS)
> support since the current vlmul printing rule is not appropriate
> information for VSETVL PASS. I split this fix in a single patch.
> 
> gcc/ChangeLog:
> 
>          * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Pass through VLMUL enum instead of machine mode.
>          * config/riscv/riscv-vector-builtins-bases.cc: Ditto.
>          * config/riscv/riscv.cc (riscv_print_operand): Print LMUL by enum vlmul instead of machine mode.
OK.  Though I suspect your ChangeLog will need to be wrapped to get past 
the commit hooks.

jeff

Re: [PATCH] RISC-V: Change vlmul printing rule

[Kito Cheng]

[-- Attachment #1: Type: text/plain, Size: 869 bytes --]

Commited

Jeff Law via Gcc-patches <gcc-patches@gcc.gnu.org> 於 2022年12月17日 週六 03:51
寫道：

>
>
> On 12/13/22 23:57, juzhe.zhong@rivai.ai wrote:
> > From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> >
> > This patch is preparing patch for the following patch (VSETVL PASS)
> > support since the current vlmul printing rule is not appropriate
> > information for VSETVL PASS. I split this fix in a single patch.
> >
> > gcc/ChangeLog:
> >
> >          * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Pass through
> VLMUL enum instead of machine mode.
> >          * config/riscv/riscv-vector-builtins-bases.cc: Ditto.
> >          * config/riscv/riscv.cc (riscv_print_operand): Print LMUL by
> enum vlmul instead of machine mode.
> OK.  Though I suspect your ChangeLog will need to be wrapped to get past
> the commit hooks.
>
> jeff
>