* [PATCH] RISC-V: Remove DCE in VSETVL PASS
@ 2023-01-18 2:53 juzhe.zhong
2023-01-22 19:37 ` Jeff Law
0 siblings, 1 reply; 2+ messages in thread
From: juzhe.zhong @ 2023-01-18 2:53 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::done): Remove DCE.
* config/riscv/t-riscv: Ditto.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 --
gcc/config/riscv/t-riscv | 2 +-
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index d494369a603..c2a8b44584d 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -87,7 +87,6 @@ along with GCC; see the file COPYING3. If not see
#include "predict.h"
#include "profile-count.h"
#include "riscv-vsetvl.h"
-#include "dce.h"
using namespace rtl_ssa;
using namespace riscv_vector;
@@ -2996,7 +2995,6 @@ pass_vsetvl::done (void)
cleanup_cfg (0);
delete crtl->ssa;
crtl->ssa = nullptr;
- run_fast_dce ();
}
m_vector_manager->release ();
delete m_vector_manager;
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index c95f4aff358..d30e0235356 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -54,7 +54,7 @@ riscv-c.o: $(srcdir)/config/riscv/riscv-c.cc $(CONFIG_H) $(SYSTEM_H) \
riscv-vsetvl.o: $(srcdir)/config/riscv/riscv-vsetvl.cc \
$(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) $(REGS_H) \
$(TARGET_H) tree-pass.h df.h rtl-ssa.h cfgcleanup.h insn-config.h \
- insn-attr.h insn-opinit.h tm-constrs.h cfgrtl.h cfganal.h lcm.h dce.h \
+ insn-attr.h insn-opinit.h tm-constrs.h cfgrtl.h cfganal.h lcm.h \
predict.h profile-count.h $(srcdir)/config/riscv/riscv-vsetvl.h
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
$(srcdir)/config/riscv/riscv-vsetvl.cc
--
2.36.3
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] RISC-V: Remove DCE in VSETVL PASS
2023-01-18 2:53 [PATCH] RISC-V: Remove DCE in VSETVL PASS juzhe.zhong
@ 2023-01-22 19:37 ` Jeff Law
0 siblings, 0 replies; 2+ messages in thread
From: Jeff Law @ 2023-01-22 19:37 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches; +Cc: kito.cheng, palmer
On 1/17/23 19:53, juzhe.zhong@rivai.ai wrote:
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vsetvl.cc (pass_vsetvl::done): Remove DCE.
> * config/riscv/t-riscv: Ditto.
OK. Presumably this is because the pass is now placed before DCE.
Jeff
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-01-22 19:37 ` Jeff Law
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