* [PATCH] RISC-V: Add vadc.vvm/vadc.vxm C API tests
@ 2023-02-08 2:32 juzhe.zhong
0 siblings, 0 replies; only message in thread
From: juzhe.zhong @ 2023-02-08 2:32 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vadc-1.c: New test.
* gcc.target/riscv/rvv/base/vadc-2.c: New test.
* gcc.target/riscv/rvv/base/vadc-3.c: New test.
* gcc.target/riscv/rvv/base/vadc-4.c: New test.
* gcc.target/riscv/rvv/base/vadc_vvm-1.c: New test.
* gcc.target/riscv/rvv/base/vadc_vvm-2.c: New test.
* gcc.target/riscv/rvv/base/vadc_vvm-3.c: New test.
* gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c: New test.
---
.../gcc.target/riscv/rvv/base/vadc-1.c | 27 ++
.../gcc.target/riscv/rvv/base/vadc-2.c | 48 +++
.../gcc.target/riscv/rvv/base/vadc-3.c | 78 +++++
.../gcc.target/riscv/rvv/base/vadc-4.c | 79 +++++
.../gcc.target/riscv/rvv/base/vadc_vvm-1.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vadc_vvm-2.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vadc_vvm-3.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c | 292 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vadc_vxm_rv32-1.c | 289 +++++++++++++++++
.../riscv/rvv/base/vadc_vxm_rv32-2.c | 289 +++++++++++++++++
.../riscv/rvv/base/vadc_vxm_rv32-3.c | 289 +++++++++++++++++
.../riscv/rvv/base/vadc_vxm_rv64-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vadc_vxm_rv64-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vadc_vxm_rv64-3.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vadc_vxm_tu_rv32-1.c | 289 +++++++++++++++++
.../riscv/rvv/base/vadc_vxm_tu_rv32-2.c | 289 +++++++++++++++++
.../riscv/rvv/base/vadc_vxm_tu_rv32-3.c | 289 +++++++++++++++++
.../riscv/rvv/base/vadc_vxm_tu_rv64-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vadc_vxm_tu_rv64-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vadc_vxm_tu_rv64-3.c | 292 ++++++++++++++++++
22 files changed, 5470 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c
new file mode 100644
index 00000000000..ed3c4edc858
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out)
+{
+ vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vadc_vvm_i32m1 (v2, v2, mask, 4);
+ vint32m1_t v4 = __riscv_vadc_vvm_i32m1_tu (v3, v2, v2, mask, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+void f2 (void * in, void *out)
+{
+ vbool32_t mask = *(vbool32_t*)in;
+ asm volatile ("":::"memory");
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4);
+ vint32m1_t v3 = __riscv_vadc_vvm_i32m1 (v2, v2, mask, 4);
+ vint32m1_t v4 = __riscv_vadc_vvm_i32m1_tu (v3, v2, v2, mask, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {vmv} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c
new file mode 100644
index 00000000000..df83902f4a5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-2.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+#include "riscv_vector.h"
+
+void f1 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vadc_vxm_i32m1 (v2, -16, mask, 4);
+ vint32m1_t v4 = __riscv_vadc_vxm_i32m1_tu (v3, v2, -16, mask, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+void f2 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vadc_vxm_i32m1 (v2, 15, mask, 4);
+ vint32m1_t v4 = __riscv_vadc_vxm_i32m1_tu (v3, v2, 15, mask, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+void f3 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vadc_vxm_i32m1 (v2, -17, mask, 4);
+ vint32m1_t v4 = __riscv_vadc_vxm_i32m1_tu (v3, v2, -17, mask, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+void f4 (void * in, void *out, int32_t x)
+{
+ vbool32_t mask = __riscv_vlm_v_b32 (in + 100, 4);
+ vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4);
+ vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4);
+ vint32m1_t v3 = __riscv_vadc_vxm_i32m1 (v2, 16, mask, 4);
+ vint32m1_t v4 = __riscv_vadc_vxm_i32m1_tu (v3, v2, 16, mask, 4);
+ __riscv_vse32_v_i32m1 (out, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 4 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c
new file mode 100644
index 00000000000..a0c2e0de8d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-3.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, -16, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, -16, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f1 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, 15, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, 15, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f2 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, -17, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, -17, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f3 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, 16, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, 16, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f4 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, 0xAAAAAAAA, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, 0xAAAAAAAA, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f5 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f6 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, x, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, x, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 10 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c
new file mode 100644
index 00000000000..550834c1d30
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc-4.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+
+#include "riscv_vector.h"
+
+void f0 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, -16, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, -16, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f1 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, 15, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, 15, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f2 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, -17, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, -17, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f3 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, 16, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, 16, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f4 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, 0xAAAAAAA, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, 0xAAAAAAA, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f5 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+void f6 (void * in, void *out, int64_t x, int n)
+{
+ vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
+ vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
+ vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
+ vint64m1_t v3 = __riscv_vadc_vxm_i64m1 (v2, x, mask, 4);
+ vint64m1_t v4 = __riscv_vadc_vxm_i64m1 (v3, x, mask, 4);
+ __riscv_vse64_v_i64m1 (out + 2, v4, 4);
+}
+
+/* { dg-final { scan-assembler-times {vadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*-16,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vim\s+v[0-9]+,\s*v[0-9]+,\s*15,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 6 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-1.c
new file mode 100644
index 00000000000..dc9bf5c2c9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf8(op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf4(op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf2(op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m1(op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m2(op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m4(op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m8(op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf4(op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf2(op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m1(op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m2(op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m4(op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m8(op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32mf2(op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m1(op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m2(op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m4(op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m8(op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m1(op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m2(op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m4(op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m8(op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf8(op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf4(op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf2(op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m1(op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m2(op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m4(op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m8(op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf4(op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf2(op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m1(op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m2(op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m4(op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m8(op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32mf2(op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m1(op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m2(op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m4(op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m8(op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m1(op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m2(op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m4(op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m8(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-2.c
new file mode 100644
index 00000000000..90e36172280
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf8(op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf4(op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf2(op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m1(op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m2(op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m4(op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m8(op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf4(op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf2(op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m1(op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m2(op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m4(op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m8(op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32mf2(op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m1(op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m2(op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m4(op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m8(op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m1(op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m2(op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m4(op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m8(op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf8(op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf4(op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf2(op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m1(op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m2(op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m4(op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m8(op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf4(op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf2(op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m1(op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m2(op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m4(op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m8(op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32mf2(op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m1(op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m2(op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m4(op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m8(op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m1(op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m2(op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m4(op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m8(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-3.c
new file mode 100644
index 00000000000..c86399e4208
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vvm_i8mf8(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf8(op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc_vvm_i8mf4(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf4(op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc_vvm_i8mf2(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf2(op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc_vvm_i8m1(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m1(op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc_vvm_i8m2(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m2(op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc_vvm_i8m4(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m4(op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc_vvm_i8m8(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m8(op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc_vvm_i16mf4(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf4(op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc_vvm_i16mf2(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf2(op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc_vvm_i16m1(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m1(op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc_vvm_i16m2(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m2(op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc_vvm_i16m4(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m4(op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc_vvm_i16m8(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m8(op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc_vvm_i32mf2(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32mf2(op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc_vvm_i32m1(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m1(op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc_vvm_i32m2(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m2(op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc_vvm_i32m4(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m4(op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc_vvm_i32m8(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m8(op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc_vvm_i64m1(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m1(op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc_vvm_i64m2(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m2(op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc_vvm_i64m4(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m4(op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc_vvm_i64m8(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m8(op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vvm_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf8(op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vvm_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf4(op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vvm_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf2(op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc_vvm_u8m1(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m1(op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc_vvm_u8m2(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m2(op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc_vvm_u8m4(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m4(op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc_vvm_u8m8(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m8(op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vvm_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf4(op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vvm_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf2(op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc_vvm_u16m1(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m1(op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc_vvm_u16m2(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m2(op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc_vvm_u16m4(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m4(op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc_vvm_u16m8(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m8(op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vvm_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32mf2(op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc_vvm_u32m1(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m1(op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc_vvm_u32m2(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m2(op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc_vvm_u32m4(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m4(op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc_vvm_u32m8(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m8(op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc_vvm_u64m1(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m1(op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc_vvm_u64m2(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m2(op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc_vvm_u64m4(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m4(op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc_vvm_u64m8(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m8(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c
new file mode 100644
index 00000000000..efca6b31c0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vvm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc_vvm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc_vvm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc_vvm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc_vvm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc_vvm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc_vvm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc_vvm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc_vvm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc_vvm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc_vvm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc_vvm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc_vvm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc_vvm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc_vvm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc_vvm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc_vvm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc_vvm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc_vvm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc_vvm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc_vvm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc_vvm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vvm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vvm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vvm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc_vvm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc_vvm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc_vvm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc_vvm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vvm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vvm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc_vvm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc_vvm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc_vvm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc_vvm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vvm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc_vvm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc_vvm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc_vvm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc_vvm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc_vvm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc_vvm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc_vvm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc_vvm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c
new file mode 100644
index 00000000000..94db1d88e2f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vvm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc_vvm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc_vvm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc_vvm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc_vvm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc_vvm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc_vvm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc_vvm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc_vvm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc_vvm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc_vvm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc_vvm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc_vvm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc_vvm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc_vvm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc_vvm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc_vvm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc_vvm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc_vvm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc_vvm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc_vvm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc_vvm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vvm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vvm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vvm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc_vvm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc_vvm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc_vvm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc_vvm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vvm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vvm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc_vvm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc_vvm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc_vvm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc_vvm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vvm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc_vvm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc_vvm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc_vvm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc_vvm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc_vvm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc_vvm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc_vvm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc_vvm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c
new file mode 100644
index 00000000000..ae885200952
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vvm_tu-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vvm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc_vvm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc_vvm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc_vvm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc_vvm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc_vvm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc_vvm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i8m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc_vvm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc_vvm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc_vvm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc_vvm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc_vvm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc_vvm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i16m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc_vvm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc_vvm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc_vvm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc_vvm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc_vvm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i32m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc_vvm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc_vvm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc_vvm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc_vvm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_i64m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vvm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vvm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vvm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc_vvm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc_vvm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc_vvm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc_vvm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u8m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vvm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vvm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc_vvm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc_vvm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc_vvm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc_vvm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u16m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vvm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc_vvm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc_vvm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc_vvm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc_vvm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u32m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc_vvm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc_vvm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc_vvm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc_vvm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vvm_u64m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c
new file mode 100644
index 00000000000..6f1a9ff8c89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8(op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4(op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2(op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1(op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2(op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4(op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8(op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4(op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2(op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1(op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2(op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4(op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8(op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2(op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1(op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2(op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4(op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8(op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1(op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2(op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4(op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8(op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8(op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4(op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2(op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1(op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2(op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4(op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8(op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4(op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2(op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1(op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2(op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4(op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8(op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2(op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1(op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2(op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4(op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8(op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1(op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2(op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4(op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c
new file mode 100644
index 00000000000..4821e55ef97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8(op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4(op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2(op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1(op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2(op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4(op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8(op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4(op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2(op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1(op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2(op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4(op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8(op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2(op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1(op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2(op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4(op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8(op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1(op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2(op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4(op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8(op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8(op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4(op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2(op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1(op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2(op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4(op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8(op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4(op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2(op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1(op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2(op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4(op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8(op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2(op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1(op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2(op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4(op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8(op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1(op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2(op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4(op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c
new file mode 100644
index 00000000000..c7650fc8bb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8(op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4(op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2(op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1(op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2(op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4(op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8(op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4(op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2(op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1(op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2(op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4(op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8(op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2(op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1(op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2(op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4(op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8(op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1(op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2(op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4(op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8(op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8(op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4(op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2(op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1(op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2(op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4(op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8(op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4(op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2(op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1(op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2(op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4(op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8(op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2(op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1(op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2(op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4(op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8(op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1(op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2(op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4(op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c
new file mode 100644
index 00000000000..15662f35f90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8(op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4(op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2(op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1(op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2(op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4(op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8(op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4(op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2(op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1(op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2(op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4(op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8(op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2(op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1(op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2(op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4(op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8(op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1(op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2(op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4(op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8(op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8(op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4(op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2(op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1(op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2(op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4(op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8(op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4(op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2(op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1(op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2(op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4(op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8(op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2(op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1(op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2(op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4(op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8(op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1(op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2(op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4(op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8(op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c
new file mode 100644
index 00000000000..4816316519a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8(op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4(op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2(op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1(op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2(op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4(op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8(op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4(op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2(op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1(op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2(op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4(op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8(op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2(op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1(op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2(op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4(op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8(op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1(op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2(op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4(op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8(op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8(op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4(op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2(op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1(op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2(op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4(op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8(op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4(op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2(op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1(op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2(op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4(op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8(op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2(op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1(op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2(op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4(op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8(op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1(op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2(op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4(op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8(op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c
new file mode 100644
index 00000000000..3aa0d4cbcbf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8(op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4(op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2(op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1(op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2(op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4(op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8(op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4(op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2(op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1(op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2(op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4(op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8(op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2(op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1(op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2(op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4(op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8(op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1(op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2(op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4(op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8(op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8(op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4(op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2(op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1(op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2(op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4(op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8(op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4(op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2(op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1(op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2(op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4(op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8(op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2(op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1(op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2(op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4(op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8(op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1(op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2(op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4(op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8(op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c
new file mode 100644
index 00000000000..fd4537d373a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c
new file mode 100644
index 00000000000..e4a0a03aa10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c
new file mode 100644
index 00000000000..208abf6d892
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c
new file mode 100644
index 00000000000..b28647f2b4e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8_tu(maskedoff,op1,op2,carryin,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c
new file mode 100644
index 00000000000..088061a7b60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8_tu(maskedoff,op1,op2,carryin,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c
new file mode 100644
index 00000000000..911707c261a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vadc_vxm_i8mf8_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf4_t test___riscv_vadc_vxm_i8mf4_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8mf2_t test___riscv_vadc_vxm_i8mf2_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m1_t test___riscv_vadc_vxm_i8m1_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m2_t test___riscv_vadc_vxm_i8m2_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m4_t test___riscv_vadc_vxm_i8m4_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint8m8_t test___riscv_vadc_vxm_i8m8_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i8m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf4_t test___riscv_vadc_vxm_i16mf4_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16mf2_t test___riscv_vadc_vxm_i16mf2_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m1_t test___riscv_vadc_vxm_i16m1_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m2_t test___riscv_vadc_vxm_i16m2_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m4_t test___riscv_vadc_vxm_i16m4_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint16m8_t test___riscv_vadc_vxm_i16m8_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i16m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32mf2_t test___riscv_vadc_vxm_i32mf2_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m1_t test___riscv_vadc_vxm_i32m1_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m2_t test___riscv_vadc_vxm_i32m2_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m4_t test___riscv_vadc_vxm_i32m4_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint32m8_t test___riscv_vadc_vxm_i32m8_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i32m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m1_t test___riscv_vadc_vxm_i64m1_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m2_t test___riscv_vadc_vxm_i64m2_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m4_t test___riscv_vadc_vxm_i64m4_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vint64m8_t test___riscv_vadc_vxm_i64m8_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_i64m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf8_t test___riscv_vadc_vxm_u8mf8_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf4_t test___riscv_vadc_vxm_u8mf4_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8mf2_t test___riscv_vadc_vxm_u8mf2_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m1_t test___riscv_vadc_vxm_u8m1_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m2_t test___riscv_vadc_vxm_u8m2_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m4_t test___riscv_vadc_vxm_u8m4_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint8m8_t test___riscv_vadc_vxm_u8m8_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u8m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf4_t test___riscv_vadc_vxm_u16mf4_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16mf2_t test___riscv_vadc_vxm_u16mf2_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m1_t test___riscv_vadc_vxm_u16m1_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m2_t test___riscv_vadc_vxm_u16m2_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m4_t test___riscv_vadc_vxm_u16m4_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint16m8_t test___riscv_vadc_vxm_u16m8_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u16m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32mf2_t test___riscv_vadc_vxm_u32mf2_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32mf2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m1_t test___riscv_vadc_vxm_u32m1_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m2_t test___riscv_vadc_vxm_u32m2_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m4_t test___riscv_vadc_vxm_u32m4_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint32m8_t test___riscv_vadc_vxm_u32m8_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u32m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m1_t test___riscv_vadc_vxm_u64m1_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m1_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m2_t test___riscv_vadc_vxm_u64m2_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m2_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m4_t test___riscv_vadc_vxm_u64m4_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m4_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+vuint64m8_t test___riscv_vadc_vxm_u64m8_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl)
+{
+ return __riscv_vadc_vxm_u64m8_tu(maskedoff,op1,op2,carryin,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+} 2 } } */
--
2.36.1
^ permalink raw reply [flat|nested] only message in thread
only message in thread, other threads:[~2023-02-08 2:32 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-08 2:32 [PATCH] RISC-V: Add vadc.vvm/vadc.vxm C API tests juzhe.zhong
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).