* [PATCH] RISC-V: Add vssra.vx C API tests
@ 2023-02-10 6:27 juzhe.zhong
0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-10 6:27 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vssra_vx-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_m-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c: New test.
---
.../gcc.target/riscv/rvv/base/vssra_vx-1.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx-2.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx-3.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_m-1.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_m-2.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_m-3.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_mu-1.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_mu-2.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_mu-3.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_tu-1.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_tu-2.c | 160 ++++++++++++++++++
.../gcc.target/riscv/rvv/base/vssra_vx_tu-3.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vssra_vx_tum-1.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vssra_vx_tum-2.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vssra_vx_tum-3.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vssra_vx_tumu-1.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vssra_vx_tumu-2.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vssra_vx_tumu-3.c | 160 ++++++++++++++++++
18 files changed, 2880 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c
new file mode 100644
index 00000000000..2feeadcd933
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4(op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4(op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4(op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8(op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1(op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2(op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4(op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8(op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-2.c
new file mode 100644
index 00000000000..1981278745c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4(op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4(op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4(op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8(op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1(op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2(op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4(op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8(op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-3.c
new file mode 100644
index 00000000000..131be178dcf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4(op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4(op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4(op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8(op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1(op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2(op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4(op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8(op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-1.c
new file mode 100644
index 00000000000..cf0d6d1f53b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_m(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_m(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_m(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_m(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_m(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_m(mask,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_m(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_m(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_m(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_m(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_m(mask,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_m(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_m(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_m(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_m(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_m(mask,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_m(mask,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_m(mask,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_m(mask,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_m(mask,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_m(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-2.c
new file mode 100644
index 00000000000..5ea70337869
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_m(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_m(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_m(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_m(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_m(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_m(mask,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_m(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_m(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_m(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_m(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_m(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_m(mask,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_m(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_m(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_m(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_m(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_m(mask,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_m(mask,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_m(mask,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_m(mask,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_m(mask,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_m(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-3.c
new file mode 100644
index 00000000000..15d3e38d5cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_m-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_m(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_m(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_m(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_m(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_m(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_m(mask,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_m(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_m(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_m(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_m(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_m(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_m(mask,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_m(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_m(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_m(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_m(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_m(mask,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_m(mask,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_m(mask,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_m(mask,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_m(mask,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_m(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-1.c
new file mode 100644
index 00000000000..0759d0c9181
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-2.c
new file mode 100644
index 00000000000..895beb1c1a0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-3.c
new file mode 100644
index 00000000000..b41176a6260
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_mu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-1.c
new file mode 100644
index 00000000000..2a6484bd282
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tu(merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tu(merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tu(merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tu(merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tu(merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tu(merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tu(merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-2.c
new file mode 100644
index 00000000000..fff92df0bb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tu(merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tu(merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tu(merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tu(merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tu(merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tu(merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tu(merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-3.c
new file mode 100644
index 00000000000..79a34034a82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tu(merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tu(merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tu(merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tu(merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tu(merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tu(merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tu(merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-1.c
new file mode 100644
index 00000000000..976aea2b0db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-2.c
new file mode 100644
index 00000000000..ccc52a48e6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-3.c
new file mode 100644
index 00000000000..6bb2fac60c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tum-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c
new file mode 100644
index 00000000000..e7c9632a204
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c
new file mode 100644
index 00000000000..cc917e6f4c6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c
new file mode 100644
index 00000000000..55dd342be66
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssra_vx_tumu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i8m8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i16m8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i32m8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_vx_i64m8_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
--
2.36.3
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH] RISC-V: Add vssra.vx C++ API tests
@ 2023-02-10 6:49 juzhe.zhong
0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-10 6:49 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vssra_vx-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_mu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tu-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tum-3.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vssra_vx_tumu-3.C: New test.
---
.../g++.target/riscv/rvv/base/vssra_vx-1.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vssra_vx-2.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vssra_vx-3.C | 314 ++++++++++++++++++
.../g++.target/riscv/rvv/base/vssra_vx_mu-1.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_mu-2.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_mu-3.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_tu-1.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_tu-2.C | 160 +++++++++
.../g++.target/riscv/rvv/base/vssra_vx_tu-3.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tum-1.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tum-2.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tum-3.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tumu-1.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tumu-2.C | 160 +++++++++
.../riscv/rvv/base/vssra_vx_tumu-3.C | 160 +++++++++
15 files changed, 2862 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
new file mode 100644
index 00000000000..23985cd3ebb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,vl);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C
new file mode 100644
index 00000000000..c7f36db94f8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,31);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C
new file mode 100644
index 00000000000..c5ff47ae379
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra(vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra(vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra(vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra(vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra(vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra(vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra(vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra(vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra(vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra(vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra(vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra(vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra(vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra(vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra(vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra(vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra(vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra(vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra(vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra(vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra(vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra(vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(op1,shift,32);
+}
+
+
+vint8mf8_t test___riscv_vssra(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C
new file mode 100644
index 00000000000..2490257db8b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C
new file mode 100644
index 00000000000..a335a9591ed
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C
new file mode 100644
index 00000000000..2e70517cade
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C
new file mode 100644
index 00000000000..4b52410c216
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C
new file mode 100644
index 00000000000..63076738b1f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C
new file mode 100644
index 00000000000..111e3a06084
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C
new file mode 100644
index 00000000000..b015812d2c6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C
new file mode 100644
index 00000000000..80247efaf83
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C
new file mode 100644
index 00000000000..50f075811ae
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C
new file mode 100644
index 00000000000..632fb380f59
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C
new file mode 100644
index 00000000000..1249c6cfd8f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C
new file mode 100644
index 00000000000..90cb29e8e4e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vssra_vx_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vssra_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vssra_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vssra_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vssra_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vssra_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vssra_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vssra_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vssra_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vssra_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vssra_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vssra_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vssra_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vssra_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vssra_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vssra_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vssra_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vssra_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vssra_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vssra_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vssra_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vssra_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vssra_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+ return __riscv_vssra_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vssra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
--
2.36.3
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2023-02-10 6:27 [PATCH] RISC-V: Add vssra.vx C API tests juzhe.zhong
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