public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
* [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension
@ 2023-02-13 10:45 Liao Shihua
  2023-02-13 10:45 ` [PATCH 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-13 10:45 UTC (permalink / raw)
  To: gcc-patches
  Cc: palmer, kito.cheng, jiawei, jeff, mjos, ben.marshall, Liao Shihua

    This patch implement RISC-V Scalar Cryptography extension.
    It includes machine descrption , intrinsic and testcase .

Liao Shihua (5):
  Add prototypes for RISC-V Crypto built-in functions
  Implement ZBKB, ZBKC and ZBKX extensions
  Implement ZKND and ZKNE extensions
  Implement ZKNH extensions
  Implement ZKSH and ZKSED extensions

 gcc/config.gcc                                |   2 +-
 gcc/config/riscv/bitmanip.md                  |  20 +-
 gcc/config/riscv/constraints.md               |   8 +
 gcc/config/riscv/crypto.md                    | 437 ++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc            |  26 ++
 gcc/config/riscv/riscv-crypto.def             |  94 ++++
 gcc/config/riscv/riscv-ftypes.def             |  10 +
 gcc/config/riscv/riscv.md                     |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h        | 218 +++++++++
 gcc/testsuite/gcc.target/riscv/zbkb32.c       |  36 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c       |  28 ++
 gcc/testsuite/gcc.target/riscv/zbkc32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c       |  17 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c       |  19 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zknd32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c       |  36 ++
 gcc/testsuite/gcc.target/riscv/zkne32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zkne64.c       |  30 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 ++
 .../gcc.target/riscv/zknh-sha512-32.c         |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c         |  31 ++
 gcc/testsuite/gcc.target/riscv/zksed.c        |  20 +
 gcc/testsuite/gcc.target/riscv/zksh.c         |  19 +
 24 files changed, 1187 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions
  2023-02-13 10:45 [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
@ 2023-02-13 10:45 ` Liao Shihua
  2023-02-13 10:45 ` [PATCH 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Liao Shihua
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-13 10:45 UTC (permalink / raw)
  To: gcc-patches
  Cc: palmer, kito.cheng, jiawei, jeff, mjos, ben.marshall, Liao Shihua

    Add prototypes for RISC-V Crypto built-in functions .

gcc/ChangeLog:

        * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2): New enumeration identifier.
        (RISCV_FTYPE_NAME3): Likewise.
        (RISCV_ATYPE_QI): New Argument types.
        (RISCV_ATYPE_HI): Likewise.
        (RISCV_FTYPE_ATYPES2): New RISCV_ATYPE.
        (RISCV_FTYPE_ATYPES3): Likewise.
        * config/riscv/riscv-ftypes.def (2): New Definitions of prototypes.
        (3):Likewise
---
 gcc/config/riscv/riscv-builtins.cc |  8 ++++++++
 gcc/config/riscv/riscv-ftypes.def  | 10 ++++++++++
 2 files changed, 18 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..ded91e17554 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -42,6 +42,8 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -132,6 +134,8 @@ AVAIL (always,     (!0))
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_QI intQI_type_node
+#define RISCV_ATYPE_HI intHI_type_node
 #define RISCV_ATYPE_SI intSI_type_node
 #define RISCV_ATYPE_DI intDI_type_node
 #define RISCV_ATYPE_VOID_PTR ptr_type_node
@@ -142,6 +146,10 @@ AVAIL (always,     (!0))
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 3a40c33e7c2..3b518195a29 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -32,3 +32,13 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, QI, QI))
+DEF_RISCV_FTYPE (2, (SI, HI, HI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, QI, QI))
+DEF_RISCV_FTYPE (2, (DI, HI, HI))
+DEF_RISCV_FTYPE (2, (DI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
+DEF_RISCV_FTYPE (3, (DI, DI, DI, SI))
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions
  2023-02-13 10:45 [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
  2023-02-13 10:45 ` [PATCH 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
@ 2023-02-13 10:45 ` Liao Shihua
  2023-02-13 10:45 ` [PATCH 3/5] RISC-V: Implement ZKND and ZKNE extensions Liao Shihua
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-13 10:45 UTC (permalink / raw)
  To: gcc-patches
  Cc: palmer, kito.cheng, jiawei, jeff, mjos, ben.marshall, Liao Shihua

   Implement ZBKB, ZBKC and ZBKX extensions. 
   ZBKB is Bitmanip instructions for Cryptography.
   ZBKC is Carry-less multiply instructions.
   ZBKX is Crossbar permutation instructions.
   Only add Machine description and intrinsics of these instructions which are not defined in the first Bitmanip ratification package.
   If them defined in Bitmanip extension, it will generate by Manchine description in bitmanip.md.

gcc/ChangeLog:

        * config.gcc: Add intrinsics header in extra_headers.
        * config/riscv/bitmanip.md: Add TARGET_ZBKB if these instructions are included in ZBKB extension.
        * config/riscv/riscv-builtins.cc (AVAIL): Add ZBKB's,ZBKC's,ZBKX's AVAIL. 
        * config/riscv/riscv.md: include crypto.md.
        * config/riscv/crypto.md: Scalar Cryptography Machine description file.
        * config/riscv/riscv-crypto.def: Scalar Cryptography built-in function file.
        * config/riscv/riscv_scalar_crypto.h: Scalar Cryptography intrinsics header.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zbkb32.c: New test.
        * gcc.target/riscv/zbkb64.c: New test.
        * gcc.target/riscv/zbkc32.c: New test.
        * gcc.target/riscv/zbkc64.c: New test.
        * gcc.target/riscv/zbkx32.c: New test.
        * gcc.target/riscv/zbkx64.c: New test.

---
 gcc/config.gcc                          |   2 +-
 gcc/config/riscv/bitmanip.md            |  20 ++--
 gcc/config/riscv/crypto.md              | 133 ++++++++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc      |   7 ++
 gcc/config/riscv/riscv-crypto.def       |  46 ++++++++
 gcc/config/riscv/riscv.md               |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h  | 106 +++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/zbkb32.c |  36 +++++++
 gcc/testsuite/gcc.target/riscv/zbkb64.c |  28 +++++
 gcc/testsuite/gcc.target/riscv/zbkc32.c |  18 ++++
 gcc/testsuite/gcc.target/riscv/zbkc64.c |  17 +++
 gcc/testsuite/gcc.target/riscv/zbkx32.c |  19 ++++
 gcc/testsuite/gcc.target/riscv/zbkx64.c |  18 ++++
 13 files changed, 442 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c

diff --git a/gcc/config.gcc b/gcc/config.gcc
index f0958e1c959..951b92b2028 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -532,7 +532,7 @@ riscv*)
 	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o riscv-selftests.o riscv-v.o riscv-vsetvl.o"
 	extra_objs="${extra_objs} riscv-vector-builtins.o riscv-vector-builtins-shapes.o riscv-vector-builtins-bases.o"
 	d_target_objs="riscv-d.o"
-	extra_headers="riscv_vector.h"
+	extra_headers="riscv_vector.h riscv_scalar_crypto.h"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.cc"
 	target_gtfiles="$target_gtfiles \$(srcdir)/config/riscv/riscv-vector-builtins.h"
 	;;
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 14d18edbe62..f076ba35832 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -189,7 +189,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
         (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
                             (match_operand:X 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "<insn>n\t%0,%2,%1"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -203,7 +203,7 @@
 			       (const_int 0)))
 		(match_operand:DI 2 "register_operand")))
    (clobber (match_operand:DI 3 "register_operand"))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
    (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 
@@ -211,7 +211,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
         (not:X (xor:X (match_operand:X 1 "register_operand" "r")
                       (match_operand:X 2 "register_operand" "r"))))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "xnor\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -277,7 +277,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
 		     (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "ror%i2%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -285,7 +285,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "ror%i2\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -293,7 +293,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 				     (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rorw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -301,7 +301,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotate:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rol%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -309,7 +309,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(rotate:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rol\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -317,7 +317,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
 				   (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rolw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -332,7 +332,7 @@
 (define_insn "bswap<mode>2"
   [(set (match_operand:X 0 "register_operand" "=r")
         (bswap:X (match_operand:X 1 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rev8\t%0,%1"
   [(set_attr "type" "bitmanip")])
 
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
new file mode 100644
index 00000000000..048db920bb6
--- /dev/null
+++ b/gcc/config/riscv/crypto.md
@@ -0,0 +1,133 @@
+;; Machine description for RISC-V Scalar Cryptography extensions.
+;; Copyright (C) 2023 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_c_enum "unspec" [
+    ;; ZBKB unspecs
+    UNSPEC_BREV8
+    UNSPEC_ZIP
+    UNSPEC_UNZIP
+    UNSPEC_PACK
+    UNSPEC_PACKH
+    UNSPEC_PACKW
+
+    ;; ZBKC unspecs
+    UNSPEC_CLMUL
+    UNSPEC_CLMULH
+
+    ;; ZBKX unspecs
+    UNSPEC_XPERM8
+    UNSPEC_XPERM4
+
+
+])
+
+;; ZBKB extension
+(define_insn "riscv_brev8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_BREV8))]
+  "TARGET_ZBKB"
+  "brev8\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_zip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+                  UNSPEC_ZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "zip\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_unzip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+                  UNSPEC_UNZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "unzip\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_pack_<X:mode><HISI:mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:HISI 1 "register_operand" "r")
+                  (match_operand:HISI 2 "register_operand" "r")]
+                  UNSPEC_PACK))]
+  "TARGET_ZBKB"
+  "pack\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_packh_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:QI 1 "register_operand" "r")
+                  (match_operand:QI 2 "register_operand" "r")]
+                  UNSPEC_PACKH))]
+  "TARGET_ZBKB"
+  "packh\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_packw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:HI 1 "register_operand" "r")
+                  (match_operand:HI 2 "register_operand" "r")]
+                  UNSPEC_PACKW))]
+  "TARGET_ZBKB && TARGET_64BIT"
+  "packw\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZBKC extension
+
+(define_insn "riscv_clmul_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_CLMUL))]
+  "TARGET_ZBKC"
+  "clmul\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_clmulh_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_CLMULH))]
+  "TARGET_ZBKC"
+  "clmulh\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZBKX extension
+
+(define_insn "riscv_xperm4_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM4))]
+  "TARGET_ZBKX"
+  "xperm4\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_xperm8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM8))]
+  "TARGET_ZBKX"
+  "xperm8\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+
+
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index ded91e17554..e9c2d92f0d3 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -100,6 +100,12 @@ AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
 AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
+AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
+AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT)
+AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT)
+AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
+AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
@@ -152,6 +158,7 @@ AVAIL (always,     (!0))
   RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
+  #include "riscv-crypto.def"
   #include "riscv-cmo.def"
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def
new file mode 100644
index 00000000000..40fbb9e43cb
--- /dev/null
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -0,0 +1,46 @@
+/* Builtin functions for RISC-V Scalar Cryptography extensions.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+// ZBKB
+RISCV_BUILTIN (pack_sihi, "pack", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_HI_HI, crypto_zbkb32),
+RISCV_BUILTIN (pack_disi, "pack", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_SI_SI, crypto_zbkb64),
+
+RISCV_BUILTIN (packh_si, "packh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_QI_QI, crypto_zbkb32),
+RISCV_BUILTIN (packh_di, "packh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_QI_QI, crypto_zbkb64),
+
+RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_HI_HI, crypto_zbkb64),
+
+RISCV_BUILTIN (zip, "zip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+RISCV_BUILTIN (unzip, "unzip_32", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+
+RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zbkb64),
+
+// ZBKC
+RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+
+// ZBKX
+RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c8adc5af5d2..c424a82dcbd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -242,6 +242,7 @@
 ;; bitmanip	bit manipulation instructions
 ;; rotate   rotation instructions
 ;; atomic   atomic instructions
+;; crypto   cryptography instructions
 ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
 ;; rdvlenb     vector byte length vlenb csrr read
 ;; rdvl        vector length vl csrr read
@@ -333,7 +334,7 @@
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
-   atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
    vldux,vldox,vstux,vstox,vldff,vldr,vstr,
    vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
    vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
@@ -3092,3 +3093,4 @@
 (include "generic.md")
 (include "sifive-7.md")
 (include "vector.md")
+(include "crypto.md")
diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h
new file mode 100644
index 00000000000..76c0a4f0436
--- /dev/null
+++ b/gcc/config/riscv/riscv_scalar_crypto.h
@@ -0,0 +1,106 @@
+/* RISC-V Scalar Cryptography Extension intrinsics include file.
+   Copyright (C) 2022-2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef _RISCV_SCALAR_CRYPTO_H
+#define _RISCV_SCALAR_CRYPTO_H
+#endif	//	_RISCV_SCALAR_CRYPTO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(__riscv_xlen) && !defined(RVKINTRIN_EMULATE)
+#warning "Target is not RISC-V. Enabling insecure emulation."
+#define RVKINTRIN_EMULATE 1
+#endif
+
+//	intrinsics via compiler builtins
+#include <stdint.h>
+#define _RVK_INTRIN_IMPL(s) __builtin_riscv_##s
+
+
+//	set type if not already set
+#if !defined(RVKINTRIN_RV32) && !defined(RVKINTRIN_RV64)
+#if __riscv_xlen == 32
+#define RVKINTRIN_RV32
+#elif __riscv_xlen == 64
+#define RVKINTRIN_RV64
+#else
+#error "__riscv_xlen not valid."
+#endif
+#endif
+
+//	Mappings to implementation
+
+//	=== (mapping)	Zbkb:	Bitmanipulation instructions for Cryptography
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t __riscv_pack(int16_t rs1, int16_t rs2)
+	{ return _RVK_INTRIN_IMPL(pack)(rs1, rs2); }			//	PACK
+
+static inline int32_t __riscv_packh(int8_t rs1, int8_t rs2)
+	{ return _RVK_INTRIN_IMPL(packh)(rs1, rs2); }			//	PACKH
+#endif
+
+#ifdef RVKINTRIN_RV64
+static inline int64_t __riscv_pack(int32_t rs1, int32_t rs2)
+	{ return _RVK_INTRIN_IMPL(pack)(rs1, rs2); }			//	PACK
+
+static inline int64_t __riscv_packh(int8_t rs1, int8_t rs2)
+	{ return _RVK_INTRIN_IMPL(packh)(rs1, rs2); }			//	PACKH
+
+static inline int64_t __riscv_packw(int16_t rs1, int16_t rs2)
+	{ return _RVK_INTRIN_IMPL(packw)(rs1, rs2); }			//	PACKW
+
+#endif
+
+static inline long __riscv_brev8(long rs1)
+	{ return _RVK_INTRIN_IMPL(brev8)(rs1); }				//	BREV8 (GREVI)
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t __riscv_zip(int32_t rs1)
+	{ return _RVK_INTRIN_IMPL(zip_32)(rs1); }				//	ZIP (SHFLI)
+
+static inline int32_t __riscv_unzip(int32_t rs1)
+	{ return _RVK_INTRIN_IMPL(unzip_32)(rs1); }				//	UNZIP (UNSHFLI)
+#endif
+
+//	=== (mapping)	Zbkc:	Carry-less multiply instructions
+
+static inline long __riscv_clmul(long rs1, long rs2)
+	{ return _RVK_INTRIN_IMPL(clmul)(rs1, rs2); }		//	CLMUL
+
+static inline long __riscv_clmulh(long rs1, long rs2)
+	{ return _RVK_INTRIN_IMPL(clmulh)(rs1, rs2); }		//	CLMULH
+
+//	=== (mapping)	Zbkx:	Crossbar permutation instructions
+
+
+static inline long __riscv_xperm8(long rs1, long rs2)
+	{ return _RVK_INTRIN_IMPL(xperm8_64)(rs1, rs2); }		//	XPERM8
+
+static inline long __riscv_xperm4(long rs1, long rs2)
+	{ return _RVK_INTRIN_IMPL(xperm4_64)(rs1, rs2); }		//	XPERM4
+
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c
new file mode 100644
index 00000000000..c37492ae32b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_scalar_crypto.h"
+
+int32_t foo1(int16_t rs1, int16_t rs2)
+{
+    return __riscv_pack(rs1, rs2);
+}
+
+int32_t foo2(int8_t rs1, int8_t rs2)
+{
+    return __riscv_packh(rs1, rs2);
+}
+
+int32_t foo3(int32_t rs1)
+{
+    return __riscv_brev8(rs1);
+}
+
+int32_t foo4(int32_t rs1)
+{
+    return __riscv_zip(rs1);
+}
+
+int32_t foo5(int32_t rs1)
+{
+    return __riscv_unzip(rs1);
+}
+
+/* { dg-final { scan-assembler-times "pack\t" 1 } } */
+/* { dg-final { scan-assembler-times "packh" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
+/* { dg-final { scan-assembler-times "zip" 2 } } */
+/* { dg-final { scan-assembler-times "unzip" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c
new file mode 100644
index 00000000000..e7771f73394
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include "riscv_scalar_crypto.h"
+
+int64_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __riscv_pack(rs1, rs2);
+}
+
+int64_t foo2(int8_t rs1, int8_t rs2)
+{
+    return __riscv_packh(rs1, rs2);
+}
+
+int64_t foo3(int16_t rs1, int16_t rs2)
+{
+    return __riscv_packw(rs1, rs2);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+    return __riscv_brev8(rs1);
+}
+/* { dg-final { scan-assembler-times "pack\t" 1 } } */
+/* { dg-final { scan-assembler-times "packh" 1 } } */
+/* { dg-final { scan-assembler-times "packw" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c
new file mode 100644
index 00000000000..f1b538f1441
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include "riscv_scalar_crypto.h"
+
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __riscv_clmul(rs1, rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+    return __riscv_clmulh(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c
new file mode 100644
index 00000000000..6493a83c57a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include "riscv_scalar_crypto.h"
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __riscv_clmul(rs1, rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __riscv_clmulh(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c
new file mode 100644
index 00000000000..5196e97e5e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkx -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_scalar_crypto.h"
+
+int32_t foo3(int32_t rs1, int32_t rs2)
+{
+    return __riscv_xperm8(rs1, rs2);
+}
+
+int32_t foo4(int32_t rs1, int32_t rs2)
+{
+    return __riscv_xperm4(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c
new file mode 100644
index 00000000000..7bc09bd77be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkx -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_scalar_crypto.h"
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __riscv_xperm8(rs1, rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __riscv_xperm4(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH 3/5] RISC-V: Implement ZKND and ZKNE extensions
  2023-02-13 10:45 [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
  2023-02-13 10:45 ` [PATCH 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
  2023-02-13 10:45 ` [PATCH 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Liao Shihua
@ 2023-02-13 10:45 ` Liao Shihua
  2023-02-13 10:45 ` [PATCH 4/5] RISC-V: Implement ZKNH extensions Liao Shihua
  2023-02-13 10:45 ` [PATCH 5/5] RISC-V: Implement ZKSH and ZKSED extensions Liao Shihua
  4 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-13 10:45 UTC (permalink / raw)
  To: gcc-patches
  Cc: palmer, kito.cheng, jiawei, jeff, mjos, ben.marshall, Liao Shihua

      Implement ZKND and ZKNE extensions.
      ZKND is NIST Suite: AES Decryption.
      ZKNE is NIST Suite: AES Encryption.
      
gcc/ChangeLog:

        * config/riscv/constraints.md (D03): New constraints of bs.
        (DsA):New constraints of rnum.
        * config/riscv/crypto.md (riscv_aes32dsi):Add ZKND,ZKNE instructions.
        (riscv_aes32dsmi): Likewise.
        (riscv_aes64ds): Likewise.
        (riscv_aes64dsm): Likewise.
        (riscv_aes64im): Likewise.
        (riscv_aes64ks1i): Likewise.
        (riscv_aes64ks2): Likewise.
        (riscv_aes32esi): Likewise.
        (riscv_aes32esmi): Likewise.
        (riscv_aes64es): Likewise.
        (riscv_aes64esm): Likewise.
        * config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL. 
        * config/riscv/riscv-crypto.def (DIRECT_BUILTIN):Add ZKND's and ZKNE's built-in functions. 
        * config/riscv/riscv_scalar_crypto.h (__riscv_aes32dsi):Add ZKND's and ZKNE's intrinsics. 
        (__riscv_aes32dsmi): Likewise.
        (__riscv_aes64ds): Likewise.
        (__riscv_aes64dsm): Likewise.
        (__riscv_aes64im): Likewise.
        (__riscv_aes64ks1i): Likewise.
        (__riscv_aes64ks2): Likewise.
        (__riscv_aes32esi): Likewise.
        (__riscv_aes32esmi): Likewise.
        (__riscv_aes64es): Likewise.
        (__riscv_aes64esm): Likewise.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zknd32.c: New test.
        * gcc.target/riscv/zknd64.c: New test.
        * gcc.target/riscv/zkne32.c: New test.
        * gcc.target/riscv/zkne64.c: New test.

---
 gcc/config/riscv/constraints.md         |   8 ++
 gcc/config/riscv/crypto.md              | 120 +++++++++++++++++++++++-
 gcc/config/riscv/riscv-builtins.cc      |   5 +
 gcc/config/riscv/riscv-crypto.def       |  15 +++
 gcc/config/riscv/riscv_scalar_crypto.h  |  45 +++++++++
 gcc/testsuite/gcc.target/riscv/zknd32.c |  18 ++++
 gcc/testsuite/gcc.target/riscv/zknd64.c |  36 +++++++
 gcc/testsuite/gcc.target/riscv/zkne32.c |  18 ++++
 gcc/testsuite/gcc.target/riscv/zkne64.c |  30 ++++++
 9 files changed, 294 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 3637380ee47..3f46f14b10f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -83,6 +83,14 @@
   (and (match_code "const_int")
        (match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
 
+(define_constraint "D03"
+  "0, 1, 2 or 3 immediate"
+  (match_test "IN_RANGE (ival, 0, 3)"))
+
+(define_constraint "DsA"
+  "0 - 10 immediate"
+  (match_test "IN_RANGE (ival, 0, 10)"))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 048db920bb6..a97fd398217 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -34,7 +34,20 @@
     UNSPEC_XPERM8
     UNSPEC_XPERM4
 
-
+    ;; ZKND unspecs
+    UNSPEC_AES_DSI
+    UNSPEC_AES_DSMI
+    UNSPEC_AES_DS
+    UNSPEC_AES_DSM
+    UNSPEC_AES_IM
+    UNSPEC_AES_KS1I
+    UNSPEC_AES_KS2
+
+    ;; ZKNE unspecs
+    UNSPEC_AES_ES
+    UNSPEC_AES_ESM
+    UNSPEC_AES_ESI
+    UNSPEC_AES_ESMI
 ])
 
 ;; ZBKB extension
@@ -129,5 +142,110 @@
   "xperm8\t%0,%1,%2"
   [(set_attr "type" "crypto")])
 
+;; ZKND extension
+
+(define_insn "riscv_aes32dsi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "register_operand" "D03")]
+                   UNSPEC_AES_DSI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32dsmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "register_operand" "D03")]
+                   UNSPEC_AES_DSMI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsmi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ds"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_DS))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64ds\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64dsm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_DSM))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64dsm\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64im"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_AES_IM))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64im\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ks1i"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "DsA")]
+                   UNSPEC_AES_KS1I))]
+  "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
+  "aes64ks1i\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ks2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_KS2))]
+  "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
+  "aes64ks2\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZKNE extension
+
+(define_insn "riscv_aes32esi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "register_operand" "D03")]
+                   UNSPEC_AES_ESI))]
+  "TARGET_ZKNE && !TARGET_64BIT"
+  "aes32esi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32esmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "register_operand" "D03")]
+                   UNSPEC_AES_ESMI))]
+  "TARGET_ZKNE && !TARGET_64BIT"
+  "aes32esmi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64es"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_ES))]
+  "TARGET_ZKNE && TARGET_64BIT"
+  "aes64es\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64esm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_ESM))]
+  "TARGET_ZKNE && TARGET_64BIT"
+  "aes64esm\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
 
 
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index e9c2d92f0d3..b92619f99e4 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -106,6 +106,11 @@ AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT)
 AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT)
 AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
 AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
+AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT)
+AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
+AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
+AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
+AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def
index 40fbb9e43cb..4c8a087aa16 100644
--- a/gcc/config/riscv/riscv-crypto.def
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -44,3 +44,18 @@ RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI,
 RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
 RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
 
+// ZKND
+DIRECT_BUILTIN (aes32dsi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes32dsmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes64ds, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64dsm, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne_or_zknd),
+DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne_or_zknd),
+
+// ZKNE
+DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+
diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h
index 76c0a4f0436..eb8b89124ea 100644
--- a/gcc/config/riscv/riscv_scalar_crypto.h
+++ b/gcc/config/riscv/riscv_scalar_crypto.h
@@ -104,3 +104,48 @@ static inline long __riscv_xperm4(long rs1, long rs2)
 	{ return _RVK_INTRIN_IMPL(xperm4_64)(rs1, rs2); }		//	XPERM4
 
 
+//	=== (mapping)	Zknd:	NIST Suite: AES Decryption
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t __riscv_aes32dsi(int32_t rs1, int32_t rs2, int bs)
+	{ return _RVK_INTRIN_IMPL(aes32dsi)(rs1, rs2, bs); }	//	AES32DSI
+
+static inline int32_t __riscv_aes32dsmi(int32_t rs1, int32_t rs2, int bs)
+	{ return _RVK_INTRIN_IMPL(aes32dsmi)(rs1, rs2, bs); }	//	AES32DSMI
+#endif
+
+#ifdef RVKINTRIN_RV64
+static inline int64_t __riscv_aes64ds(int64_t rs1, int64_t rs2)
+	{ return _RVK_INTRIN_IMPL(aes64ds)(rs1, rs2); }			//	AES64DS
+
+static inline int64_t __riscv_aes64dsm(int64_t rs1, int64_t rs2)
+	{ return _RVK_INTRIN_IMPL(aes64dsm)(rs1, rs2); }		//	AES64DSM
+
+static inline int64_t __riscv_aes64im(int64_t rs1)
+	{ return _RVK_INTRIN_IMPL(aes64im)(rs1); }				//	AES64IM
+
+static inline int64_t __riscv_aes64ks1i(int64_t rs1, int rnum)
+	{ return _RVK_INTRIN_IMPL(aes64ks1i)(rs1, rnum); }		//	AES64KS1I
+
+static inline int64_t __riscv_aes64ks2(int64_t rs1, int64_t rs2)
+	{ return _RVK_INTRIN_IMPL(aes64ks2)(rs1, rs2); }		//	AES64KS2
+#endif
+
+//	=== (mapping)	Zkne:	NIST Suite: AES Encryption
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t __riscv_aes32esi(int32_t rs1, int32_t rs2, int bs)
+	{ return _RVK_INTRIN_IMPL(aes32esi)(rs1, rs2, bs); }	//	AES32ESI
+
+static inline int32_t __riscv_aes32esmi(int32_t rs1, int32_t rs2, int bs)
+	{ return _RVK_INTRIN_IMPL(aes32esmi)(rs1, rs2, bs); }	//	AES32ESMI
+#endif
+
+#ifdef RVKINTRIN_RV64
+static inline int64_t __riscv_aes64es(int64_t rs1, int64_t rs2)
+	{ return _RVK_INTRIN_IMPL(aes64es)(rs1, rs2); }			//	AES64ES
+
+static inline int64_t __riscv_aes64esm(int64_t rs1, int64_t rs2)
+	{ return _RVK_INTRIN_IMPL(aes64esm)(rs1, rs2); }		//	AES64ESM
+#endif
+
diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c b/gcc/testsuite/gcc.target/riscv/zknd32.c
new file mode 100644
index 00000000000..b7bde2bb20d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknd32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zknd -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_scalar_crypto.h"
+
+int32_t foo1(int32_t rs1, int32_t rs2, int bs)
+{
+    return __riscv_aes32dsi(rs1,rs2,bs);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2, int bs)
+{
+    return __riscv_aes32dsmi(rs1,rs2,bs);
+}
+
+/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.target/riscv/zknd64.c
new file mode 100644
index 00000000000..8ad3c55341c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknd64.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknd -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __riscv_aes64ds(rs1,rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __riscv_aes64dsm(rs1,rs2);
+}
+
+int64_t foo3(int64_t rs1, int rnum)
+{
+    return __riscv_aes64ks1i(rs1,rnum);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+    return __riscv_aes64ks2(rs1,rs2);
+}
+
+int64_t foo5(int64_t rs1)
+{
+    return __riscv_aes64im(rs1);
+}
+
+/* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */
+/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
+/* { dg-final { scan-assembler-times "aes64im" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zkne32.c b/gcc/testsuite/gcc.target/riscv/zkne32.c
new file mode 100644
index 00000000000..48a1dda8a3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zkne32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zkne -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include "riscv_scalar_crypto.h"
+
+int32_t foo1(int32_t rs1, int32_t rs2, int bs)
+{
+    return __riscv_aes32esi(rs1, rs2, bs);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2, int bs)
+{
+    return __riscv_aes32esmi(rs1, rs2, bs);
+}
+
+/* { dg-final { scan-assembler-times "aes32esi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zkne64.c b/gcc/testsuite/gcc.target/riscv/zkne64.c
new file mode 100644
index 00000000000..6d5be92f666
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zkne64.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zkne -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __riscv_aes64es(rs1,rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __riscv_aes64esm(rs1,rs2);
+}
+
+int64_t foo3(int64_t rs1, int rnum)
+{
+    return __riscv_aes64ks1i(rs1,rnum);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+    return __riscv_aes64ks2(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "aes64es\t" 1 } } */
+/* { dg-final { scan-assembler-times "aes64esm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH 4/5] RISC-V: Implement ZKNH extensions
  2023-02-13 10:45 [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
                   ` (2 preceding siblings ...)
  2023-02-13 10:45 ` [PATCH 3/5] RISC-V: Implement ZKND and ZKNE extensions Liao Shihua
@ 2023-02-13 10:45 ` Liao Shihua
  2023-02-13 10:45 ` [PATCH 5/5] RISC-V: Implement ZKSH and ZKSED extensions Liao Shihua
  4 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-13 10:45 UTC (permalink / raw)
  To: gcc-patches
  Cc: palmer, kito.cheng, jiawei, jeff, mjos, ben.marshall, Liao Shihua

      Implement ZKNH extensions.
      ZKNH is NIST Suite: Hash Function Instructions.

gcc/ChangeLog:

        * config/riscv/crypto.md (riscv_sha256sig0_<mode>):Add ZKNH's instructions.
        (riscv_sha256sig1_<mode>): Likewise.
        (riscv_sha256sum0_<mode>): Likewise.
        (riscv_sha256sum1_<mode>): Likewise.
        (riscv_sha512sig0h): Likewise.
        (riscv_sha512sig0l): Likewise.
        (riscv_sha512sig1h): Likewise.
        (riscv_sha512sig1l): Likewise.
        (riscv_sha512sum0r): Likewise.
        (riscv_sha512sum1r): Likewise.
        (riscv_sha512sig0): Likewise.
        (riscv_sha512sig1): Likewise.
        (riscv_sha512sum0): Likewise.
        (riscv_sha512sum1): Likewise.
        * config/riscv/riscv-builtins.cc (AVAIL): Add ZKNH's AVAIL.
        * config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKNH's built-in functions.
        (DIRECT_BUILTIN): Likewise.
        * config/riscv/riscv_scalar_crypto.h (__riscv_sha256sig0): Add ZKNH's intrinsics.
        (__riscv_sha256sig1): Likewise.
        (__riscv_sha256sum0): Likewise.
        (__riscv_sha256sum1): Likewise.
        (__riscv_sha512sig0h): Likewise.
        (__riscv_sha512sig0l): Likewise.
        (__riscv_sha512sig1h): Likewise.
        (__riscv_sha512sig1l): Likewise.
        (__riscv_sha512sum0r): Likewise.
        (__riscv_sha512sum1r): Likewise.
        (__riscv_sha512sig0): Likewise.
        (__riscv_sha512sig1): Likewise.
        (__riscv_sha512sum0): Likewise.
        (__riscv_sha512sum1): Likewise.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zknh-sha256.c: New test.
        * gcc.target/riscv/zknh-sha512-32.c: New test.
        * gcc.target/riscv/zknh-sha512-64.c: New test.

---
 gcc/config/riscv/crypto.md                    | 138 ++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc            |   2 +
 gcc/config/riscv/riscv-crypto.def             |  21 +++
 gcc/config/riscv/riscv_scalar_crypto.h        |  48 ++++++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 ++++
 .../gcc.target/riscv/zknh-sha512-32.c         |  43 ++++++
 .../gcc.target/riscv/zknh-sha512-64.c         |  31 ++++
 7 files changed, 312 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index a97fd398217..236eba69e46 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -48,6 +48,22 @@
     UNSPEC_AES_ESM
     UNSPEC_AES_ESI
     UNSPEC_AES_ESMI
+
+    ;; ZKNH unspecs
+    UNSPEC_SHA_256_SIG0
+    UNSPEC_SHA_256_SIG1
+    UNSPEC_SHA_256_SUM0
+    UNSPEC_SHA_256_SUM1
+    UNSPEC_SHA_512_SIG0
+    UNSPEC_SHA_512_SIG0H
+    UNSPEC_SHA_512_SIG0L
+    UNSPEC_SHA_512_SIG1
+    UNSPEC_SHA_512_SIG1H
+    UNSPEC_SHA_512_SIG1L
+    UNSPEC_SHA_512_SUM0
+    UNSPEC_SHA_512_SUM0R
+    UNSPEC_SHA_512_SUM1
+    UNSPEC_SHA_512_SUM1R
 ])
 
 ;; ZBKB extension
@@ -249,3 +265,125 @@
   [(set_attr "type" "crypto")])
 
 
+
+;; ZKNH - SHA256
+
+(define_insn "riscv_sha256sig0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SIG0))]
+  "TARGET_ZKNH"
+  "sha256sig0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sig1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SIG1))]
+  "TARGET_ZKNH"
+  "sha256sig1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SUM0))]
+  "TARGET_ZKNH"
+  "sha256sum0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SUM1))]
+  "TARGET_ZKNH"
+  "sha256sum1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA512
+
+(define_insn "riscv_sha512sig0h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0l\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1l\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM0R))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sum0r\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum1r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM1R))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sum1r\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sig0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sig1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM0))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sum0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM1))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sum1\t%0,%1"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index b92619f99e4..2a35167e6fb 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -111,6 +111,8 @@ AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
 AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
 AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
+AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
+AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def
index 4c8a087aa16..831ab8c0d01 100644
--- a/gcc/config/riscv/riscv-crypto.def
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -59,3 +59,24 @@ DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
 DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
 DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
 
+// ZKNH
+RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum0_di, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum1_si, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum1_di, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+DIRECT_BUILTIN (sha512sig0h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig0l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+
+DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h
index eb8b89124ea..d6739f75774 100644
--- a/gcc/config/riscv/riscv_scalar_crypto.h
+++ b/gcc/config/riscv/riscv_scalar_crypto.h
@@ -149,3 +149,51 @@ static inline int64_t __riscv_aes64esm(int64_t rs1, int64_t rs2)
 	{ return _RVK_INTRIN_IMPL(aes64esm)(rs1, rs2); }		//	AES64ESM
 #endif
 
+//	=== (mapping)	Zknh:	NIST Suite: Hash Function Instructions
+
+static inline long __riscv_sha256sig0(long rs1)
+	{ return _RVK_INTRIN_IMPL(sha256sig0)(rs1); }			//	SHA256SIG0
+
+static inline long __riscv_sha256sig1(long rs1)
+	{ return _RVK_INTRIN_IMPL(sha256sig1)(rs1); }			//	SHA256SIG1
+
+static inline long __riscv_sha256sum0(long rs1)
+	{ return _RVK_INTRIN_IMPL(sha256sum0)(rs1); }			//	SHA256SUM0
+
+static inline long __riscv_sha256sum1(long rs1)
+	{ return _RVK_INTRIN_IMPL(sha256sum1)(rs1); }			//	SHA256SUM1
+
+#ifdef RVKINTRIN_RV32
+static inline int32_t __riscv_sha512sig0h(int32_t rs1, int32_t rs2)
+	{ return _RVK_INTRIN_IMPL(sha512sig0h)(rs1, rs2); }		//	SHA512SIG0H
+
+static inline int32_t __riscv_sha512sig0l(int32_t rs1, int32_t rs2)
+	{ return _RVK_INTRIN_IMPL(sha512sig0l)(rs1, rs2); }		//	SHA512SIG0L
+
+static inline int32_t __riscv_sha512sig1h(int32_t rs1, int32_t rs2)
+	{ return _RVK_INTRIN_IMPL(sha512sig1h)(rs1, rs2); }		//	SHA512SIG1H
+
+static inline int32_t __riscv_sha512sig1l(int32_t rs1, int32_t rs2)
+	{ return _RVK_INTRIN_IMPL(sha512sig1l)(rs1, rs2); }		//	SHA512SIG1L
+
+static inline int32_t __riscv_sha512sum0r(int32_t rs1, int32_t rs2)
+	{ return _RVK_INTRIN_IMPL(sha512sum0r)(rs1, rs2); }		//	SHA512SUM0R
+
+static inline int32_t __riscv_sha512sum1r(int32_t rs1, int32_t rs2)
+	{ return _RVK_INTRIN_IMPL(sha512sum1r)(rs1, rs2); }		//	SHA512SUM1R
+#endif
+
+#ifdef RVKINTRIN_RV64
+static inline int64_t __riscv_sha512sig0(int64_t rs1)
+	{ return _RVK_INTRIN_IMPL(sha512sig0)(rs1); }			//	SHA512SIG0
+
+static inline int64_t __riscv_sha512sig1(int64_t rs1)
+	{ return _RVK_INTRIN_IMPL(sha512sig1)(rs1); }			//	SHA512SIG1
+
+static inline int64_t __riscv_sha512sum0(int64_t rs1)
+	{ return _RVK_INTRIN_IMPL(sha512sum0)(rs1); }			//	SHA512SUM0
+
+static inline int64_t __riscv_sha512sum1(int64_t rs1)
+	{ return _RVK_INTRIN_IMPL(sha512sum1)(rs1); }			//	SHA512SUM1
+#endif
+
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256.c b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
new file mode 100644
index 00000000000..88bf01eb279
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+long foo1(long rs1)
+{
+    return __riscv_sha256sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __riscv_sha256sig1(rs1);
+}
+
+long foo3(long rs1)
+{
+    return __riscv_sha256sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+    return __riscv_sha256sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
new file mode 100644
index 00000000000..dcea6ad1536
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
@@ -0,0 +1,43 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __riscv_sha512sig0h(rs1,rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+    return __riscv_sha512sig0l(rs1,rs2);
+}
+
+int32_t foo3(int32_t rs1, int32_t rs2)
+{
+    return __riscv_sha512sig1h(rs1,rs2);
+}
+
+int32_t foo4(int32_t rs1, int32_t rs2)
+{
+    return __riscv_sha512sig1l(rs1,rs2);
+}
+
+int32_t foo5(int32_t rs1, int32_t rs2)
+{
+    return __riscv_sha512sum0r(rs1,rs2);
+}
+
+int32_t foo6(int32_t rs1, int32_t rs2)
+{
+    return __riscv_sha512sum1r(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
new file mode 100644
index 00000000000..ed87e1e93bb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+int64_t foo1(int64_t rs1)
+{
+    return __riscv_sha512sig0(rs1);
+}
+
+int64_t foo2(int64_t rs1)
+{
+    return __riscv_sha512sig1(rs1);
+}
+
+int64_t foo3(int64_t rs1)
+{
+    return __riscv_sha512sum0(rs1);
+}
+
+int64_t foo4(int64_t rs1)
+{
+    return __riscv_sha512sum1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH 5/5] RISC-V: Implement ZKSH and ZKSED extensions
  2023-02-13 10:45 [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
                   ` (3 preceding siblings ...)
  2023-02-13 10:45 ` [PATCH 4/5] RISC-V: Implement ZKNH extensions Liao Shihua
@ 2023-02-13 10:45 ` Liao Shihua
  4 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-13 10:45 UTC (permalink / raw)
  To: gcc-patches
  Cc: palmer, kito.cheng, jiawei, jeff, mjos, ben.marshall, Liao Shihua

      Implement ZKSH and ZKSED extensions.
      ZKSH  is  ShangMi Suite: SM3 Hash Function Instructions.
      ZKSED is ShangMi Suite: SM4 Block Cipher Instructions.

gcc/ChangeLog:

        * config/riscv/crypto.md (riscv_sm3p0_<mode>): Add ZKSH's and ZKSED's instructions.
        (riscv_sm3p1_<mode>): Likewise.
        (riscv_sm4ed_<mode>): Likewise.
        (riscv_sm4ks_<mode>): Likewise.
        * config/riscv/riscv-builtins.cc (AVAIL): Add ZKSH's and ZKSED's AVAIL.
        * config/riscv/riscv-crypto.def (RISCV_BUILTIN): Add ZKSH's and ZKSED's built-in functions.
        * config/riscv/riscv_scalar_crypto.h (__riscv_sm4ks): Add ZKSH's and ZKSED's intrinsics.
        (__riscv_sm4ed): Likewise.
        (__riscv_sm3p0): Likewise.
        (__riscv_sm3p1): Likewise.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zksed.c: New test.
        * gcc.target/riscv/zksh.c: New test.
---
 gcc/config/riscv/crypto.md             | 48 ++++++++++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc     |  4 +++
 gcc/config/riscv/riscv-crypto.def      | 12 +++++++
 gcc/config/riscv/riscv_scalar_crypto.h | 19 ++++++++++
 gcc/testsuite/gcc.target/riscv/zksed.c | 20 +++++++++++
 gcc/testsuite/gcc.target/riscv/zksh.c  | 19 ++++++++++
 6 files changed, 122 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 236eba69e46..564a685d690 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -64,6 +64,14 @@
     UNSPEC_SHA_512_SUM0R
     UNSPEC_SHA_512_SUM1
     UNSPEC_SHA_512_SUM1R
+
+    ;; ZKSH unspecs
+    UNSPEC_SM3_P0
+    UNSPEC_SM3_P1
+
+    ;; ZKSED unspecs
+    UNSPEC_SM4_ED
+    UNSPEC_SM4_KS
 ])
 
 ;; ZBKB extension
@@ -387,3 +395,43 @@
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1"
   [(set_attr "type" "crypto")])
+
+ ;; ZKSH
+
+(define_insn "riscv_sm3p0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm3p1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKSED 
+
+(define_insn "riscv_sm4ed_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")
+                  (match_operand:SI 3 "register_operand" "D03")]
+                  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm4ks_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")
+                  (match_operand:SI 3 "register_operand" "D03")]
+                  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 2a35167e6fb..18c0cce6b8b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -113,6 +113,10 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-crypto.def b/gcc/config/riscv/riscv-crypto.def
index 831ab8c0d01..7774b801aec 100644
--- a/gcc/config/riscv/riscv-crypto.def
+++ b/gcc/config/riscv/riscv-crypto.def
@@ -80,3 +80,15 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// ZKSH
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+
+// ZKSED
+RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64),
+RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ks_di, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64),
diff --git a/gcc/config/riscv/riscv_scalar_crypto.h b/gcc/config/riscv/riscv_scalar_crypto.h
index d6739f75774..b1f596a5078 100644
--- a/gcc/config/riscv/riscv_scalar_crypto.h
+++ b/gcc/config/riscv/riscv_scalar_crypto.h
@@ -197,3 +197,22 @@ static inline int64_t __riscv_sha512sum1(int64_t rs1)
 	{ return _RVK_INTRIN_IMPL(sha512sum1)(rs1); }			//	SHA512SUM1
 #endif
 
+//	=== (mapping)	Zksed:	ShangMi Suite: SM4 Block Cipher Instructions
+
+static inline long __riscv_sm4ks(long rs1, long rs2, int bs)
+	{ return _RVK_INTRIN_IMPL(sm4ks)(rs1, rs2, bs); }		//	SM4KS
+
+static inline long __riscv_sm4ed(long rs1, long rs2, int bs)
+	{ return _RVK_INTRIN_IMPL(sm4ed)(rs1, rs2, bs); }		//	SM4ED
+
+//	=== (mapping)	Zksh:	ShangMi Suite: SM3 Hash Function Instructions
+
+static inline long __riscv_sm3p0(long rs1)
+	{ return _RVK_INTRIN_IMPL(sm3p0)(rs1); }				//	SM3P0
+
+static inline long __riscv_sm3p1(long rs1)
+	{ return _RVK_INTRIN_IMPL(sm3p1)(rs1); }				//	SM3P1
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/gcc/testsuite/gcc.target/riscv/zksed.c b/gcc/testsuite/gcc.target/riscv/zksed.c
new file mode 100644
index 00000000000..2c7a6ab4089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksed.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zksed -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+long foo1(long rs1, long rs2, int bs)
+{
+    return __riscv_sm4ks(rs1,rs2,bs);
+}
+
+long foo2(long rs1, long rs2, int bs)
+{
+    return __riscv_sm4ed(rs1,rs2,bs);
+}
+
+
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
+
diff --git a/gcc/testsuite/gcc.target/riscv/zksh.c b/gcc/testsuite/gcc.target/riscv/zksh.c
new file mode 100644
index 00000000000..79485c7f3a9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksh.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zksh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include"riscv_scalar_crypto.h"
+
+long foo1(long rs1)
+{
+    return __riscv_sm3p0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __riscv_sm3p1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension
@ 2023-02-13 10:32 Liao Shihua
  0 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-13 10:32 UTC (permalink / raw)
  To: gcc-patches
  Cc: palmer, kito.cheng, jiawei, cmuellner, jeff, mjos, ben.marshall,
	Liao Shihua

    This patch implement RISC-V Scalar Cryptography extension.
    It includes machine descrption , intrinsic and testcase .

Liao Shihua (5):
  Add prototypes for RISC-V Crypto built-in functions
  Implement ZBKB, ZBKC and ZBKX extensions
  Implement ZKND and ZKNE extensions
  Implement ZKNH extensions
  Implement ZKSH and ZKSED extensions

 gcc/config.gcc                                |   2 +-
 gcc/config/riscv/bitmanip.md                  |  20 +-
 gcc/config/riscv/constraints.md               |   8 +
 gcc/config/riscv/crypto.md                    | 437 ++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc            |  26 ++
 gcc/config/riscv/riscv-crypto.def             |  94 ++++
 gcc/config/riscv/riscv-ftypes.def             |  10 +
 gcc/config/riscv/riscv.md                     |   4 +-
 gcc/config/riscv/riscv_scalar_crypto.h        | 218 +++++++++
 gcc/testsuite/gcc.target/riscv/zbkb32.c       |  36 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c       |  28 ++
 gcc/testsuite/gcc.target/riscv/zbkc32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c       |  17 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c       |  19 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zknd32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c       |  36 ++
 gcc/testsuite/gcc.target/riscv/zkne32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zkne64.c       |  30 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  29 ++
 .../gcc.target/riscv/zknh-sha512-32.c         |  43 ++
 .../gcc.target/riscv/zknh-sha512-64.c         |  31 ++
 gcc/testsuite/gcc.target/riscv/zksed.c        |  20 +
 gcc/testsuite/gcc.target/riscv/zksh.c         |  19 +
 24 files changed, 1187 insertions(+), 12 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-crypto.def
 create mode 100644 gcc/config/riscv/riscv_scalar_crypto.h
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh.c

-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-02-13 10:45 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-13 10:45 [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
2023-02-13 10:45 ` [PATCH 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
2023-02-13 10:45 ` [PATCH 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Liao Shihua
2023-02-13 10:45 ` [PATCH 3/5] RISC-V: Implement ZKND and ZKNE extensions Liao Shihua
2023-02-13 10:45 ` [PATCH 4/5] RISC-V: Implement ZKNH extensions Liao Shihua
2023-02-13 10:45 ` [PATCH 5/5] RISC-V: Implement ZKSH and ZKSED extensions Liao Shihua
  -- strict thread matches above, loose matches on Subject: below --
2023-02-13 10:32 [PATCH 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).