[PATCH] RISC-V: Add all mask C++ api tests

[PATCH] RISC-V: Add all mask C++ api tests

[juzhe.zhong]

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vcpop_m-1.C: New test.
        * g++.target/riscv/rvv/base/vcpop_m-2.C: New test.
        * g++.target/riscv/rvv/base/vcpop_m-3.C: New test.
        * g++.target/riscv/rvv/base/vfirst_m-1.C: New test.
        * g++.target/riscv/rvv/base/vfirst_m-2.C: New test.
        * g++.target/riscv/rvv/base/vfirst_m-3.C: New test.
        * g++.target/riscv/rvv/base/vid_v-1.C: New test.
        * g++.target/riscv/rvv/base/vid_v-2.C: New test.
        * g++.target/riscv/rvv/base/vid_v-3.C: New test.
        * g++.target/riscv/rvv/base/vid_v_m-1.C: New test.
        * g++.target/riscv/rvv/base/vid_v_m-2.C: New test.
        * g++.target/riscv/rvv/base/vid_v_m-3.C: New test.
        * g++.target/riscv/rvv/base/vid_v_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vid_v_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vid_v_mu-3.C: New test.
        * g++.target/riscv/rvv/base/viota_m_m-1.C: New test.
        * g++.target/riscv/rvv/base/viota_m_m-2.C: New test.
        * g++.target/riscv/rvv/base/viota_m_m-3.C: New test.
        * g++.target/riscv/rvv/base/viota_m_mu-1.C: New test.
        * g++.target/riscv/rvv/base/viota_m_mu-2.C: New test.
        * g++.target/riscv/rvv/base/viota_m_mu-3.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tu-1.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tu-2.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tu-3.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tum-1.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tum-2.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tum-3.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/viota_m_tumu-3.C: New test.
        * g++.target/riscv/rvv/base/vlm_v-1.C: New test.
        * g++.target/riscv/rvv/base/vlm_v-2.C: New test.
        * g++.target/riscv/rvv/base/vlm_v-3.C: New test.
        * g++.target/riscv/rvv/base/vsm_v-1.C: New test.
        * g++.target/riscv/rvv/base/vsm_v-2.C: New test.
        * g++.target/riscv/rvv/base/vsm_v-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vcpop_m-1.C     | 104 ++++++
 .../g++.target/riscv/rvv/base/vcpop_m-2.C     | 104 ++++++
 .../g++.target/riscv/rvv/base/vcpop_m-3.C     | 104 ++++++
 .../g++.target/riscv/rvv/base/vfirst_m-1.C    | 104 ++++++
 .../g++.target/riscv/rvv/base/vfirst_m-2.C    | 104 ++++++
 .../g++.target/riscv/rvv/base/vfirst_m-3.C    | 104 ++++++
 .../g++.target/riscv/rvv/base/vid_v-1.C       | 160 +++++++++
 .../g++.target/riscv/rvv/base/vid_v-2.C       | 160 +++++++++
 .../g++.target/riscv/rvv/base/vid_v-3.C       | 160 +++++++++
 .../g++.target/riscv/rvv/base/vid_v_m-1.C     | 160 +++++++++
 .../g++.target/riscv/rvv/base/vid_v_m-2.C     | 160 +++++++++
 .../g++.target/riscv/rvv/base/vid_v_m-3.C     | 160 +++++++++
 .../g++.target/riscv/rvv/base/vid_v_mu-1.C    | 160 +++++++++
 .../g++.target/riscv/rvv/base/vid_v_mu-2.C    | 160 +++++++++
 .../g++.target/riscv/rvv/base/vid_v_mu-3.C    | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_m-1.C   | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/viota_m_m-2.C   | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/viota_m_m-3.C   | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/viota_m_mu-1.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_mu-2.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_mu-3.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_tu-1.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_tu-2.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_tu-3.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_tum-1.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_tum-2.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/viota_m_tum-3.C | 160 +++++++++
 .../riscv/rvv/base/viota_m_tumu-1.C           | 160 +++++++++
 .../riscv/rvv/base/viota_m_tumu-2.C           | 160 +++++++++
 .../riscv/rvv/base/viota_m_tumu-3.C           | 160 +++++++++
 .../g++.target/riscv/rvv/base/vlm_v-1.C       |  55 +++
 .../g++.target/riscv/rvv/base/vlm_v-2.C       |  55 +++
 .../g++.target/riscv/rvv/base/vlm_v-3.C       |  55 +++
 .../g++.target/riscv/rvv/base/vsm_v-1.C       |  55 +++
 .../g++.target/riscv/rvv/base/vsm_v-2.C       |  55 +++
 .../g++.target/riscv/rvv/base/vsm_v-3.C       |  55 +++
 36 files changed, 5256 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-1.C
new file mode 100644
index 00000000000..d4aa6745675
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-1.C
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+uint64_t test___riscv_vcpop(vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,vl);
+}
+
+
+uint64_t test___riscv_vcpop(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-2.C
new file mode 100644
index 00000000000..e08e6ca60fc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-2.C
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+uint64_t test___riscv_vcpop(vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,31);
+}
+
+
+uint64_t test___riscv_vcpop(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-3.C
new file mode 100644
index 00000000000..a7dae462e33
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vcpop_m-3.C
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+uint64_t test___riscv_vcpop(vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop(op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,32);
+}
+
+
+uint64_t test___riscv_vcpop(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vcpop(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vcpop\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-1.C
new file mode 100644
index 00000000000..9d1e179bcf6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-1.C
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+long test___riscv_vfirst(vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,vl);
+}
+
+
+long test___riscv_vfirst(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-2.C
new file mode 100644
index 00000000000..cbb0bd7927d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-2.C
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+long test___riscv_vfirst(vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,31);
+}
+
+
+long test___riscv_vfirst(vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,31);
+}
+
+
+long test___riscv_vfirst(vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,31);
+}
+
+
+long test___riscv_vfirst(vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,31);
+}
+
+
+long test___riscv_vfirst(vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,31);
+}
+
+
+long test___riscv_vfirst(vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,31);
+}
+
+
+long test___riscv_vfirst(vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,31);
+}
+
+
+long test___riscv_vfirst(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,31);
+}
+
+
+long test___riscv_vfirst(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,31);
+}
+
+
+long test___riscv_vfirst(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,31);
+}
+
+
+long test___riscv_vfirst(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,31);
+}
+
+
+long test___riscv_vfirst(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,31);
+}
+
+
+long test___riscv_vfirst(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,31);
+}
+
+
+long test___riscv_vfirst(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-3.C
new file mode 100644
index 00000000000..c39b142c31f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vfirst_m-3.C
@@ -0,0 +1,104 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+long test___riscv_vfirst(vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,32);
+}
+
+
+long test___riscv_vfirst(vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,32);
+}
+
+
+long test___riscv_vfirst(vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,32);
+}
+
+
+long test___riscv_vfirst(vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,32);
+}
+
+
+long test___riscv_vfirst(vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,32);
+}
+
+
+long test___riscv_vfirst(vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,32);
+}
+
+
+long test___riscv_vfirst(vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst(op1,32);
+}
+
+
+long test___riscv_vfirst(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,32);
+}
+
+
+long test___riscv_vfirst(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,32);
+}
+
+
+long test___riscv_vfirst(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,32);
+}
+
+
+long test___riscv_vfirst(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,32);
+}
+
+
+long test___riscv_vfirst(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,32);
+}
+
+
+long test___riscv_vfirst(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,32);
+}
+
+
+long test___riscv_vfirst(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_vfirst(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vfirst\.m\s+[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-1.C
new file mode 100644
index 00000000000..9ec685594ee
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8(size_t vl)
+{
+    return __riscv_vid_v_u8mf8(vl);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4(size_t vl)
+{
+    return __riscv_vid_v_u8mf4(vl);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2(size_t vl)
+{
+    return __riscv_vid_v_u8mf2(vl);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1(size_t vl)
+{
+    return __riscv_vid_v_u8m1(vl);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2(size_t vl)
+{
+    return __riscv_vid_v_u8m2(vl);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4(size_t vl)
+{
+    return __riscv_vid_v_u8m4(vl);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8(size_t vl)
+{
+    return __riscv_vid_v_u8m8(vl);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4(size_t vl)
+{
+    return __riscv_vid_v_u16mf4(vl);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2(size_t vl)
+{
+    return __riscv_vid_v_u16mf2(vl);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1(size_t vl)
+{
+    return __riscv_vid_v_u16m1(vl);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2(size_t vl)
+{
+    return __riscv_vid_v_u16m2(vl);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4(size_t vl)
+{
+    return __riscv_vid_v_u16m4(vl);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8(size_t vl)
+{
+    return __riscv_vid_v_u16m8(vl);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2(size_t vl)
+{
+    return __riscv_vid_v_u32mf2(vl);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1(size_t vl)
+{
+    return __riscv_vid_v_u32m1(vl);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2(size_t vl)
+{
+    return __riscv_vid_v_u32m2(vl);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4(size_t vl)
+{
+    return __riscv_vid_v_u32m4(vl);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8(size_t vl)
+{
+    return __riscv_vid_v_u32m8(vl);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1(size_t vl)
+{
+    return __riscv_vid_v_u64m1(vl);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2(size_t vl)
+{
+    return __riscv_vid_v_u64m2(vl);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4(size_t vl)
+{
+    return __riscv_vid_v_u64m4(vl);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8(size_t vl)
+{
+    return __riscv_vid_v_u64m8(vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-2.C
new file mode 100644
index 00000000000..63a3b1d9237
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8(size_t vl)
+{
+    return __riscv_vid_v_u8mf8(31);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4(size_t vl)
+{
+    return __riscv_vid_v_u8mf4(31);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2(size_t vl)
+{
+    return __riscv_vid_v_u8mf2(31);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1(size_t vl)
+{
+    return __riscv_vid_v_u8m1(31);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2(size_t vl)
+{
+    return __riscv_vid_v_u8m2(31);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4(size_t vl)
+{
+    return __riscv_vid_v_u8m4(31);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8(size_t vl)
+{
+    return __riscv_vid_v_u8m8(31);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4(size_t vl)
+{
+    return __riscv_vid_v_u16mf4(31);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2(size_t vl)
+{
+    return __riscv_vid_v_u16mf2(31);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1(size_t vl)
+{
+    return __riscv_vid_v_u16m1(31);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2(size_t vl)
+{
+    return __riscv_vid_v_u16m2(31);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4(size_t vl)
+{
+    return __riscv_vid_v_u16m4(31);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8(size_t vl)
+{
+    return __riscv_vid_v_u16m8(31);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2(size_t vl)
+{
+    return __riscv_vid_v_u32mf2(31);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1(size_t vl)
+{
+    return __riscv_vid_v_u32m1(31);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2(size_t vl)
+{
+    return __riscv_vid_v_u32m2(31);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4(size_t vl)
+{
+    return __riscv_vid_v_u32m4(31);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8(size_t vl)
+{
+    return __riscv_vid_v_u32m8(31);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1(size_t vl)
+{
+    return __riscv_vid_v_u64m1(31);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2(size_t vl)
+{
+    return __riscv_vid_v_u64m2(31);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4(size_t vl)
+{
+    return __riscv_vid_v_u64m4(31);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8(size_t vl)
+{
+    return __riscv_vid_v_u64m8(31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-3.C
new file mode 100644
index 00000000000..19995364639
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8(size_t vl)
+{
+    return __riscv_vid_v_u8mf8(32);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4(size_t vl)
+{
+    return __riscv_vid_v_u8mf4(32);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2(size_t vl)
+{
+    return __riscv_vid_v_u8mf2(32);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1(size_t vl)
+{
+    return __riscv_vid_v_u8m1(32);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2(size_t vl)
+{
+    return __riscv_vid_v_u8m2(32);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4(size_t vl)
+{
+    return __riscv_vid_v_u8m4(32);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8(size_t vl)
+{
+    return __riscv_vid_v_u8m8(32);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4(size_t vl)
+{
+    return __riscv_vid_v_u16mf4(32);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2(size_t vl)
+{
+    return __riscv_vid_v_u16mf2(32);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1(size_t vl)
+{
+    return __riscv_vid_v_u16m1(32);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2(size_t vl)
+{
+    return __riscv_vid_v_u16m2(32);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4(size_t vl)
+{
+    return __riscv_vid_v_u16m4(32);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8(size_t vl)
+{
+    return __riscv_vid_v_u16m8(32);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2(size_t vl)
+{
+    return __riscv_vid_v_u32mf2(32);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1(size_t vl)
+{
+    return __riscv_vid_v_u32m1(32);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2(size_t vl)
+{
+    return __riscv_vid_v_u32m2(32);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4(size_t vl)
+{
+    return __riscv_vid_v_u32m4(32);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8(size_t vl)
+{
+    return __riscv_vid_v_u32m8(32);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1(size_t vl)
+{
+    return __riscv_vid_v_u64m1(32);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2(size_t vl)
+{
+    return __riscv_vid_v_u64m2(32);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4(size_t vl)
+{
+    return __riscv_vid_v_u64m4(32);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8(size_t vl)
+{
+    return __riscv_vid_v_u64m8(32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-1.C
new file mode 100644
index 00000000000..95fb5005e3f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf8_m(mask,vl);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf4_m(mask,vl);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf2_m(mask,vl);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m1_m(mask,vl);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m2_m(mask,vl);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4_m(vbool2_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m4_m(mask,vl);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8_m(vbool1_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m8_m(mask,vl);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16mf4_m(mask,vl);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16mf2_m(mask,vl);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m1_m(mask,vl);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m2_m(mask,vl);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m4_m(mask,vl);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8_m(vbool2_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m8_m(mask,vl);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32mf2_m(mask,vl);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m1_m(mask,vl);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m2_m(mask,vl);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m4_m(mask,vl);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m8_m(mask,vl);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m1_m(mask,vl);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m2_m(mask,vl);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m4_m(mask,vl);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m8_m(mask,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-2.C
new file mode 100644
index 00000000000..e1434c788e0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf8_m(mask,31);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf4_m(mask,31);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf2_m(mask,31);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m1_m(mask,31);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m2_m(mask,31);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4_m(vbool2_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m4_m(mask,31);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8_m(vbool1_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m8_m(mask,31);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16mf4_m(mask,31);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16mf2_m(mask,31);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m1_m(mask,31);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m2_m(mask,31);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m4_m(mask,31);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8_m(vbool2_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m8_m(mask,31);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32mf2_m(mask,31);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m1_m(mask,31);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m2_m(mask,31);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m4_m(mask,31);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m8_m(mask,31);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m1_m(mask,31);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m2_m(mask,31);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m4_m(mask,31);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m8_m(mask,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-3.C
new file mode 100644
index 00000000000..d9c51908e1e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_m-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf8_m(mask,32);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf4_m(mask,32);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8mf2_m(mask,32);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m1_m(mask,32);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m2_m(mask,32);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4_m(vbool2_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m4_m(mask,32);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8_m(vbool1_t mask,size_t vl)
+{
+    return __riscv_vid_v_u8m8_m(mask,32);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16mf4_m(mask,32);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16mf2_m(mask,32);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m1_m(mask,32);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m2_m(mask,32);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m4_m(mask,32);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8_m(vbool2_t mask,size_t vl)
+{
+    return __riscv_vid_v_u16m8_m(mask,32);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32mf2_m(mask,32);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m1_m(mask,32);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m2_m(mask,32);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m4_m(mask,32);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8_m(vbool4_t mask,size_t vl)
+{
+    return __riscv_vid_v_u32m8_m(mask,32);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1_m(vbool64_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m1_m(mask,32);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2_m(vbool32_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m2_m(mask,32);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4_m(vbool16_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m4_m(mask,32);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8_m(vbool8_t mask,size_t vl)
+{
+    return __riscv_vid_v_u64m8_m(mask,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-1.C
new file mode 100644
index 00000000000..c407d19fd7a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf8_mu(mask,maskedoff,vl);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf4_mu(mask,maskedoff,vl);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf2_mu(mask,maskedoff,vl);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m1_mu(mask,maskedoff,vl);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m2_mu(mask,maskedoff,vl);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m4_mu(mask,maskedoff,vl);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m8_mu(mask,maskedoff,vl);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16mf4_mu(mask,maskedoff,vl);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16mf2_mu(mask,maskedoff,vl);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m1_mu(mask,maskedoff,vl);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m2_mu(mask,maskedoff,vl);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m4_mu(mask,maskedoff,vl);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m8_mu(mask,maskedoff,vl);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32mf2_mu(mask,maskedoff,vl);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m1_mu(mask,maskedoff,vl);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m2_mu(mask,maskedoff,vl);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m4_mu(mask,maskedoff,vl);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m8_mu(mask,maskedoff,vl);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m1_mu(mask,maskedoff,vl);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m2_mu(mask,maskedoff,vl);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m4_mu(mask,maskedoff,vl);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m8_mu(mask,maskedoff,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-2.C
new file mode 100644
index 00000000000..2f55e49c525
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf8_mu(mask,maskedoff,31);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf4_mu(mask,maskedoff,31);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf2_mu(mask,maskedoff,31);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m1_mu(mask,maskedoff,31);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m2_mu(mask,maskedoff,31);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m4_mu(mask,maskedoff,31);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m8_mu(mask,maskedoff,31);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16mf4_mu(mask,maskedoff,31);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16mf2_mu(mask,maskedoff,31);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m1_mu(mask,maskedoff,31);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m2_mu(mask,maskedoff,31);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m4_mu(mask,maskedoff,31);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m8_mu(mask,maskedoff,31);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32mf2_mu(mask,maskedoff,31);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m1_mu(mask,maskedoff,31);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m2_mu(mask,maskedoff,31);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m4_mu(mask,maskedoff,31);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m8_mu(mask,maskedoff,31);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m1_mu(mask,maskedoff,31);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m2_mu(mask,maskedoff,31);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m4_mu(mask,maskedoff,31);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m8_mu(mask,maskedoff,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-3.C
new file mode 100644
index 00000000000..3e3b5a85cf7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vid_v_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vid_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf8_mu(mask,maskedoff,32);
+}
+
+
+vuint8mf4_t test___riscv_vid_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf4_mu(mask,maskedoff,32);
+}
+
+
+vuint8mf2_t test___riscv_vid_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8mf2_mu(mask,maskedoff,32);
+}
+
+
+vuint8m1_t test___riscv_vid_v_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m1_mu(mask,maskedoff,32);
+}
+
+
+vuint8m2_t test___riscv_vid_v_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m2_mu(mask,maskedoff,32);
+}
+
+
+vuint8m4_t test___riscv_vid_v_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m4_mu(mask,maskedoff,32);
+}
+
+
+vuint8m8_t test___riscv_vid_v_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u8m8_mu(mask,maskedoff,32);
+}
+
+
+vuint16mf4_t test___riscv_vid_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16mf4_mu(mask,maskedoff,32);
+}
+
+
+vuint16mf2_t test___riscv_vid_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16mf2_mu(mask,maskedoff,32);
+}
+
+
+vuint16m1_t test___riscv_vid_v_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m1_mu(mask,maskedoff,32);
+}
+
+
+vuint16m2_t test___riscv_vid_v_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m2_mu(mask,maskedoff,32);
+}
+
+
+vuint16m4_t test___riscv_vid_v_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m4_mu(mask,maskedoff,32);
+}
+
+
+vuint16m8_t test___riscv_vid_v_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u16m8_mu(mask,maskedoff,32);
+}
+
+
+vuint32mf2_t test___riscv_vid_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32mf2_mu(mask,maskedoff,32);
+}
+
+
+vuint32m1_t test___riscv_vid_v_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m1_mu(mask,maskedoff,32);
+}
+
+
+vuint32m2_t test___riscv_vid_v_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m2_mu(mask,maskedoff,32);
+}
+
+
+vuint32m4_t test___riscv_vid_v_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m4_mu(mask,maskedoff,32);
+}
+
+
+vuint32m8_t test___riscv_vid_v_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u32m8_mu(mask,maskedoff,32);
+}
+
+
+vuint64m1_t test___riscv_vid_v_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m1_mu(mask,maskedoff,32);
+}
+
+
+vuint64m2_t test___riscv_vid_v_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m2_mu(mask,maskedoff,32);
+}
+
+
+vuint64m4_t test___riscv_vid_v_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m4_mu(mask,maskedoff,32);
+}
+
+
+vuint64m8_t test___riscv_vid_v_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl)
+{
+    return __riscv_vid_v_u64m8_mu(mask,maskedoff,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-1.C
new file mode 100644
index 00000000000..c1564036324
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_m_u8mf8(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8(op1,vl);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4(op1,vl);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2(op1,vl);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1(op1,vl);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2(op1,vl);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4(vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4(op1,vl);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8(vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8(op1,vl);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4(op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2(op1,vl);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1(op1,vl);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2(op1,vl);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4(op1,vl);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8(vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8(op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2(op1,vl);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1(op1,vl);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2(op1,vl);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4(op1,vl);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8(op1,vl);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1(op1,vl);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2(op1,vl);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4(op1,vl);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8(op1,vl);
+}
+
+
+vuint8mf8_t test___riscv_viota_m_u8mf8_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8_m(mask,op1,vl);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4_m(mask,op1,vl);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2_m(mask,op1,vl);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1_m(mask,op1,vl);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2_m(mask,op1,vl);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4_m(mask,op1,vl);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8_m(mask,op1,vl);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4_m(mask,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2_m(mask,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1_m(mask,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2_m(mask,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4_m(mask,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8_m(mask,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2_m(mask,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1_m(mask,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2_m(mask,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4_m(mask,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8_m(mask,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1_m(mask,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2_m(mask,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4_m(mask,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-2.C
new file mode 100644
index 00000000000..4c554393849
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_m_u8mf8(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8(op1,31);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4(op1,31);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2(op1,31);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1(op1,31);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2(op1,31);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4(vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4(op1,31);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8(vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8(op1,31);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4(op1,31);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2(op1,31);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1(op1,31);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2(op1,31);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4(op1,31);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8(vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8(op1,31);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2(op1,31);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1(op1,31);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2(op1,31);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4(op1,31);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8(op1,31);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1(op1,31);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2(op1,31);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4(op1,31);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8(op1,31);
+}
+
+
+vuint8mf8_t test___riscv_viota_m_u8mf8_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8_m(mask,op1,31);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4_m(mask,op1,31);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2_m(mask,op1,31);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1_m(mask,op1,31);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2_m(mask,op1,31);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4_m(mask,op1,31);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8_m(mask,op1,31);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4_m(mask,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2_m(mask,op1,31);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1_m(mask,op1,31);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2_m(mask,op1,31);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4_m(mask,op1,31);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8_m(mask,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2_m(mask,op1,31);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1_m(mask,op1,31);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2_m(mask,op1,31);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4_m(mask,op1,31);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8_m(mask,op1,31);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1_m(mask,op1,31);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2_m(mask,op1,31);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4_m(mask,op1,31);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-3.C
new file mode 100644
index 00000000000..28e358738b7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_m-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_m_u8mf8(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8(op1,32);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4(op1,32);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2(op1,32);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1(op1,32);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2(op1,32);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4(vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4(op1,32);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8(vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8(op1,32);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4(op1,32);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2(op1,32);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1(op1,32);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2(op1,32);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4(op1,32);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8(vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8(op1,32);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2(op1,32);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1(op1,32);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2(op1,32);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4(op1,32);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8(vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8(op1,32);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1(vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1(op1,32);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2(vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2(op1,32);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4(vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4(op1,32);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8(vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8(op1,32);
+}
+
+
+vuint8mf8_t test___riscv_viota_m_u8mf8_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8_m(mask,op1,32);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4_m(mask,op1,32);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2_m(mask,op1,32);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1_m(mask,op1,32);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2_m(mask,op1,32);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4_m(mask,op1,32);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8_m(vbool1_t mask,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8_m(mask,op1,32);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4_m(mask,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2_m(mask,op1,32);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1_m(mask,op1,32);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2_m(mask,op1,32);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4_m(mask,op1,32);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8_m(vbool2_t mask,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8_m(mask,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2_m(mask,op1,32);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1_m(mask,op1,32);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2_m(mask,op1,32);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4_m(mask,op1,32);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8_m(vbool4_t mask,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8_m(mask,op1,32);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1_m(vbool64_t mask,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1_m(mask,op1,32);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2_m(vbool32_t mask,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2_m(mask,op1,32);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4_m(vbool16_t mask,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4_m(mask,op1,32);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8_m(vbool8_t mask,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-1.C
new file mode 100644
index 00000000000..695147401af
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_m_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4_mu(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8_mu(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-2.C
new file mode 100644
index 00000000000..dfc2053c7a2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_m_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4_mu(mask,maskedoff,op1,31);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8_mu(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-3.C
new file mode 100644
index 00000000000..3bac3f1583e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_m_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf8_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint8mf4_t test___riscv_viota_m_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf4_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint8mf2_t test___riscv_viota_m_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8mf2_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint8m1_t test___riscv_viota_m_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m1_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint8m2_t test___riscv_viota_m_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m2_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint8m4_t test___riscv_viota_m_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m4_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint8m8_t test___riscv_viota_m_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_m_u8m8_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint16mf4_t test___riscv_viota_m_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf4_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_viota_m_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16mf2_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint16m1_t test___riscv_viota_m_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m1_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint16m2_t test___riscv_viota_m_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m2_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint16m4_t test___riscv_viota_m_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m4_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint16m8_t test___riscv_viota_m_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_m_u16m8_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_viota_m_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32mf2_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint32m1_t test___riscv_viota_m_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m1_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint32m2_t test___riscv_viota_m_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m2_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint32m4_t test___riscv_viota_m_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m4_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint32m8_t test___riscv_viota_m_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_m_u32m8_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint64m1_t test___riscv_viota_m_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m1_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint64m2_t test___riscv_viota_m_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m2_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint64m4_t test___riscv_viota_m_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m4_mu(mask,maskedoff,op1,32);
+}
+
+
+vuint64m8_t test___riscv_viota_m_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_m_u64m8_mu(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-1.C
new file mode 100644
index 00000000000..5ed01e60e0e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tu(vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint8mf4_t test___riscv_viota_tu(vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint8mf2_t test___riscv_viota_tu(vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint8m1_t test___riscv_viota_tu(vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint8m2_t test___riscv_viota_tu(vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint8m4_t test___riscv_viota_tu(vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint8m8_t test___riscv_viota_tu(vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint16mf4_t test___riscv_viota_tu(vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_viota_tu(vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_viota_tu(vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_viota_tu(vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_viota_tu(vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_viota_tu(vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_viota_tu(vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_viota_tu(vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_viota_tu(vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_viota_tu(vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_viota_tu(vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_viota_tu(vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_viota_tu(vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_viota_tu(vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_viota_tu(vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-2.C
new file mode 100644
index 00000000000..4cc263fb196
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tu(vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint8mf4_t test___riscv_viota_tu(vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint8mf2_t test___riscv_viota_tu(vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint8m1_t test___riscv_viota_tu(vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint8m2_t test___riscv_viota_tu(vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint8m4_t test___riscv_viota_tu(vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint8m8_t test___riscv_viota_tu(vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint16mf4_t test___riscv_viota_tu(vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_viota_tu(vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint16m1_t test___riscv_viota_tu(vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint16m2_t test___riscv_viota_tu(vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint16m4_t test___riscv_viota_tu(vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint16m8_t test___riscv_viota_tu(vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_viota_tu(vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint32m1_t test___riscv_viota_tu(vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint32m2_t test___riscv_viota_tu(vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint32m4_t test___riscv_viota_tu(vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint32m8_t test___riscv_viota_tu(vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint64m1_t test___riscv_viota_tu(vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint64m2_t test___riscv_viota_tu(vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint64m4_t test___riscv_viota_tu(vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+vuint64m8_t test___riscv_viota_tu(vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-3.C
new file mode 100644
index 00000000000..398a0835bcf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tu(vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint8mf4_t test___riscv_viota_tu(vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint8mf2_t test___riscv_viota_tu(vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint8m1_t test___riscv_viota_tu(vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint8m2_t test___riscv_viota_tu(vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint8m4_t test___riscv_viota_tu(vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint8m8_t test___riscv_viota_tu(vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint16mf4_t test___riscv_viota_tu(vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_viota_tu(vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint16m1_t test___riscv_viota_tu(vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint16m2_t test___riscv_viota_tu(vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint16m4_t test___riscv_viota_tu(vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint16m8_t test___riscv_viota_tu(vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_viota_tu(vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint32m1_t test___riscv_viota_tu(vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint32m2_t test___riscv_viota_tu(vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint32m4_t test___riscv_viota_tu(vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint32m8_t test___riscv_viota_tu(vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint64m1_t test___riscv_viota_tu(vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint64m2_t test___riscv_viota_tu(vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint64m4_t test___riscv_viota_tu(vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+vuint64m8_t test___riscv_viota_tu(vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tu(maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-1.C
new file mode 100644
index 00000000000..cc973938e74
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tum(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint8mf4_t test___riscv_viota_tum(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint8mf2_t test___riscv_viota_tum(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m1_t test___riscv_viota_tum(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m2_t test___riscv_viota_tum(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m4_t test___riscv_viota_tum(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m8_t test___riscv_viota_tum(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint16mf4_t test___riscv_viota_tum(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_viota_tum(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_viota_tum(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_viota_tum(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_viota_tum(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_viota_tum(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_viota_tum(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_viota_tum(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_viota_tum(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_viota_tum(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_viota_tum(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_viota_tum(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_viota_tum(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_viota_tum(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_viota_tum(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-2.C
new file mode 100644
index 00000000000..7b27e5a4710
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tum(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint8mf4_t test___riscv_viota_tum(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint8mf2_t test___riscv_viota_tum(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint8m1_t test___riscv_viota_tum(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint8m2_t test___riscv_viota_tum(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint8m4_t test___riscv_viota_tum(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint8m8_t test___riscv_viota_tum(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint16mf4_t test___riscv_viota_tum(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_viota_tum(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint16m1_t test___riscv_viota_tum(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint16m2_t test___riscv_viota_tum(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint16m4_t test___riscv_viota_tum(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint16m8_t test___riscv_viota_tum(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_viota_tum(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint32m1_t test___riscv_viota_tum(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint32m2_t test___riscv_viota_tum(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint32m4_t test___riscv_viota_tum(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint32m8_t test___riscv_viota_tum(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint64m1_t test___riscv_viota_tum(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint64m2_t test___riscv_viota_tum(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint64m4_t test___riscv_viota_tum(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+vuint64m8_t test___riscv_viota_tum(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-3.C
new file mode 100644
index 00000000000..7aa1cd1d3ab
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tum(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint8mf4_t test___riscv_viota_tum(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint8mf2_t test___riscv_viota_tum(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint8m1_t test___riscv_viota_tum(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint8m2_t test___riscv_viota_tum(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint8m4_t test___riscv_viota_tum(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint8m8_t test___riscv_viota_tum(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint16mf4_t test___riscv_viota_tum(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_viota_tum(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint16m1_t test___riscv_viota_tum(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint16m2_t test___riscv_viota_tum(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint16m4_t test___riscv_viota_tum(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint16m8_t test___riscv_viota_tum(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_viota_tum(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint32m1_t test___riscv_viota_tum(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint32m2_t test___riscv_viota_tum(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint32m4_t test___riscv_viota_tum(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint32m8_t test___riscv_viota_tum(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint64m1_t test___riscv_viota_tum(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint64m2_t test___riscv_viota_tum(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint64m4_t test___riscv_viota_tum(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+vuint64m8_t test___riscv_viota_tum(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tum(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-1.C
new file mode 100644
index 00000000000..a3b7d3274a5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tumu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8mf4_t test___riscv_viota_tumu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8mf2_t test___riscv_viota_tumu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m1_t test___riscv_viota_tumu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m2_t test___riscv_viota_tumu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m4_t test___riscv_viota_tumu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint8m8_t test___riscv_viota_tumu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16mf4_t test___riscv_viota_tumu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16mf2_t test___riscv_viota_tumu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m1_t test___riscv_viota_tumu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m2_t test___riscv_viota_tumu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m4_t test___riscv_viota_tumu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint16m8_t test___riscv_viota_tumu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32mf2_t test___riscv_viota_tumu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m1_t test___riscv_viota_tumu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m2_t test___riscv_viota_tumu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m4_t test___riscv_viota_tumu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint32m8_t test___riscv_viota_tumu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m1_t test___riscv_viota_tumu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m2_t test___riscv_viota_tumu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m4_t test___riscv_viota_tumu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+vuint64m8_t test___riscv_viota_tumu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-2.C
new file mode 100644
index 00000000000..44ae504f9f1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tumu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint8mf4_t test___riscv_viota_tumu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint8mf2_t test___riscv_viota_tumu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint8m1_t test___riscv_viota_tumu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint8m2_t test___riscv_viota_tumu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint8m4_t test___riscv_viota_tumu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint8m8_t test___riscv_viota_tumu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint16mf4_t test___riscv_viota_tumu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint16mf2_t test___riscv_viota_tumu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint16m1_t test___riscv_viota_tumu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint16m2_t test___riscv_viota_tumu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint16m4_t test___riscv_viota_tumu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint16m8_t test___riscv_viota_tumu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint32mf2_t test___riscv_viota_tumu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint32m1_t test___riscv_viota_tumu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint32m2_t test___riscv_viota_tumu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint32m4_t test___riscv_viota_tumu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint32m8_t test___riscv_viota_tumu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint64m1_t test___riscv_viota_tumu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint64m2_t test___riscv_viota_tumu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint64m4_t test___riscv_viota_tumu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+vuint64m8_t test___riscv_viota_tumu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-3.C
new file mode 100644
index 00000000000..ab777525ce2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/viota_m_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_viota_tumu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint8mf4_t test___riscv_viota_tumu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint8mf2_t test___riscv_viota_tumu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint8m1_t test___riscv_viota_tumu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint8m2_t test___riscv_viota_tumu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint8m4_t test___riscv_viota_tumu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint8m8_t test___riscv_viota_tumu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint16mf4_t test___riscv_viota_tumu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint16mf2_t test___riscv_viota_tumu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint16m1_t test___riscv_viota_tumu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint16m2_t test___riscv_viota_tumu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint16m4_t test___riscv_viota_tumu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint16m8_t test___riscv_viota_tumu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint32mf2_t test___riscv_viota_tumu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint32m1_t test___riscv_viota_tumu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint32m2_t test___riscv_viota_tumu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint32m4_t test___riscv_viota_tumu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint32m8_t test___riscv_viota_tumu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint64m1_t test___riscv_viota_tumu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint64m2_t test___riscv_viota_tumu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint64m4_t test___riscv_viota_tumu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+vuint64m8_t test___riscv_viota_tumu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl)
+{
+    return __riscv_viota_tumu(mask,maskedoff,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-1.C
new file mode 100644
index 00000000000..a43aa6b7c0b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-1.C
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b1(base,vl);
+}
+
+
+vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b2(base,vl);
+}
+
+
+vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b4(base,vl);
+}
+
+
+vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b8(base,vl);
+}
+
+
+vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b16(base,vl);
+}
+
+
+vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b32(base,vl);
+}
+
+
+vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b64(base,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-2.C
new file mode 100644
index 00000000000..3b416545952
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-2.C
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b1(base,31);
+}
+
+
+vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b2(base,31);
+}
+
+
+vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b4(base,31);
+}
+
+
+vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b8(base,31);
+}
+
+
+vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b16(base,31);
+}
+
+
+vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b32(base,31);
+}
+
+
+vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b64(base,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-3.C
new file mode 100644
index 00000000000..eaa0220aff5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vlm_v-3.C
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool1_t test___riscv_vlm_v_b1(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b1(base,32);
+}
+
+
+vbool2_t test___riscv_vlm_v_b2(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b2(base,32);
+}
+
+
+vbool4_t test___riscv_vlm_v_b4(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b4(base,32);
+}
+
+
+vbool8_t test___riscv_vlm_v_b8(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b8(base,32);
+}
+
+
+vbool16_t test___riscv_vlm_v_b16(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b16(base,32);
+}
+
+
+vbool32_t test___riscv_vlm_v_b32(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b32(base,32);
+}
+
+
+vbool64_t test___riscv_vlm_v_b64(const uint8_t* base,size_t vl)
+{
+    return __riscv_vlm_v_b64(base,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vlm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-1.C
new file mode 100644
index 00000000000..ead18fd60bb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-1.C
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void test___riscv_vsm(uint8_t* base,vbool1_t value,size_t vl)
+{
+    __riscv_vsm(base,value,vl);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool2_t value,size_t vl)
+{
+    __riscv_vsm(base,value,vl);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool4_t value,size_t vl)
+{
+    __riscv_vsm(base,value,vl);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool8_t value,size_t vl)
+{
+    __riscv_vsm(base,value,vl);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool16_t value,size_t vl)
+{
+    __riscv_vsm(base,value,vl);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool32_t value,size_t vl)
+{
+    __riscv_vsm(base,value,vl);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool64_t value,size_t vl)
+{
+    __riscv_vsm(base,value,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-2.C
new file mode 100644
index 00000000000..b20c298dc0c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-2.C
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void test___riscv_vsm(uint8_t* base,vbool1_t value,size_t vl)
+{
+    __riscv_vsm(base,value,31);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool2_t value,size_t vl)
+{
+    __riscv_vsm(base,value,31);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool4_t value,size_t vl)
+{
+    __riscv_vsm(base,value,31);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool8_t value,size_t vl)
+{
+    __riscv_vsm(base,value,31);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool16_t value,size_t vl)
+{
+    __riscv_vsm(base,value,31);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool32_t value,size_t vl)
+{
+    __riscv_vsm(base,value,31);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool64_t value,size_t vl)
+{
+    __riscv_vsm(base,value,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-3.C
new file mode 100644
index 00000000000..4b5e34f8c77
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsm_v-3.C
@@ -0,0 +1,55 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+void test___riscv_vsm(uint8_t* base,vbool1_t value,size_t vl)
+{
+    __riscv_vsm(base,value,32);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool2_t value,size_t vl)
+{
+    __riscv_vsm(base,value,32);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool4_t value,size_t vl)
+{
+    __riscv_vsm(base,value,32);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool8_t value,size_t vl)
+{
+    __riscv_vsm(base,value,32);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool16_t value,size_t vl)
+{
+    __riscv_vsm(base,value,32);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool32_t value,size_t vl)
+{
+    __riscv_vsm(base,value,32);
+}
+
+
+void test___riscv_vsm(uint8_t* base,vbool64_t value,size_t vl)
+{
+    __riscv_vsm(base,value,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsm\.v\s+v[0-9]+,\s*0?\([a-x0-9]+\)\s+} 1 } } */
-- 
2.36.1