From: "Junxian Zhu" <zhujunxian@oss.cipunited.com>
To: <gcc-patches@gcc.gnu.org>
Cc: <doko@debian.org>, <syq@debian.org>,
"Junxian Zhu" <zhujunxian@oss.cipunited.com>
Subject: [PATCH] Add pattern for clo
Date: Fri, 17 Feb 2023 16:35:56 +0800 [thread overview]
Message-ID: <20230217083531.3409405-1-zhujunxian@oss.cipunited.com> (raw)
[-- Attachment #1: Type: text/plain, Size: 3341 bytes --]
From: Junxian Zhu <zhujunxian@oss.cipunited.com>
gcc/ChangeLog:
* config/mips/mips.md (*clo<mode>2): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/mips/clz.c: New test.
* gcc.target/mips/clz.c: New test.
* gcc.target/mips/mips.exp: New option HAS_CLZ.
Signed-off-by: Junxian Zhu <zhujunxian@oss.cipunited.com>
---
gcc/config/mips/mips.md | 9 +++++++++
gcc/testsuite/gcc.target/mips/clo.c | 11 +++++++++++
gcc/testsuite/gcc.target/mips/clz.c | 10 ++++++++++
gcc/testsuite/gcc.target/mips/mips.exp | 3 +++
4 files changed, 33 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/mips/clo.c
create mode 100644 gcc/testsuite/gcc.target/mips/clz.c
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index e3bf32a3430..10607a57efc 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -3165,6 +3165,15 @@
[(set_attr "type" "clz")
(set_attr "mode" "<MODE>")])
+
+(define_insn "*clo<mode>2"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (clz:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))))]
+ "ISA_HAS_CLZ_CLO"
+ "<d>clo\t%0,%1"
+ [(set_attr "type" "clz")
+ (set_attr "mode" "<MODE>")])
+
;;
;; ...................
;;
diff --git a/gcc/testsuite/gcc.target/mips/clo.c b/gcc/testsuite/gcc.target/mips/clo.c
new file mode 100644
index 00000000000..91f29a1322a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/clo.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "(HAS_CLZ)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 unsigned int foo(unsigned int x)
+{
+ return __builtin_clz (~x);
+}
+
+/* { dg-final { scan-assembler-not "\tclz\t" } } */
+/* { dg-final { scan-assembler "\tclo\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/clz.c b/gcc/testsuite/gcc.target/mips/clz.c
new file mode 100644
index 00000000000..74e6edb90aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/clz.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "(HAS_CLZ)" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+NOMIPS16 unsigned int foo(unsigned int x)
+{
+ return __builtin_clz (x);
+}
+
+/* { dg-final { scan-assembler "\tclz\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp
index 025fbe78359..ac3ab129541 100644
--- a/gcc/testsuite/gcc.target/mips/mips.exp
+++ b/gcc/testsuite/gcc.target/mips/mips.exp
@@ -252,6 +252,7 @@ set mips_option_groups {
warnings "-w"
dump "-fdump-.*"
ins "HAS_INS"
+ clz "HAS_CLZ"
dmul "NOT_HAS_DMUL"
ldc "HAS_LDC"
movn "HAS_MOVN"
@@ -1198,11 +1199,13 @@ proc mips-dg-options { args } {
#
# - paired-single instructions(*)
# - odd numbered single precision registers
+ # - clz clo instructions
#
# (*) Note that we don't support MIPS V at the moment.
} elseif { $isa_rev < 1
&& ([mips_have_test_option_p options "-mpaired-single"]
|| ([mips_have_test_option_p options "-modd-spreg"]
+ || [mips_have_test_option_p options "HAS_CLZ"]
&& ![mips_have_test_option_p options "-mfp64"]))} {
if { $gp_size == 32 } {
mips_make_test_option options "-mips32"
--
2.39.1
reply other threads:[~2023-02-17 8:36 UTC|newest]
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