From: Liao Shihua <shihua@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, Liao Shihua <shihua@iscas.ac.cn>
Subject: [PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions
Date: Mon, 20 Feb 2023 15:01:23 +0800 [thread overview]
Message-ID: <20230220070125.2291-4-shihua@iscas.ac.cn> (raw)
In-Reply-To: <20230220070125.2291-1-shihua@iscas.ac.cn>
This patch supports Zkne and Zknd extension.
It includes instruction's machine description and built-in funtions.
gcc/ChangeLog:
* config/riscv/constraints.md (D03): Add constants of bs and rnum.
(DsA):
* config/riscv/crypto.md (riscv_aes32dsi): Add ZKND's and ZKNE's instructions.
(riscv_aes32dsmi):
(riscv_aes64ds):
(riscv_aes64dsm):
(riscv_aes64im):
(riscv_aes64ks1i):
(riscv_aes64ks2):
(riscv_aes32esi):
(riscv_aes32esmi):
(riscv_aes64es):
(riscv_aes64esm):
* config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL.
* config/riscv/riscv-scalar-crypto.def (DIRECT_BUILTIN): Add ZKND's and ZKNE's built-in functions.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zknd32.c: New test.
* gcc.target/riscv/zknd64.c: New test.
* gcc.target/riscv/zkne32.c: New test.
* gcc.target/riscv/zkne64.c: New test.
Co-Authored-By: SiYu Wu
---
gcc/config/riscv/constraints.md | 8 ++
gcc/config/riscv/crypto.md | 121 +++++++++++++++++++++++
gcc/config/riscv/riscv-builtins.cc | 5 +
gcc/config/riscv/riscv-scalar-crypto.def | 15 +++
gcc/testsuite/gcc.target/riscv/zknd32.c | 18 ++++
gcc/testsuite/gcc.target/riscv/zknd64.c | 36 +++++++
gcc/testsuite/gcc.target/riscv/zkne32.c | 18 ++++
gcc/testsuite/gcc.target/riscv/zkne64.c | 30 ++++++
8 files changed, 251 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 3637380ee47..3f46f14b10f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -83,6 +83,14 @@
(and (match_code "const_int")
(match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
+(define_constraint "D03"
+ "0, 1, 2 or 3 immediate"
+ (match_test "IN_RANGE (ival, 0, 3)"))
+
+(define_constraint "DsA"
+ "0 - 10 immediate"
+ (match_test "IN_RANGE (ival, 0, 10)"))
+
;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
;; not available in RV32.
(define_constraint "G"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index a270036e39b..7568466ec97 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -33,6 +33,21 @@
;; Zbkx unspecs
UNSPEC_XPERM8
UNSPEC_XPERM4
+
+ ;; Zknd unspecs
+ UNSPEC_AES_DSI
+ UNSPEC_AES_DSMI
+ UNSPEC_AES_DS
+ UNSPEC_AES_DSM
+ UNSPEC_AES_IM
+ UNSPEC_AES_KS1I
+ UNSPEC_AES_KS2
+
+ ;; Zkne unspecs
+ UNSPEC_AES_ES
+ UNSPEC_AES_ESM
+ UNSPEC_AES_ESI
+ UNSPEC_AES_ESMI
])
;; ZBKB extension
@@ -126,3 +141,109 @@
"TARGET_ZBKX"
"xperm8\t%0,%1,%2"
[(set_attr "type" "crypto")])
+
+;; ZKND extension
+
+(define_insn "riscv_aes32dsi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "D03")]
+ UNSPEC_AES_DSI))]
+ "TARGET_ZKND && !TARGET_64BIT"
+ "aes32dsi\t%0,%1,%2,%3"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32dsmi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "D03")]
+ UNSPEC_AES_DSMI))]
+ "TARGET_ZKND && !TARGET_64BIT"
+ "aes32dsmi\t%0,%1,%2,%3"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ds"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_DS))]
+ "TARGET_ZKND && TARGET_64BIT"
+ "aes64ds\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64dsm"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_DSM))]
+ "TARGET_ZKND && TARGET_64BIT"
+ "aes64dsm\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64im"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_AES_IM))]
+ "TARGET_ZKND && TARGET_64BIT"
+ "aes64im\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ks1i"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "DsA")]
+ UNSPEC_AES_KS1I))]
+ "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
+ "aes64ks1i\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ks2"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_KS2))]
+ "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
+ "aes64ks2\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+;; ZKNE extension
+
+(define_insn "riscv_aes32esi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "D03")]
+ UNSPEC_AES_ESI))]
+ "TARGET_ZKNE && !TARGET_64BIT"
+ "aes32esi\t%0,%1,%2,%3"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32esmi"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")
+ (match_operand:SI 3 "register_operand" "D03")]
+ UNSPEC_AES_ESMI))]
+ "TARGET_ZKNE && !TARGET_64BIT"
+ "aes32esmi\t%0,%1,%2,%3"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64es"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_ES))]
+ "TARGET_ZKNE && TARGET_64BIT"
+ "aes64es\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64esm"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+ (match_operand:DI 2 "register_operand" "r")]
+ UNSPEC_AES_ESM))]
+ "TARGET_ZKNE && TARGET_64BIT"
+ "aes64esm\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index f0d60709c7d..6632009734b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -106,6 +106,11 @@ AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT)
AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT)
AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
+AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT)
+AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
+AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
+AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
+AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
AVAIL (always, (!0))
/* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
index e4c97acbc05..fe1a4e13d2d 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -43,3 +43,18 @@ RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI,
RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+
+// ZKND
+DIRECT_BUILTIN (aes32dsi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes32dsmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes64ds, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64dsm, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne_or_zknd),
+DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne_or_zknd),
+
+// ZKNE
+DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c b/gcc/testsuite/gcc.target/riscv/zknd32.c
new file mode 100644
index 00000000000..203e3337d2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknd32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zknd -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2, int bs)
+{
+ return __builtin_riscv_aes32dsi(rs1,rs2,bs);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2, int bs)
+{
+ return __builtin_riscv_aes32dsmi(rs1,rs2,bs);
+}
+
+/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.target/riscv/zknd64.c
new file mode 100644
index 00000000000..396c512fd3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknd64.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknd -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+ return __builtin_riscv_aes64ds(rs1,rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+ return __builtin_riscv_aes64dsm(rs1,rs2);
+}
+
+int64_t foo3(int64_t rs1, int rnum)
+{
+ return __builtin_riscv_aes64ks1i(rs1,rnum);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+ return __builtin_riscv_aes64ks2(rs1,rs2);
+}
+
+int64_t foo5(int64_t rs1)
+{
+ return __builtin_riscv_aes64im(rs1);
+}
+
+/* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */
+/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
+/* { dg-final { scan-assembler-times "aes64im" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zkne32.c b/gcc/testsuite/gcc.target/riscv/zkne32.c
new file mode 100644
index 00000000000..b3bf984a140
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zkne32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zkne -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2, int bs)
+{
+ return __builtin_riscv_aes32esi(rs1, rs2, bs);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2, int bs)
+{
+ return __builtin_riscv_aes32esmi(rs1, rs2, bs);
+}
+
+/* { dg-final { scan-assembler-times "aes32esi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zkne64.c b/gcc/testsuite/gcc.target/riscv/zkne64.c
new file mode 100644
index 00000000000..894bab44fb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zkne64.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zkne -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+ return __builtin_riscv_aes64es(rs1,rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+ return __builtin_riscv_aes64esm(rs1,rs2);
+}
+
+int64_t foo3(int64_t rs1, int rnum)
+{
+ return __builtin_riscv_aes64ks1i(rs1,rnum);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+ return __builtin_riscv_aes64ks2(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "aes64es\t" 1 } } */
+/* { dg-final { scan-assembler-times "aes64esm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
--
2.38.1.windows.1
next prev parent reply other threads:[~2023-02-20 10:15 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-20 7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
2023-02-20 7:01 ` [PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
2023-02-20 7:01 ` [PATCH V3 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Liao Shihua
2023-02-20 7:01 ` Liao Shihua [this message]
2023-02-20 7:01 ` [PATCH V3 4/5] RISC-V: Implement ZKNH extension Liao Shihua
2023-02-20 7:01 ` [PATCH V3 5/5] RISC-V: Implement ZKSH and ZKSED extensions Liao Shihua
2023-03-05 10:19 ` [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Kito Cheng
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