From: Liao Shihua <shihua@iscas.ac.cn>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, Liao Shihua <shihua@iscas.ac.cn>
Subject: [PATCH V3 4/5] RISC-V: Implement ZKNH extension
Date: Mon, 20 Feb 2023 15:01:24 +0800 [thread overview]
Message-ID: <20230220070125.2291-5-shihua@iscas.ac.cn> (raw)
In-Reply-To: <20230220070125.2291-1-shihua@iscas.ac.cn>
This patch supports Zknh extension.
It includes instruction's machine description and built-in funtions.
gcc/ChangeLog:
* config/riscv/crypto.md (riscv_sha256sig0_<mode>): Add ZKNH's instructions.
(riscv_sha256sig1_<mode>):
(riscv_sha256sum0_<mode>):
(riscv_sha256sum1_<mode>):
(riscv_sha512sig0h):
(riscv_sha512sig0l):
(riscv_sha512sig1h):
(riscv_sha512sig1l):
(riscv_sha512sum0r):
(riscv_sha512sum1r):
(riscv_sha512sig0):
(riscv_sha512sig1):
(riscv_sha512sum0):
(riscv_sha512sum1):
* config/riscv/riscv-builtins.cc (AVAIL): And ZKNH's AVAIL.
* config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): And ZKNH's built-in functions.
(DIRECT_BUILTIN):
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zknh-sha256.c: New test.
* gcc.target/riscv/zknh-sha512-32.c: New test.
* gcc.target/riscv/zknh-sha512-64.c: New test.
Co-Authored-By: SiYu Wu
---
gcc/config/riscv/crypto.md | 138 ++++++++++++++++++
gcc/config/riscv/riscv-builtins.cc | 2 +
gcc/config/riscv/riscv-scalar-crypto.def | 22 +++
gcc/testsuite/gcc.target/riscv/zknh-sha256.c | 28 ++++
.../gcc.target/riscv/zknh-sha512-32.c | 42 ++++++
.../gcc.target/riscv/zknh-sha512-64.c | 31 ++++
6 files changed, 263 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 7568466ec97..17e7440c0b5 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -48,6 +48,22 @@
UNSPEC_AES_ESM
UNSPEC_AES_ESI
UNSPEC_AES_ESMI
+
+ ;; Zknh unspecs
+ UNSPEC_SHA_256_SIG0
+ UNSPEC_SHA_256_SIG1
+ UNSPEC_SHA_256_SUM0
+ UNSPEC_SHA_256_SUM1
+ UNSPEC_SHA_512_SIG0
+ UNSPEC_SHA_512_SIG0H
+ UNSPEC_SHA_512_SIG0L
+ UNSPEC_SHA_512_SIG1
+ UNSPEC_SHA_512_SIG1H
+ UNSPEC_SHA_512_SIG1L
+ UNSPEC_SHA_512_SUM0
+ UNSPEC_SHA_512_SUM0R
+ UNSPEC_SHA_512_SUM1
+ UNSPEC_SHA_512_SUM1R
])
;; ZBKB extension
@@ -247,3 +263,125 @@
"TARGET_ZKNE && TARGET_64BIT"
"aes64esm\t%0,%1,%2"
[(set_attr "type" "crypto")])
+
+;; ZKNH - SHA256
+
+(define_insn "riscv_sha256sig0_<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (unspec:X [(match_operand:X 1 "register_operand" "r")]
+ UNSPEC_SHA_256_SIG0))]
+ "TARGET_ZKNH"
+ "sha256sig0\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sig1_<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (unspec:X [(match_operand:X 1 "register_operand" "r")]
+ UNSPEC_SHA_256_SIG1))]
+ "TARGET_ZKNH"
+ "sha256sig1\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum0_<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (unspec:X [(match_operand:X 1 "register_operand" "r")]
+ UNSPEC_SHA_256_SUM0))]
+ "TARGET_ZKNH"
+ "sha256sum0\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum1_<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (unspec:X [(match_operand:X 1 "register_operand" "r")]
+ UNSPEC_SHA_256_SUM1))]
+ "TARGET_ZKNH"
+ "sha256sum1\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA512
+
+(define_insn "riscv_sha512sig0h"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG0H))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sig0h\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0l"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG0L))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sig0l\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1h"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG1H))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sig1h\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1l"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG1L))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sig1l\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0r"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SUM0R))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sum0r\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum1r"
+ [(set (match_operand:SI 0 "register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")]
+ UNSPEC_SHA_512_SUM1R))]
+ "TARGET_ZKNH && !TARGET_64BIT"
+ "sha512sum1r\t%0,%1,%2"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG0))]
+ "TARGET_ZKNH && TARGET_64BIT"
+ "sha512sig0\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_SHA_512_SIG1))]
+ "TARGET_ZKNH && TARGET_64BIT"
+ "sha512sig1\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_SHA_512_SUM0))]
+ "TARGET_ZKNH && TARGET_64BIT"
+ "sha512sum0\t%0,%1"
+ [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum1"
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+ UNSPEC_SHA_512_SUM1))]
+ "TARGET_ZKNH && TARGET_64BIT"
+ "sha512sum1\t%0,%1"
+ [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 6632009734b..ab5bd52ee7f 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -111,6 +111,8 @@ AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
+AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
+AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
AVAIL (always, (!0))
/* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
index fe1a4e13d2d..d38aad122e5 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -58,3 +58,25 @@ DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+
+// ZKNH
+RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum0_di, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum1_si, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum1_di, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+DIRECT_BUILTIN (sha512sig0h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig0l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+
+DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256.c b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
new file mode 100644
index 00000000000..54329aa6af2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+long foo1(long rs1)
+{
+ return __builtin_riscv_sha256sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+ return __builtin_riscv_sha256sig1(rs1);
+}
+
+long foo3(long rs1)
+{
+ return __builtin_riscv_sha256sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+ return __builtin_riscv_sha256sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
new file mode 100644
index 00000000000..eff9978922e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+ return __builtin_riscv_sha512sig0h(rs1,rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+ return __builtin_riscv_sha512sig0l(rs1,rs2);
+}
+
+int32_t foo3(int32_t rs1, int32_t rs2)
+{
+ return __builtin_riscv_sha512sig1h(rs1,rs2);
+}
+
+int32_t foo4(int32_t rs1, int32_t rs2)
+{
+ return __builtin_riscv_sha512sig1l(rs1,rs2);
+}
+
+int32_t foo5(int32_t rs1, int32_t rs2)
+{
+ return __builtin_riscv_sha512sum0r(rs1,rs2);
+}
+
+int32_t foo6(int32_t rs1, int32_t rs2)
+{
+ return __builtin_riscv_sha512sum1r(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
new file mode 100644
index 00000000000..53cbd302b3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1)
+{
+ return __builtin_riscv_sha512sig0(rs1);
+}
+
+int64_t foo2(int64_t rs1)
+{
+ return __builtin_riscv_sha512sig1(rs1);
+}
+
+int64_t foo3(int64_t rs1)
+{
+ return __builtin_riscv_sha512sum0(rs1);
+}
+
+int64_t foo4(int64_t rs1)
+{
+ return __builtin_riscv_sha512sum1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */
--
2.38.1.windows.1
next prev parent reply other threads:[~2023-02-20 10:15 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-20 7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
2023-02-20 7:01 ` [PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
2023-02-20 7:01 ` [PATCH V3 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Liao Shihua
2023-02-20 7:01 ` [PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions Liao Shihua
2023-02-20 7:01 ` Liao Shihua [this message]
2023-02-20 7:01 ` [PATCH V3 5/5] RISC-V: Implement ZKSH and ZKSED extensions Liao Shihua
2023-03-05 10:19 ` [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Kito Cheng
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