* Re: [PATCH] RISC-V: Optimize the MASK opt generation
@ 2023-03-03 8:54 jiawei
2023-03-03 9:12 ` Feng Wang
0 siblings, 1 reply; 3+ messages in thread
From: jiawei @ 2023-03-03 8:54 UTC (permalink / raw)
To: wangfeng; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 15374 bytes --]
The Mask flag in the single TargetVariable is not enough due to more
and more extensions were added.So I optimize the defination of Mask
flag, please refer to the below case:
There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B),
but these MASK flags can't store into x_target_flags,because the total number
of MASK flags exceed 32. In this patch we can write it like this in this scence.
TargetVariable
int riscv_zvl_flags
Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
The corresponding MASK and TARGET will be automatically generated.
gcc/ChangeLog:
* config/riscv/riscv-opts.h Delete below definations
(MASK_ZICSR): Delete;
(MASK_ZIFENCEI): Delete;
(TARGET_ZICSR): Delete;
(TARGET_ZIFENCEI): Delete;
(MASK_ZAWRS): Delete;
(TARGET_ZAWRS): Delete;
(MASK_ZBA): Delete;
(MASK_ZBB): Delete;
(MASK_ZBC): Delete;
(MASK_ZBS): Delete;
(TARGET_ZBA): Delete;
(TARGET_ZBB): Delete;
(TARGET_ZBC): Delete;
(TARGET_ZBS): Delete;
(MASK_ZFINX): Delete;
(MASK_ZDINX): Delete;
(MASK_ZHINX): Delete;
(MASK_ZHINXMIN): Delete;
(TARGET_ZFINX): Delete;
(TARGET_ZDINX): Delete;
(TARGET_ZHINX): Delete;
(TARGET_ZHINXMIN): Delete;
(MASK_ZBKB): Delete;
(MASK_ZBKC): Delete;
(MASK_ZBKX): Delete;
(MASK_ZKNE): Delete;
(MASK_ZKND): Delete;
(MASK_ZKNH): Delete;
(MASK_ZKR): Delete;
(MASK_ZKSED): Delete;
(MASK_ZKSH): Delete;
(MASK_ZKT): Delete;
(TARGET_ZBKB): Delete;
(TARGET_ZBKC): Delete;
(TARGET_ZBKX): Delete;
(TARGET_ZKNE): Delete;
(TARGET_ZKND): Delete;
(TARGET_ZKNH): Delete;
(TARGET_ZKR): Delete;
(TARGET_ZKSED): Delete;
(TARGET_ZKSH): Delete;
(TARGET_ZKT): Delete;
(MASK_VECTOR_ELEN_32): Delete;
(MASK_VECTOR_ELEN_64): Delete;
(MASK_VECTOR_ELEN_FP_32): Delete;
(MASK_VECTOR_ELEN_FP_64): Delete;
(TARGET_VECTOR_ELEN_32): Delete;
(TARGET_VECTOR_ELEN_64): Delete;
(TARGET_VECTOR_ELEN_FP_32): Delete;
(TARGET_VECTOR_ELEN_FP_64): Delete;
(MASK_ZVL32B): Delete;
(MASK_ZVL64B): Delete;
(MASK_ZVL128B): Delete;
(MASK_ZVL256B): Delete;
(MASK_ZVL512B): Delete;
(MASK_ZVL1024B): Delete;
(MASK_ZVL2048B): Delete;
(MASK_ZVL4096B): Delete;
(MASK_ZVL8192B): Delete;
(MASK_ZVL16384B): Delete;
(MASK_ZVL32768B): Delete;
(MASK_ZVL65536B): Delete;
(TARGET_ZVL32B): Delete;
(TARGET_ZVL64B): Delete;
(TARGET_ZVL128B): Delete;
(TARGET_ZVL256B): Delete;
(TARGET_ZVL512B): Delete;
(TARGET_ZVL1024B): Delete;
(TARGET_ZVL2048B): Delete;
(TARGET_ZVL4096B): Delete;
(TARGET_ZVL8192B): Delete;
(TARGET_ZVL16384B): Delete;
(TARGET_ZVL32768B): Delete;
(TARGET_ZVL65536B): Delete;
(MASK_ZICBOZ): Delete;
(MASK_ZICBOM): Delete;
(MASK_ZICBOP): Delete;
(TARGET_ZICBOZ): Delete;
(TARGET_ZICBOM): Delete;
(TARGET_ZICBOP): Delete;
(MASK_ZFHMIN): Delete;
(MASK_ZFH): Delete;
(TARGET_ZFHMIN): Delete;
(TARGET_ZFH): Delete;
(MASK_ZMMUL): Delete;
(TARGET_ZMMUL): Delete;
(MASK_SVINVAL): Delete;
(MASK_SVNAPOT): Delete;
(TARGET_SVINVAL): Delete;
(TARGET_SVNAPOT): Delete;
* config/riscv/riscv.opt: Add new Mask defination.
* opt-functions.awk: Add new function to find the index
of target variable from extra_target_vars.
* opt-read.awk: Add new function to store the Mask flags.
* opth-gen.awk: Add new function to output the defination of
Mask Macro and Target Macro.
---
gcc/config/riscv/riscv-opts.h | 115 ----------------------------------
gcc/config/riscv/riscv.opt | 90 ++++++++++++++++++++++++++
gcc/opt-functions.awk | 11 ++++
gcc/opt-read.awk | 16 ++++-
gcc/opth-gen.awk | 22 +++++++
5 files changed, 138 insertions(+), 116 deletions(-)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 25fd85b09b1..7cf28838cb5 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -66,121 +66,6 @@ enum stack_protector_guard {
SSP_TLS, /* per-thread canary in TLS block */
SSP_GLOBAL /* global canary */
};
-
-#define MASK_ZICSR (1 << 0)
-#define MASK_ZIFENCEI (1 << 1)
-
-#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
-#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
-
-#define MASK_ZAWRS (1 << 0)
-#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
-
-#define MASK_ZBA (1 << 0)
-#define MASK_ZBB (1 << 1)
-#define MASK_ZBC (1 << 2)
-#define MASK_ZBS (1 << 3)
-
-#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
-#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
-#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
-#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
-
-#define MASK_ZFINX (1 << 0)
-#define MASK_ZDINX (1 << 1)
-#define MASK_ZHINX (1 << 2)
-#define MASK_ZHINXMIN (1 << 3)
-
-#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
-#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
-#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
-#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
-
-#define MASK_ZBKB (1 << 0)
-#define MASK_ZBKC (1 << 1)
-#define MASK_ZBKX (1 << 2)
-#define MASK_ZKNE (1 << 3)
-#define MASK_ZKND (1 << 4)
-#define MASK_ZKNH (1 << 5)
-#define MASK_ZKR (1 << 6)
-#define MASK_ZKSED (1 << 7)
-#define MASK_ZKSH (1 << 8)
-#define MASK_ZKT (1 << 9)
-
-#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
-#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
-#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
-#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
-#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
-#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
-#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
-#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
-#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
-#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
-
-#define MASK_VECTOR_ELEN_32 (1 << 0)
-#define MASK_VECTOR_ELEN_64 (1 << 1)
-#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
-#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
-
-#define TARGET_VECTOR_ELEN_32 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
-#define TARGET_VECTOR_ELEN_64 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
-#define TARGET_VECTOR_ELEN_FP_32 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
-#define TARGET_VECTOR_ELEN_FP_64 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
-
-#define MASK_ZVL32B (1 << 0)
-#define MASK_ZVL64B (1 << 1)
-#define MASK_ZVL128B (1 << 2)
-#define MASK_ZVL256B (1 << 3)
-#define MASK_ZVL512B (1 << 4)
-#define MASK_ZVL1024B (1 << 5)
-#define MASK_ZVL2048B (1 << 6)
-#define MASK_ZVL4096B (1 << 7)
-#define MASK_ZVL8192B (1 << 8)
-#define MASK_ZVL16384B (1 << 9)
-#define MASK_ZVL32768B (1 << 10)
-#define MASK_ZVL65536B (1 << 11)
-
-#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
-#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
-#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
-#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
-#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
-#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
-#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
-#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
-#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
-#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
-#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
-#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
-
-#define MASK_ZICBOZ (1 << 0)
-#define MASK_ZICBOM (1 << 1)
-#define MASK_ZICBOP (1 << 2)
-
-#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
-#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
-#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
-
-#define MASK_ZFHMIN (1 << 0)
-#define MASK_ZFH (1 << 1)
-
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
-
-#define MASK_ZMMUL (1 << 0)
-#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
-
-#define MASK_SVINVAL (1 << 0)
-#define MASK_SVNAPOT (1 << 1)
-
-#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
-#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
-
/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
popcount to caclulate the minimal VLEN. */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 7c3ca48d1cc..77f553356b1 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -203,36 +203,126 @@ long riscv_stack_protector_guard_offset = 0
TargetVariable
int riscv_zi_subext
+Mask(ZICSR) in TargetVariable(riscv_zi_subext)
+
+Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
+
TargetVariable
int riscv_za_subext
+Mask(ZAWRS) in TargetVariable(riscv_za_subext)
+
TargetVariable
int riscv_zb_subext
+Mask(ZBA) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBB) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBC) in TargetVariable(riscv_zb_subext)
+
+Mask(ZBS) in TargetVariable(riscv_zb_subext)
+
TargetVariable
int riscv_zinx_subext
+Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
+
+Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
+
TargetVariable
int riscv_zk_subext
+Mask(ZBKB) in TargetVariable(riscv_zk_subext)
+
+Mask(ZBKC) in TargetVariable(riscv_zk_subext)
+
+Mask(ZBKX) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKNE) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKND) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKNH) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKR) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKSED) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKSH) in TargetVariable(riscv_zk_subext)
+
+Mask(ZKT) in TargetVariable(riscv_zk_subext)
+
TargetVariable
int riscv_vector_elen_flags
+Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
+
TargetVariable
int riscv_zvl_flags
+Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
+
+Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
+
TargetVariable
int riscv_zicmo_subext
+Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
+
+Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
+
TargetVariable
int riscv_zf_subext
+Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
+
+Mask(ZFH) in TargetVariable(riscv_zf_subext)
+
TargetVariable
int riscv_zm_subext
+Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
+
TargetVariable
int riscv_sv_subext
+Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
+
+Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
+It looks like a good idea. However, there are still many modules that look very similar, can we further optimize these codes.BR,Jiawei
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
index 2aee0b9f1c3..9d6080d64a8 100644
--- a/gcc/opt-functions.awk
+++ b/gcc/opt-functions.awk
@@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
else
return "-1, -1"
}
+
+# Find the index of target variable from extra_target_vars
+function find_index(var, var_arry, n_var_arry)
+{
+ for (var_index = 0; var_index < n_var_arry; var_index++)
+ {
+ if (var_arry[var_index] == var)
+ break
+ }
+ return var_index
+}
\ No newline at end of file
diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index ce3617c8d4a..ebe48db968b 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -22,6 +22,7 @@ BEGIN {
n_opts = 0
n_langs = 0
n_target_save = 0
+ n_target_vars = 0
n_extra_vars = 0
n_extra_target_vars = 0
n_extra_masks = 0
@@ -121,7 +122,20 @@ BEGIN {
n_opts++;
}
else {
- extra_masks[n_extra_masks++] = name
+ if($0 ~ "in")
+ {
+ target_var = opt_args("TargetVariable", $1)
+ var_index = find_index(target_var, target_vars, n_target_vars)
+ if (var_index == n_target_vars)
+ {
+ target_vars[n_target_vars++] = target_var
+ }
+ other_masks[var_index][n_other_mask[var_index]++] = name
+ }
+ else
+ {
+ extra_masks[n_extra_masks++] = name
+ }
}
}
}
diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
index 8bba8ec4549..247a9fb8944 100644
--- a/gcc/opth-gen.awk
+++ b/gcc/opth-gen.awk
@@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
}
+for (i = 0; i < n_target_vars; i++)
+{
+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
+ continue
+ for (j = 0; j < n_other_mask[i]; j++)
+ {
+ print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
+ }
+ if (other_masknum[i][""] > 32)
+ print "#error too many target masks for" extra_target_vars[i]
+}
+
for (var in masknum) {
if (var != "" && host_wide_int[var] == "yes") {
print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
@@ -457,6 +469,16 @@ for (i = 0; i < n_extra_masks; i++) {
print "#define TARGET_" extra_masks[i] \
" ((target_flags & MASK_" extra_masks[i] ") != 0)"
}
+for (i = 0; i < n_target_vars; i++)
+{
+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
+ continue
+ for (j = 0; j < n_other_mask[i]; j++)
+ {
+ print "#define TARGET_" other_masks[i][j] \
+ " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
+ }
+}
print ""
for (i = 0; i < n_opts; i++) {
--
2.17.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Re: [PATCH] RISC-V: Optimize the MASK opt generation
2023-03-03 8:54 [PATCH] RISC-V: Optimize the MASK opt generation jiawei
@ 2023-03-03 9:12 ` Feng Wang
2023-03-06 1:06 ` Feng Wang
0 siblings, 1 reply; 3+ messages in thread
From: Feng Wang @ 2023-03-03 9:12 UTC (permalink / raw)
To: jiawei; +Cc: gcc-patches
On 2023-03-03 16:54 jiawei<jiawei@iscas.ac.cn> wrote:
>
>The Mask flag in the single TargetVariable is not enough due to more
>and more extensions were added.So I optimize the defination of Mask
>flag, please refer to the below case:
>There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B),
>but these MASK flags can't store into x_target_flags,because the total number
>of MASK flags exceed 32. In this patch we can write it like this in this scence.
>
>TargetVariable
>int riscv_zvl_flags
>
>Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
>
>The corresponding MASK and TARGET will be automatically generated.
>
>gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h Delete below definations
> (MASK_ZICSR): Delete;
> (MASK_ZIFENCEI): Delete;
> (TARGET_ZICSR): Delete;
> (TARGET_ZIFENCEI): Delete;
> (MASK_ZAWRS): Delete;
> (TARGET_ZAWRS): Delete;
> (MASK_ZBA): Delete;
> (MASK_ZBB): Delete;
> (MASK_ZBC): Delete;
> (MASK_ZBS): Delete;
> (TARGET_ZBA): Delete;
> (TARGET_ZBB): Delete;
> (TARGET_ZBC): Delete;
> (TARGET_ZBS): Delete;
> (MASK_ZFINX): Delete;
> (MASK_ZDINX): Delete;
> (MASK_ZHINX): Delete;
> (MASK_ZHINXMIN): Delete;
> (TARGET_ZFINX): Delete;
> (TARGET_ZDINX): Delete;
> (TARGET_ZHINX): Delete;
> (TARGET_ZHINXMIN): Delete;
> (MASK_ZBKB): Delete;
> (MASK_ZBKC): Delete;
> (MASK_ZBKX): Delete;
> (MASK_ZKNE): Delete;
> (MASK_ZKND): Delete;
> (MASK_ZKNH): Delete;
> (MASK_ZKR): Delete;
> (MASK_ZKSED): Delete;
> (MASK_ZKSH): Delete;
> (MASK_ZKT): Delete;
> (TARGET_ZBKB): Delete;
> (TARGET_ZBKC): Delete;
> (TARGET_ZBKX): Delete;
> (TARGET_ZKNE): Delete;
> (TARGET_ZKND): Delete;
> (TARGET_ZKNH): Delete;
> (TARGET_ZKR): Delete;
> (TARGET_ZKSED): Delete;
> (TARGET_ZKSH): Delete;
> (TARGET_ZKT): Delete;
> (MASK_VECTOR_ELEN_32): Delete;
> (MASK_VECTOR_ELEN_64): Delete;
> (MASK_VECTOR_ELEN_FP_32): Delete;
> (MASK_VECTOR_ELEN_FP_64): Delete;
> (TARGET_VECTOR_ELEN_32): Delete;
> (TARGET_VECTOR_ELEN_64): Delete;
> (TARGET_VECTOR_ELEN_FP_32): Delete;
> (TARGET_VECTOR_ELEN_FP_64): Delete;
> (MASK_ZVL32B): Delete;
> (MASK_ZVL64B): Delete;
> (MASK_ZVL128B): Delete;
> (MASK_ZVL256B): Delete;
> (MASK_ZVL512B): Delete;
> (MASK_ZVL1024B): Delete;
> (MASK_ZVL2048B): Delete;
> (MASK_ZVL4096B): Delete;
> (MASK_ZVL8192B): Delete;
> (MASK_ZVL16384B): Delete;
> (MASK_ZVL32768B): Delete;
> (MASK_ZVL65536B): Delete;
> (TARGET_ZVL32B): Delete;
> (TARGET_ZVL64B): Delete;
> (TARGET_ZVL128B): Delete;
> (TARGET_ZVL256B): Delete;
> (TARGET_ZVL512B): Delete;
> (TARGET_ZVL1024B): Delete;
> (TARGET_ZVL2048B): Delete;
> (TARGET_ZVL4096B): Delete;
> (TARGET_ZVL8192B): Delete;
> (TARGET_ZVL16384B): Delete;
> (TARGET_ZVL32768B): Delete;
> (TARGET_ZVL65536B): Delete;
> (MASK_ZICBOZ): Delete;
> (MASK_ZICBOM): Delete;
> (MASK_ZICBOP): Delete;
> (TARGET_ZICBOZ): Delete;
> (TARGET_ZICBOM): Delete;
> (TARGET_ZICBOP): Delete;
> (MASK_ZFHMIN): Delete;
> (MASK_ZFH): Delete;
> (TARGET_ZFHMIN): Delete;
> (TARGET_ZFH): Delete;
> (MASK_ZMMUL): Delete;
> (TARGET_ZMMUL): Delete;
> (MASK_SVINVAL): Delete;
> (MASK_SVNAPOT): Delete;
> (TARGET_SVINVAL): Delete;
> (TARGET_SVNAPOT): Delete;
> * config/riscv/riscv.opt: Add new Mask defination.
> * opt-functions.awk: Add new function to find the index
> of target variable from extra_target_vars.
> * opt-read.awk: Add new function to store the Mask flags.
> * opth-gen.awk: Add new function to output the defination of
> Mask Macro and Target Macro.
>---
> gcc/config/riscv/riscv-opts.h | 115 ----------------------------------
> gcc/config/riscv/riscv.opt | 90 ++++++++++++++++++++++++++
> gcc/opt-functions.awk | 11 ++++
> gcc/opt-read.awk | 16 ++++-
> gcc/opth-gen.awk | 22 +++++++
> 5 files changed, 138 insertions(+), 116 deletions(-)
>
>diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
>index 25fd85b09b1..7cf28838cb5 100644
>--- a/gcc/config/riscv/riscv-opts.h
>+++ b/gcc/config/riscv/riscv-opts.h
>@@ -66,121 +66,6 @@ enum stack_protector_guard {
> SSP_TLS, /* per-thread canary in TLS block */
> SSP_GLOBAL /* global canary */
> };
>-
>-#define MASK_ZICSR (1 << 0)
>-#define MASK_ZIFENCEI (1 << 1)
>-
>-#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
>-#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
>-
>-#define MASK_ZAWRS (1 << 0)
>-#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
>-
>-#define MASK_ZBA (1 << 0)
>-#define MASK_ZBB (1 << 1)
>-#define MASK_ZBC (1 << 2)
>-#define MASK_ZBS (1 << 3)
>-
>-#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
>-#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
>-#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
>-#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
>-
>-#define MASK_ZFINX (1 << 0)
>-#define MASK_ZDINX (1 << 1)
>-#define MASK_ZHINX (1 << 2)
>-#define MASK_ZHINXMIN (1 << 3)
>-
>-#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
>-#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
>-#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
>-#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
>-
>-#define MASK_ZBKB (1 << 0)
>-#define MASK_ZBKC (1 << 1)
>-#define MASK_ZBKX (1 << 2)
>-#define MASK_ZKNE (1 << 3)
>-#define MASK_ZKND (1 << 4)
>-#define MASK_ZKNH (1 << 5)
>-#define MASK_ZKR (1 << 6)
>-#define MASK_ZKSED (1 << 7)
>-#define MASK_ZKSH (1 << 8)
>-#define MASK_ZKT (1 << 9)
>-
>-#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
>-#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
>-#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
>-#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
>-#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
>-#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
>-#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
>-#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
>-#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
>-#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
>-
>-#define MASK_VECTOR_ELEN_32 (1 << 0)
>-#define MASK_VECTOR_ELEN_64 (1 << 1)
>-#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
>-#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
>-
>-#define TARGET_VECTOR_ELEN_32 \
>- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
>-#define TARGET_VECTOR_ELEN_64 \
>- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
>-#define TARGET_VECTOR_ELEN_FP_32 \
>- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
>-#define TARGET_VECTOR_ELEN_FP_64 \
>- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
>-
>-#define MASK_ZVL32B (1 << 0)
>-#define MASK_ZVL64B (1 << 1)
>-#define MASK_ZVL128B (1 << 2)
>-#define MASK_ZVL256B (1 << 3)
>-#define MASK_ZVL512B (1 << 4)
>-#define MASK_ZVL1024B (1 << 5)
>-#define MASK_ZVL2048B (1 << 6)
>-#define MASK_ZVL4096B (1 << 7)
>-#define MASK_ZVL8192B (1 << 8)
>-#define MASK_ZVL16384B (1 << 9)
>-#define MASK_ZVL32768B (1 << 10)
>-#define MASK_ZVL65536B (1 << 11)
>-
>-#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
>-#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
>-#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
>-#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
>-#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
>-#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
>-#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
>-#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
>-#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
>-#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
>-#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
>-#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
>-
>-#define MASK_ZICBOZ (1 << 0)
>-#define MASK_ZICBOM (1 << 1)
>-#define MASK_ZICBOP (1 << 2)
>-
>-#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
>-#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
>-#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
>-
>-#define MASK_ZFHMIN (1 << 0)
>-#define MASK_ZFH (1 << 1)
>-
>-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
>-#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
>-
>-#define MASK_ZMMUL (1 << 0)
>-#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
>-
>-#define MASK_SVINVAL (1 << 0)
>-#define MASK_SVNAPOT (1 << 1)
>-
>-#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
>-#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
>-
> /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
> set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
> popcount to caclulate the minimal VLEN. */
>diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>index 7c3ca48d1cc..77f553356b1 100644
>--- a/gcc/config/riscv/riscv.opt
>+++ b/gcc/config/riscv/riscv.opt
>@@ -203,36 +203,126 @@ long riscv_stack_protector_guard_offset = 0
> TargetVariable
> int riscv_zi_subext
>
>+Mask(ZICSR) in TargetVariable(riscv_zi_subext)
>+
>+Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
>+
> TargetVariable
> int riscv_za_subext
>
>+Mask(ZAWRS) in TargetVariable(riscv_za_subext)
>+
> TargetVariable
> int riscv_zb_subext
>
>+Mask(ZBA) in TargetVariable(riscv_zb_subext)
>+
>+Mask(ZBB) in TargetVariable(riscv_zb_subext)
>+
>+Mask(ZBC) in TargetVariable(riscv_zb_subext)
>+
>+Mask(ZBS) in TargetVariable(riscv_zb_subext)
>+
> TargetVariable
> int riscv_zinx_subext
>
>+Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
>+
>+Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
>+
>+Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
>+
>+Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
>+
> TargetVariable
> int riscv_zk_subext
>
>+Mask(ZBKB) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZBKC) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZBKX) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZKNE) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZKND) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZKNH) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZKR) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZKSED) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZKSH) in TargetVariable(riscv_zk_subext)
>+
>+Mask(ZKT) in TargetVariable(riscv_zk_subext)
>+
> TargetVariable
> int riscv_vector_elen_flags
>
>+Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
>+
>+Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
>+
>+Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
>+
>+Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
>+
> TargetVariable
> int riscv_zvl_flags
>
>+Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
>+
>+Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
>+
> TargetVariable
> int riscv_zicmo_subext
>
>+Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
>+
>+Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
>+
>+Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
>+
> TargetVariable
> int riscv_zf_subext
>
>+Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
>+
>+Mask(ZFH) in TargetVariable(riscv_zf_subext)
>+
> TargetVariable
> int riscv_zm_subext
>
>+Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
>+
> TargetVariable
> int riscv_sv_subext
>
>+Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
>+
>+Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
>+It looks like a good idea. However, there are still many modules that look very similar, can we further optimize these codes.BR,Jiawei
>
> Enum
> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
> Supported ISA specs (for use with the -misa-spec= option):
>diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
>index 2aee0b9f1c3..9d6080d64a8 100644
>--- a/gcc/opt-functions.awk
>+++ b/gcc/opt-functions.awk
>@@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
> else
> return "-1, -1"
> }
>+
>+# Find the index of target variable from extra_target_vars
>+function find_index(var, var_arry, n_var_arry)
>+{
>+ for (var_index = 0; var_index < n_var_arry; var_index++)
>+ {
>+ if (var_arry[var_index] == var)
>+ break
>+ }
>+ return var_index
>+}
>\ No newline at end of file
>diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>index ce3617c8d4a..ebe48db968b 100644
>--- a/gcc/opt-read.awk
>+++ b/gcc/opt-read.awk
>@@ -22,6 +22,7 @@ BEGIN {
> n_opts = 0
> n_langs = 0
> n_target_save = 0
>+ n_target_vars = 0
> n_extra_vars = 0
> n_extra_target_vars = 0
> n_extra_masks = 0
>@@ -121,7 +122,20 @@ BEGIN {
> n_opts++;
> }
> else {
>- extra_masks[n_extra_masks++] = name
>+ if($0 ~ "in")
>+ {
>+ target_var = opt_args("TargetVariable", $1)
>+ var_index = find_index(target_var, target_vars, n_target_vars)
>+ if (var_index == n_target_vars)
>+ {
>+ target_vars[n_target_vars++] = target_var
>+ }
>+ other_masks[var_index][n_other_mask[var_index]++] = name
>+ }
>+ else
>+ {
>+ extra_masks[n_extra_masks++] = name
>+ }
> }
> }
> }
>diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
>index 8bba8ec4549..247a9fb8944 100644
>--- a/gcc/opth-gen.awk
>+++ b/gcc/opth-gen.awk
>@@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
> print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
> }
>
>+for (i = 0; i < n_target_vars; i++)
>+{
>+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
>+ continue
>+ for (j = 0; j < n_other_mask[i]; j++)
>+ {
>+ print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
>+ }
>+ if (other_masknum[i][""] > 32)
>+ print "#error too many target masks for" extra_target_vars[i]
>+}
>+
> for (var in masknum) {
> if (var != "" && host_wide_int[var] == "yes") {
> print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
>@@ -457,6 +469,16 @@ for (i = 0; i < n_extra_masks; i++) {
> print "#define TARGET_" extra_masks[i] \
> " ((target_flags & MASK_" extra_masks[i] ") != 0)"
> }
>+for (i = 0; i < n_target_vars; i++)
>+{
>+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
>+ continue
>+ for (j = 0; j < n_other_mask[i]; j++)
>+ {
>+ print "#define TARGET_" other_masks[i][j] \
>+ " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
>+ }
>+}
> print ""
>
> for (i = 0; i < n_opts; i++) {
>--
>2.17.1
Hi Jiawei,
Thanks for your replay, I will try to optimize the generation code to eliminate the redundant codes.
Wang Feng
Best regards
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Re: [PATCH] RISC-V: Optimize the MASK opt generation
2023-03-03 9:12 ` Feng Wang
@ 2023-03-06 1:06 ` Feng Wang
0 siblings, 0 replies; 3+ messages in thread
From: Feng Wang @ 2023-03-06 1:06 UTC (permalink / raw)
To: jiawei; +Cc: gcc-patches
On 2023-03-03 17:12 Feng Wang<wangfeng@eswincomputing.com> wrote:
>
>On 2023-03-03 16:54 jiawei<jiawei@iscas.ac.cn> wrote:
>>
>>The Mask flag in the single TargetVariable is not enough due to more
>>and more extensions were added.So I optimize the defination of Mask
>>flag, please refer to the below case:
>>There are some new MASK flags for 'v' extension(ZVL32B,ZVL64B,...,ZVL65536B),
>>but these MASK flags can't store into x_target_flags,because the total number
>>of MASK flags exceed 32. In this patch we can write it like this in this scence.
>>
>>TargetVariable
>>int riscv_zvl_flags
>>
>>Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
>>
>>The corresponding MASK and TARGET will be automatically generated.
>>
>>gcc/ChangeLog:
>>
>> * config/riscv/riscv-opts.h Delete below definations
>> (MASK_ZICSR): Delete;
>> (MASK_ZIFENCEI): Delete;
>> (TARGET_ZICSR): Delete;
>> (TARGET_ZIFENCEI): Delete;
>> (MASK_ZAWRS): Delete;
>> (TARGET_ZAWRS): Delete;
>> (MASK_ZBA): Delete;
>> (MASK_ZBB): Delete;
>> (MASK_ZBC): Delete;
>> (MASK_ZBS): Delete;
>> (TARGET_ZBA): Delete;
>> (TARGET_ZBB): Delete;
>> (TARGET_ZBC): Delete;
>> (TARGET_ZBS): Delete;
>> (MASK_ZFINX): Delete;
>> (MASK_ZDINX): Delete;
>> (MASK_ZHINX): Delete;
>> (MASK_ZHINXMIN): Delete;
>> (TARGET_ZFINX): Delete;
>> (TARGET_ZDINX): Delete;
>> (TARGET_ZHINX): Delete;
>> (TARGET_ZHINXMIN): Delete;
>> (MASK_ZBKB): Delete;
>> (MASK_ZBKC): Delete;
>> (MASK_ZBKX): Delete;
>> (MASK_ZKNE): Delete;
>> (MASK_ZKND): Delete;
>> (MASK_ZKNH): Delete;
>> (MASK_ZKR): Delete;
>> (MASK_ZKSED): Delete;
>> (MASK_ZKSH): Delete;
>> (MASK_ZKT): Delete;
>> (TARGET_ZBKB): Delete;
>> (TARGET_ZBKC): Delete;
>> (TARGET_ZBKX): Delete;
>> (TARGET_ZKNE): Delete;
>> (TARGET_ZKND): Delete;
>> (TARGET_ZKNH): Delete;
>> (TARGET_ZKR): Delete;
>> (TARGET_ZKSED): Delete;
>> (TARGET_ZKSH): Delete;
>> (TARGET_ZKT): Delete;
>> (MASK_VECTOR_ELEN_32): Delete;
>> (MASK_VECTOR_ELEN_64): Delete;
>> (MASK_VECTOR_ELEN_FP_32): Delete;
>> (MASK_VECTOR_ELEN_FP_64): Delete;
>> (TARGET_VECTOR_ELEN_32): Delete;
>> (TARGET_VECTOR_ELEN_64): Delete;
>> (TARGET_VECTOR_ELEN_FP_32): Delete;
>> (TARGET_VECTOR_ELEN_FP_64): Delete;
>> (MASK_ZVL32B): Delete;
>> (MASK_ZVL64B): Delete;
>> (MASK_ZVL128B): Delete;
>> (MASK_ZVL256B): Delete;
>> (MASK_ZVL512B): Delete;
>> (MASK_ZVL1024B): Delete;
>> (MASK_ZVL2048B): Delete;
>> (MASK_ZVL4096B): Delete;
>> (MASK_ZVL8192B): Delete;
>> (MASK_ZVL16384B): Delete;
>> (MASK_ZVL32768B): Delete;
>> (MASK_ZVL65536B): Delete;
>> (TARGET_ZVL32B): Delete;
>> (TARGET_ZVL64B): Delete;
>> (TARGET_ZVL128B): Delete;
>> (TARGET_ZVL256B): Delete;
>> (TARGET_ZVL512B): Delete;
>> (TARGET_ZVL1024B): Delete;
>> (TARGET_ZVL2048B): Delete;
>> (TARGET_ZVL4096B): Delete;
>> (TARGET_ZVL8192B): Delete;
>> (TARGET_ZVL16384B): Delete;
>> (TARGET_ZVL32768B): Delete;
>> (TARGET_ZVL65536B): Delete;
>> (MASK_ZICBOZ): Delete;
>> (MASK_ZICBOM): Delete;
>> (MASK_ZICBOP): Delete;
>> (TARGET_ZICBOZ): Delete;
>> (TARGET_ZICBOM): Delete;
>> (TARGET_ZICBOP): Delete;
>> (MASK_ZFHMIN): Delete;
>> (MASK_ZFH): Delete;
>> (TARGET_ZFHMIN): Delete;
>> (TARGET_ZFH): Delete;
>> (MASK_ZMMUL): Delete;
>> (TARGET_ZMMUL): Delete;
>> (MASK_SVINVAL): Delete;
>> (MASK_SVNAPOT): Delete;
>> (TARGET_SVINVAL): Delete;
>> (TARGET_SVNAPOT): Delete;
>> * config/riscv/riscv.opt: Add new Mask defination.
>> * opt-functions.awk: Add new function to find the index
>> of target variable from extra_target_vars.
>> * opt-read.awk: Add new function to store the Mask flags.
>> * opth-gen.awk: Add new function to output the defination of
>> Mask Macro and Target Macro.
>>---
>> gcc/config/riscv/riscv-opts.h | 115 ----------------------------------
>> gcc/config/riscv/riscv.opt | 90 ++++++++++++++++++++++++++
>> gcc/opt-functions.awk | 11 ++++
>> gcc/opt-read.awk | 16 ++++-
>> gcc/opth-gen.awk | 22 +++++++
>> 5 files changed, 138 insertions(+), 116 deletions(-)
>>
>>diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
>>index 25fd85b09b1..7cf28838cb5 100644
>>--- a/gcc/config/riscv/riscv-opts.h
>>+++ b/gcc/config/riscv/riscv-opts.h
>>@@ -66,121 +66,6 @@ enum stack_protector_guard {
>> SSP_TLS, /* per-thread canary in TLS block */
>> SSP_GLOBAL /* global canary */
>> };
>>-
>>-#define MASK_ZICSR (1 << 0)
>>-#define MASK_ZIFENCEI (1 << 1)
>>-
>>-#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
>>-#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
>>-
>>-#define MASK_ZAWRS (1 << 0)
>>-#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
>>-
>>-#define MASK_ZBA (1 << 0)
>>-#define MASK_ZBB (1 << 1)
>>-#define MASK_ZBC (1 << 2)
>>-#define MASK_ZBS (1 << 3)
>>-
>>-#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
>>-#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
>>-#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
>>-#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
>>-
>>-#define MASK_ZFINX (1 << 0)
>>-#define MASK_ZDINX (1 << 1)
>>-#define MASK_ZHINX (1 << 2)
>>-#define MASK_ZHINXMIN (1 << 3)
>>-
>>-#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
>>-#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
>>-#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
>>-#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
>>-
>>-#define MASK_ZBKB (1 << 0)
>>-#define MASK_ZBKC (1 << 1)
>>-#define MASK_ZBKX (1 << 2)
>>-#define MASK_ZKNE (1 << 3)
>>-#define MASK_ZKND (1 << 4)
>>-#define MASK_ZKNH (1 << 5)
>>-#define MASK_ZKR (1 << 6)
>>-#define MASK_ZKSED (1 << 7)
>>-#define MASK_ZKSH (1 << 8)
>>-#define MASK_ZKT (1 << 9)
>>-
>>-#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
>>-#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
>>-#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
>>-#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
>>-#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
>>-#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
>>-#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
>>-#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
>>-#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
>>-#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
>>-
>>-#define MASK_VECTOR_ELEN_32 (1 << 0)
>>-#define MASK_VECTOR_ELEN_64 (1 << 1)
>>-#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
>>-#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
>>-
>>-#define TARGET_VECTOR_ELEN_32 \
>>- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
>>-#define TARGET_VECTOR_ELEN_64 \
>>- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
>>-#define TARGET_VECTOR_ELEN_FP_32 \
>>- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
>>-#define TARGET_VECTOR_ELEN_FP_64 \
>>- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
>>-
>>-#define MASK_ZVL32B (1 << 0)
>>-#define MASK_ZVL64B (1 << 1)
>>-#define MASK_ZVL128B (1 << 2)
>>-#define MASK_ZVL256B (1 << 3)
>>-#define MASK_ZVL512B (1 << 4)
>>-#define MASK_ZVL1024B (1 << 5)
>>-#define MASK_ZVL2048B (1 << 6)
>>-#define MASK_ZVL4096B (1 << 7)
>>-#define MASK_ZVL8192B (1 << 8)
>>-#define MASK_ZVL16384B (1 << 9)
>>-#define MASK_ZVL32768B (1 << 10)
>>-#define MASK_ZVL65536B (1 << 11)
>>-
>>-#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
>>-#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
>>-#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
>>-#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
>>-#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
>>-#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
>>-#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
>>-#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
>>-#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
>>-#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
>>-#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
>>-#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
>>-
>>-#define MASK_ZICBOZ (1 << 0)
>>-#define MASK_ZICBOM (1 << 1)
>>-#define MASK_ZICBOP (1 << 2)
>>-
>>-#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
>>-#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
>>-#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
>>-
>>-#define MASK_ZFHMIN (1 << 0)
>>-#define MASK_ZFH (1 << 1)
>>-
>>-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
>>-#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
>>-
>>-#define MASK_ZMMUL (1 << 0)
>>-#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
>>-
>>-#define MASK_SVINVAL (1 << 0)
>>-#define MASK_SVNAPOT (1 << 1)
>>-
>>-#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
>>-#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
>>-
>> /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
>> set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
>> popcount to caclulate the minimal VLEN. */
>>diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
>>index 7c3ca48d1cc..77f553356b1 100644
>>--- a/gcc/config/riscv/riscv.opt
>>+++ b/gcc/config/riscv/riscv.opt
>>@@ -203,36 +203,126 @@ long riscv_stack_protector_guard_offset = 0
>> TargetVariable
>> int riscv_zi_subext
>>
>>+Mask(ZICSR) in TargetVariable(riscv_zi_subext)
>>+
>>+Mask(ZIFENCEI) in TargetVariable(riscv_zi_subext)
>>+
>> TargetVariable
>> int riscv_za_subext
>>
>>+Mask(ZAWRS) in TargetVariable(riscv_za_subext)
>>+
>> TargetVariable
>> int riscv_zb_subext
>>
>>+Mask(ZBA) in TargetVariable(riscv_zb_subext)
>>+
>>+Mask(ZBB) in TargetVariable(riscv_zb_subext)
>>+
>>+Mask(ZBC) in TargetVariable(riscv_zb_subext)
>>+
>>+Mask(ZBS) in TargetVariable(riscv_zb_subext)
>>+
>> TargetVariable
>> int riscv_zinx_subext
>>
>>+Mask(ZFINX) in TargetVariable(riscv_zinx_subext)
>>+
>>+Mask(ZDINX) in TargetVariable(riscv_zinx_subext)
>>+
>>+Mask(ZHINX) in TargetVariable(riscv_zinx_subext)
>>+
>>+Mask(ZHINXMIN) in TargetVariable(riscv_zinx_subext)
>>+
>> TargetVariable
>> int riscv_zk_subext
>>
>>+Mask(ZBKB) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZBKC) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZBKX) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZKNE) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZKND) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZKNH) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZKR) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZKSED) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZKSH) in TargetVariable(riscv_zk_subext)
>>+
>>+Mask(ZKT) in TargetVariable(riscv_zk_subext)
>>+
>> TargetVariable
>> int riscv_vector_elen_flags
>>
>>+Mask(VECTOR_ELEN_32) in TargetVariable(riscv_vector_elen_flags)
>>+
>>+Mask(VECTOR_ELEN_64) in TargetVariable(riscv_vector_elen_flags)
>>+
>>+Mask(VECTOR_ELEN_FP_32) in TargetVariable(riscv_vector_elen_flags)
>>+
>>+Mask(VECTOR_ELEN_FP_64) in TargetVariable(riscv_vector_elen_flags)
>>+
>> TargetVariable
>> int riscv_zvl_flags
>>
>>+Mask(ZVL32B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL64B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL128B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL256B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL512B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL1024B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL2048B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL4096B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL8192B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL16384B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL32768B) in TargetVariable(riscv_zvl_flags)
>>+
>>+Mask(ZVL65536B) in TargetVariable(riscv_zvl_flags)
>>+
>> TargetVariable
>> int riscv_zicmo_subext
>>
>>+Mask(ZICBOZ) in TargetVariable(riscv_zicmo_subext)
>>+
>>+Mask(ZICBOM) in TargetVariable(riscv_zicmo_subext)
>>+
>>+Mask(ZICBOP) in TargetVariable(riscv_zicmo_subext)
>>+
>> TargetVariable
>> int riscv_zf_subext
>>
>>+Mask(ZFHMIN) in TargetVariable(riscv_zf_subext)
>>+
>>+Mask(ZFH) in TargetVariable(riscv_zf_subext)
>>+
>> TargetVariable
>> int riscv_zm_subext
>>
>>+Mask(ZMMUL) in TargetVariable(riscv_zm_subext)
>>+
>> TargetVariable
>> int riscv_sv_subext
>>
>>+Mask(SVINVAL) in TargetVariable(riscv_sv_subext)
>>+
>>+Mask(SVNAPOT) in TargetVariable(riscv_sv_subext)
>>+It looks like a good idea. However, there are still many modules that look very similar, can we further optimize these codes.BR,Jiawei
>>
>> Enum
>> Name(isa_spec_class) Type(enum riscv_isa_spec_class)
>> Supported ISA specs (for use with the -misa-spec= option):
>>diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
>>index 2aee0b9f1c3..9d6080d64a8 100644
>>--- a/gcc/opt-functions.awk
>>+++ b/gcc/opt-functions.awk
>>@@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option, uinteger_used)
>> else
>> return "-1, -1"
>> }
>>+
>>+# Find the index of target variable from extra_target_vars
>>+function find_index(var, var_arry, n_var_arry)
>>+{
>>+ for (var_index = 0; var_index < n_var_arry; var_index++)
>>+ {
>>+ if (var_arry[var_index] == var)
>>+ break
>>+ }
>>+ return var_index
>>+}
>>\ No newline at end of file
>>diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
>>index ce3617c8d4a..ebe48db968b 100644
>>--- a/gcc/opt-read.awk
>>+++ b/gcc/opt-read.awk
>>@@ -22,6 +22,7 @@ BEGIN {
>> n_opts = 0
>> n_langs = 0
>> n_target_save = 0
>>+ n_target_vars = 0
>> n_extra_vars = 0
>> n_extra_target_vars = 0
>> n_extra_masks = 0
>>@@ -121,7 +122,20 @@ BEGIN {
>> n_opts++;
>> }
>> else {
>>- extra_masks[n_extra_masks++] = name
>>+ if($0 ~ "in")
>>+ {
>>+ target_var = opt_args("TargetVariable", $1)
>>+ var_index = find_index(target_var, target_vars, n_target_vars)
>>+ if (var_index == n_target_vars)
>>+ {
>>+ target_vars[n_target_vars++] = target_var
>>+ }
>>+ other_masks[var_index][n_other_mask[var_index]++] = name
>>+ }
>>+ else
>>+ {
>>+ extra_masks[n_extra_masks++] = name
>>+ }
>> }
>> }
>> }
>>diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
>>index 8bba8ec4549..247a9fb8944 100644
>>--- a/gcc/opth-gen.awk
>>+++ b/gcc/opth-gen.awk
>>@@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
>> print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++ ")"
>> }
>>
>>+for (i = 0; i < n_target_vars; i++)
>>+{
>>+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
>>+ continue
>>+ for (j = 0; j < n_other_mask[i]; j++)
>>+ {
>>+ print "#define MASK_" other_masks[i][j] " (1U << " other_masknum[i][""]++ ")"
>>+ }
>>+ if (other_masknum[i][""] > 32)
>>+ print "#error too many target masks for" extra_target_vars[i]
>>+}
>>+
>> for (var in masknum) {
>> if (var != "" && host_wide_int[var] == "yes") {
>> print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] " > HOST_BITS_PER_WIDE_INT"
>>@@ -457,6 +469,16 @@ for (i = 0; i < n_extra_masks; i++) {
>> print "#define TARGET_" extra_masks[i] \
>> " ((target_flags & MASK_" extra_masks[i] ") != 0)"
>> }
>>+for (i = 0; i < n_target_vars; i++)
>>+{
>>+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars) == n_extra_target_vars)
>>+ continue
>>+ for (j = 0; j < n_other_mask[i]; j++)
>>+ {
>>+ print "#define TARGET_" other_masks[i][j] \
>>+ " ((" target_vars[i] " & MASK_" other_masks[i][j] ") != 0)"
>>+ }
>>+}
>> print ""
>>
>> for (i = 0; i < n_opts; i++) {
>>--
>>2.17.1
>
>Hi Jiawei,
>
>Thanks for your replay, I will try to optimize the generation code to eliminate the redundant codes.
>
>Wang Feng
>Best regards
>
Hi Jiawei,
I studied the code of generation again and I think it is better to be independent this part in order not to
affect the processing of other architectures. If you have any suggestions, you can discuss with me. Thank you.
Wang Feng
Best regards
^ permalink raw reply [flat|nested] 3+ messages in thread
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2023-03-03 8:54 [PATCH] RISC-V: Optimize the MASK opt generation jiawei
2023-03-03 9:12 ` Feng Wang
2023-03-06 1:06 ` Feng Wang
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