* [PATCH 13-backport 0/3] RISC-V Testsuite Fixes
@ 2023-04-17 18:20 Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 1/3] RISC-V: Clean up the pr106602.c testcase Palmer Dabbelt
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2023-04-17 18:20 UTC (permalink / raw)
To: gcc-patches
These had been approved for trunk, but I hadn't gotten around to
committing them before the branch. They're on trunk now. They're all
pretty trivial test suite fixes.
OK for 13?
(Also I'm not sure if we're supposed to be using `git cherry-pick -x`)
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 13-backport 1/3] RISC-V: Clean up the pr106602.c testcase
2023-04-17 18:20 [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Palmer Dabbelt
@ 2023-04-17 18:20 ` Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 2/3] RISC-V: Set the ABI for the RVV tests Palmer Dabbelt
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2023-04-17 18:20 UTC (permalink / raw)
To: gcc-patches; +Cc: Palmer Dabbelt
The test case that was added is rv64i-specific, as there's better ways
to generate this code on rv32i (where the long/int cast is a NOP) and on
rv64i_zba (where we have word shifts). This renames the original test
case and adds two more for those targets.
gcc/testsuite/ChangeLog:
PR target/106602
* gcc.target/riscv/pr106602.c: Moved to...
* gcc.target/riscv/pr106602-rv64i.c: ...here.
* gcc.target/riscv/pr106602-rv32i.c: New test.
* gcc.target/riscv/pr106602-rv64i_zba.c: New test.
(cherry picked from commit 8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368)
---
gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c | 14 ++++++++++++++
.../riscv/{pr106602.c => pr106602-rv64i.c} | 2 +-
.../gcc.target/riscv/pr106602-rv64i_zba.c | 15 +++++++++++++++
3 files changed, 30 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c
rename gcc/testsuite/gcc.target/riscv/{pr106602.c => pr106602-rv64i.c} (88%)
create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c
new file mode 100644
index 00000000000..05b54db7486
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv32i.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2 -march=rv32i -mabi=ilp32" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+ return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli\t" 1 } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
similarity index 88%
rename from gcc/testsuite/gcc.target/riscv/pr106602.c
rename to gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
index 825b1a143b5..ef0719f4a9a 100644
--- a/gcc/testsuite/gcc.target/riscv/pr106602.c
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { riscv64*-*-* } } } */
-/* { dg-options "-O2" } */
+/* { dg-options "-O2 -march=rv64i -mabi=lp64" } */
unsigned long
foo2 (unsigned long a)
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c
new file mode 100644
index 00000000000..23b9f1e60f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602-rv64i_zba.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2 -march=rv64i_zba -mabi=lp64" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+ return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli.uw\t" 1 } } */
+/* { dg-final { scan-assembler-not "slli\t" } } */
+/* { dg-final { scan-assembler-not "srli\t" } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */
--
2.39.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 13-backport 2/3] RISC-V: Set the ABI for the RVV tests
2023-04-17 18:20 [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 1/3] RISC-V: Clean up the pr106602.c testcase Palmer Dabbelt
@ 2023-04-17 18:20 ` Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 3/3] RISC-V: Force ilp32d for the T-Head FMV test Palmer Dabbelt
2023-04-18 6:10 ` [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Richard Biener
3 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2023-04-17 18:20 UTC (permalink / raw)
To: gcc-patches; +Cc: Palmer Dabbelt
The RVV test harness currently sets the ISA according to the target
tuple, but doesn't also set the ABI. This just sets the ABI to match
the ISA, though we should really also be respecting the user's specific
ISA to test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp (gcc_mabi): New variable.
(cherry picked from commit e6b050da8a4513ab37fd3699c7a963421fbe4d81)
---
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index 7a9a2b6ac48..4b5509db385 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -31,15 +31,17 @@ if ![info exists DEFAULT_CFLAGS] then {
}
set gcc_march "rv64gcv_zfh"
+set gcc_mabi "lp64d"
if [istarget riscv32-*-*] then {
set gcc_march "rv32gcv_zfh"
+ set gcc_mabi "ilp32d"
}
# Initialize `dg'.
dg-init
# Main loop.
-set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -O3"
+set CFLAGS "$DEFAULT_CFLAGS -march=$gcc_march -mabi=$gcc_mabi -O3"
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/base/*.\[cS\]]] \
"" $CFLAGS
gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/vsetvl/*.\[cS\]]] \
--
2.39.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 13-backport 3/3] RISC-V: Force ilp32d for the T-Head FMV test
2023-04-17 18:20 [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 1/3] RISC-V: Clean up the pr106602.c testcase Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 2/3] RISC-V: Set the ABI for the RVV tests Palmer Dabbelt
@ 2023-04-17 18:20 ` Palmer Dabbelt
2023-04-18 6:10 ` [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Richard Biener
3 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2023-04-17 18:20 UTC (permalink / raw)
To: gcc-patches; +Cc: Palmer Dabbelt
These functions are NOPs on the soft-float ABIs. Since we're already
forcing the ISA, let's just force the ABI too.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadfmv-fmv.c: Force the ilp32d ABI.
(cherry picked from commit c16848ed8f30be952ac0167fd464ae794fa5ac67)
---
gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
index 10d035e9e1d..1036044291e 100644
--- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
+++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c
@@ -1,5 +1,5 @@
/* { dg-do compile { target { rv32 } } } */
-/* { dg-options "-march=rv32gc_xtheadfmv" } */
+/* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */
/* { dg-skip-if "" { *-*-* } { "-O0" } } */
double
--
2.39.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 13-backport 0/3] RISC-V Testsuite Fixes
2023-04-17 18:20 [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Palmer Dabbelt
` (2 preceding siblings ...)
2023-04-17 18:20 ` [PATCH 13-backport 3/3] RISC-V: Force ilp32d for the T-Head FMV test Palmer Dabbelt
@ 2023-04-18 6:10 ` Richard Biener
2023-04-19 2:41 ` Palmer Dabbelt
3 siblings, 1 reply; 6+ messages in thread
From: Richard Biener @ 2023-04-18 6:10 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: gcc-patches
On Mon, Apr 17, 2023 at 8:22 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> These had been approved for trunk, but I hadn't gotten around to
> committing them before the branch. They're on trunk now. They're all
> pretty trivial test suite fixes.
>
> OK for 13?
Yes
> (Also I'm not sure if we're supposed to be using `git cherry-pick -x`)
And yes.
Richard.
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 13-backport 0/3] RISC-V Testsuite Fixes
2023-04-18 6:10 ` [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Richard Biener
@ 2023-04-19 2:41 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2023-04-19 2:41 UTC (permalink / raw)
To: richard.guenther; +Cc: gcc-patches
On Mon, 17 Apr 2023 23:10:03 PDT (-0700), richard.guenther@gmail.com wrote:
> On Mon, Apr 17, 2023 at 8:22 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>>
>> These had been approved for trunk, but I hadn't gotten around to
>> committing them before the branch. They're on trunk now. They're all
>> pretty trivial test suite fixes.
>>
>> OK for 13?
>
> Yes
>
>> (Also I'm not sure if we're supposed to be using `git cherry-pick -x`)
>
> And yes.
Thanks. Committed.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-04-19 2:41 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-04-17 18:20 [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 1/3] RISC-V: Clean up the pr106602.c testcase Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 2/3] RISC-V: Set the ABI for the RVV tests Palmer Dabbelt
2023-04-17 18:20 ` [PATCH 13-backport 3/3] RISC-V: Force ilp32d for the T-Head FMV test Palmer Dabbelt
2023-04-18 6:10 ` [PATCH 13-backport 0/3] RISC-V Testsuite Fixes Richard Biener
2023-04-19 2:41 ` Palmer Dabbelt
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