[PATCH] RISC-V: Add basic vec_init support for RVV auto-vectorizaiton

[PATCH] RISC-V: Add basic vec_init support for RVV auto-vectorizaiton

[juzhe.zhong]

From: Juzhe-Zhong <juzhe.zhong@rivai.ai>

This is patching is adding basic vec_init support for RVV auto-vectorization.
Testing is on-going.

This patch makes vec_init support common init vector handling (using vslide1down to insert element)
which can handle any cases of initialization vec but it's not optimal for cases.

And support Case 1 optimizaiton:
https://godbolt.org/z/GzYsTEfqx

#include <stdint.h>

typedef int8_t vnx16qi __attribute__((vector_size (16)));

__attribute__((noipa))
void foo(int8_t a, int8_t b, int8_t c, int8_t *out)
{
  vnx16qi v = { a, b, a, b, a, b, a, b, a, b, a, b, a, b, a, b };
  *(vnx16qi*) out = v;
}

LLVM codegen:
foo:                                    # @foo
        lui     a3, 5
        addiw   a3, a3, 1365
        vsetivli        zero, 1, e16, mf4, ta, ma
        vmv.s.x v0, a3
        vsetivli        zero, 16, e8, m1, ta, ma
        vmv.v.x v8, a1
        vmerge.vxm      v8, v8, a0, v0
        vse8.v  v8, (a2)
        ret

This patch codegen:
foo:
        slli    a0,a0,8
        or      a0,a0,a1
        vsetvli a5,zero,e16,m1,ta,ma
        vmv.v.x v1,a0
        vs1r.v  v1,0(a2)
        ret

We support more optimizations cases in the future. But they are not included in this patch.

gcc/ChangeLog:

        * config/riscv/autovec.md (vec_init<mode><vel>): New pattern.
        * config/riscv/riscv-protos.h (expand_vec_init): New function.
        * config/riscv/riscv-v.cc (class rvv_builder): New class.
        (rvv_builder::can_duplicate_repeating_sequence_p): New function.
        (rvv_builder::get_merged_repeating_sequence): Ditto.
        (expand_vector_init_insert_elems): Ditto.
        (expand_vec_init): Ditto.
        * config/riscv/vector-iterators.md: New attribute.

---
 gcc/config/riscv/autovec.md          |  16 ++++
 gcc/config/riscv/riscv-protos.h      |   1 +
 gcc/config/riscv/riscv-v.cc          | 127 +++++++++++++++++++++++++++
 gcc/config/riscv/vector-iterators.md |   9 ++
 4 files changed, 153 insertions(+)

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 99dc4f046b0..fb57a52a4b6 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -82,3 +82,19 @@
     DONE;
   }
 )
+
+;; -------------------------------------------------------------------------
+;; ---- [INT,FP] Initialize from individual elements
+;; -------------------------------------------------------------------------
+;; This is the pattern initialize the vector
+;; -------------------------------------------------------------------------
+
+(define_expand "vec_init<mode><vel>"
+  [(match_operand:V 0 "register_operand")
+   (match_operand 1 "")]
+  "TARGET_VECTOR"
+  {
+    riscv_vector::expand_vec_init (operands[0], operands[1]);
+    DONE;
+  }
+)
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index e8a728ae226..7196e34e335 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -220,6 +220,7 @@ void expand_tuple_move (machine_mode, rtx *);
 machine_mode preferred_simd_mode (scalar_mode);
 opt_machine_mode get_mask_mode (machine_mode);
 void expand_vec_series (rtx, rtx, rtx);
+void expand_vec_init (rtx, rtx);
 }
 
 /* We classify builtin types into two classes:
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 0c3b1b4c40b..9ab6d7d5f41 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1091,4 +1091,131 @@ preferred_simd_mode (scalar_mode mode)
   return word_mode;
 }
 
+class rvv_builder : public rtx_vector_builder
+{
+public:
+  static const uint8_t MAX_DUP_SIZE = 64;
+
+  rvv_builder () : rtx_vector_builder () {}
+  rvv_builder (machine_mode mode, unsigned int npatterns,
+	       unsigned int nelts_per_pattern)
+    : rtx_vector_builder (mode, npatterns, nelts_per_pattern)
+  {
+    m_inner_mode = GET_MODE_INNER (mode);
+    m_inner_size = GET_MODE_BITSIZE (m_inner_mode).to_constant ();
+  }
+
+  bool can_duplicate_repeating_sequence_p ();
+  rtx get_merged_repeating_sequence ();
+
+  machine_mode new_mode () const { return m_new_mode; }
+
+private:
+  machine_mode m_inner_mode;
+  machine_mode m_new_mode;
+  scalar_int_mode m_new_inner_mode;
+  unsigned int m_inner_size;
+};
+
+/* Return true if the vector duplicated by a super element which is the fusion
+   of consecutive elements.
+
+     v = { a, b, a, b } super element = ab, v = { ab, ab }  */
+bool
+rvv_builder::can_duplicate_repeating_sequence_p ()
+{
+  poly_uint64 new_size = exact_div (full_nelts (), npatterns ());
+  unsigned int new_inner_size = m_inner_size * npatterns ();
+  if (!int_mode_for_size (new_inner_size, 0).exists (&m_new_inner_mode)
+      || GET_MODE_BITSIZE (m_new_inner_mode) > MAX_DUP_SIZE
+      || !get_vector_mode (m_new_inner_mode, new_size).exists (&m_new_mode))
+    return false;
+  return repeating_sequence_p (0, encoded_nelts (), npatterns ());
+}
+
+/* Merge the repeating sequence into a single element and return the RTX.  */
+rtx
+rvv_builder::get_merged_repeating_sequence ()
+{
+  scalar_int_mode mode = m_new_inner_mode;
+  if (GET_MODE_SIZE (m_new_inner_mode) < UNITS_PER_WORD)
+    mode = Pmode;
+  rtx target = gen_reg_rtx (mode);
+  emit_move_insn (gen_lowpart (m_inner_mode, target), elt (npatterns () - 1));
+  /* { a, b, a, b }: Generate duplicate element = a << bits | b.  */
+  for (unsigned int i = 0; i < npatterns () - 1; i++)
+    {
+      unsigned int loc = m_inner_size * (npatterns () - 1 - i);
+      rtx shift = GEN_INT (loc);
+      rtx tmp = expand_simple_binop (mode, ASHIFT, gen_lowpart (mode, elt (i)),
+				     shift, NULL_RTX, false, OPTAB_DIRECT);
+      rtx tmp2 = expand_simple_binop (mode, IOR, tmp, target, NULL_RTX, false,
+				      OPTAB_DIRECT);
+      emit_move_insn (target, tmp2);
+    }
+  if (GET_MODE_SIZE (m_new_inner_mode) < UNITS_PER_WORD)
+    return gen_lowpart (m_new_inner_mode, target);
+  return target;
+}
+
+/* Subroutine of riscv_vector_expand_vector_init.
+   Works as follows:
+   (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
+   (b) Skip leading elements from BUILDER, which are the same as
+       element NELTS_REQD - 1.
+   (c) Insert earlier elements in reverse order in TARGET using vslide1down.  */
+
+static void
+expand_vector_init_insert_elems (rtx target, const rvv_builder &builder,
+				 int nelts_reqd)
+{
+  machine_mode mode = GET_MODE (target);
+  scalar_mode elem_mode = GET_MODE_INNER (mode);
+  machine_mode mask_mode;
+  gcc_assert (get_mask_mode (mode).exists (&mask_mode));
+  rtx dup = expand_vector_broadcast (mode, builder.elt (0));
+  emit_move_insn (target, dup);
+  int ndups = builder.count_dups (0, nelts_reqd - 1, 1);
+  for (int i = ndups; i < nelts_reqd; i++)
+    {
+      unsigned int unspec
+	= FLOAT_MODE_P (mode) ? UNSPEC_VFSLIDE1DOWN : UNSPEC_VSLIDE1DOWN;
+      insn_code icode = code_for_pred_slide (unspec, mode);
+      rtx ops[3] = {target, target, builder.elt (i)};
+      emit_binop (icode, ops, mask_mode, elem_mode);
+    }
+}
+
+/* Initialize register TARGET from the elements in PARALLEL rtx VALS.  */
+
+void
+expand_vec_init (rtx target, rtx vals)
+{
+  machine_mode mode = GET_MODE (target);
+  int nelts = XVECLEN (vals, 0);
+
+  rvv_builder v (mode, nelts, 1);
+  for (int i = 0; i < nelts; i++)
+    v.quick_push (XVECEXP (vals, 0, i));
+  v.finalize ();
+
+  if (nelts > 3)
+    {
+      /* Case 1: Convert v = { a, b, a, b } into v = { ab, ab }.  */
+      if (v.can_duplicate_repeating_sequence_p ())
+	{
+	  rtx ele = v.get_merged_repeating_sequence ();
+	  rtx dup = expand_vector_broadcast (v.new_mode (), ele);
+	  emit_move_insn (target, gen_lowpart (mode, dup));
+	  return;
+	}
+      /* TODO: We will support more Initialization of vector in the future.  */
+    }
+
+  /* Handle common situation by vslide1down. This function can handle any
+     situation of vec_init<mode>. Only the cases that are not optimized above
+     will fall through here.  */
+  expand_vector_init_insert_elems (target, v, nelts);
+}
+
 } // namespace riscv_vector
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 29c9d77674b..19ea016cb6d 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -996,6 +996,15 @@
   (VNx1DF "DF") (VNx2DF "DF") (VNx4DF "DF") (VNx8DF "DF") (VNx16DF "DF")
 ])
 
+(define_mode_attr vel [
+  (VNx1QI "qi") (VNx2QI "qi") (VNx4QI "qi") (VNx8QI "qi") (VNx16QI "qi") (VNx32QI "qi") (VNx64QI "qi") (VNx128QI "qi")
+  (VNx1HI "hi") (VNx2HI "hi") (VNx4HI "hi") (VNx8HI "hi") (VNx16HI "hi") (VNx32HI "hi") (VNx64HI "hi")
+  (VNx1SI "si") (VNx2SI "si") (VNx4SI "si") (VNx8SI "si") (VNx16SI "si") (VNx32SI "si")
+  (VNx1DI "di") (VNx2DI "di") (VNx4DI "di") (VNx8DI "di") (VNx16DI "di")
+  (VNx1SF "sf") (VNx2SF "sf") (VNx4SF "sf") (VNx8SF "sf") (VNx16SF "sf") (VNx32SF "sf")
+  (VNx1DF "df") (VNx2DF "df") (VNx4DF "df") (VNx8DF "df") (VNx16DF "df")
+])
+
 (define_mode_attr VSUBEL [
   (VNx1HI "QI") (VNx2HI "QI") (VNx4HI "QI") (VNx8HI "QI") (VNx16HI "QI") (VNx32HI "QI") (VNx64HI "QI")
   (VNx1SI "HI") (VNx2SI "HI") (VNx4SI "HI") (VNx8SI "HI") (VNx16SI "HI") (VNx32SI "HI")
-- 
2.36.3