From: Christophe Lyon <christophe.lyon@arm.com>
To: <gcc-patches@gcc.gnu.org>, <kyrylo.tkachov@arm.com>,
<richard.earnshaw@arm.com>, <richard.sandiford@arm.com>
Cc: Christophe Lyon <christophe.lyon@arm.com>
Subject: [PATCH 10/26] arm: [MVE intrinsics] factorize vrbsrq
Date: Fri, 12 May 2023 11:38:39 +0200 [thread overview]
Message-ID: <20230512093855.79529-10-christophe.lyon@arm.com> (raw)
In-Reply-To: <20230512093855.79529-1-christophe.lyon@arm.com>
Factorize vrbsrq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (MVE_VBRSR_M_N_FP, MVE_VBRSR_N_FP): New.
(mve_insn): Add vbrsr.
* config/arm/mve.md (mve_vbrsrq_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_n_f<mode>): ... this.
(mve_vbrsrq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
(mve_vbrsrq_m_n_f<mode>): Rename into ...
(@mve_<mve_insn>q_m_n_f<mode>): ... this.
---
gcc/config/arm/iterators.md | 10 ++++++++++
gcc/config/arm/mve.md | 20 ++++++++++----------
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index d1d14488b56..dfc8d9cae72 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -610,6 +610,14 @@ (define_int_iterator MVE_FP_CREATE_ONLY [
VCREATEQ_F
])
+(define_int_iterator MVE_VBRSR_M_N_FP [
+ VBRSRQ_M_N_F
+ ])
+
+(define_int_iterator MVE_VBRSR_N_FP [
+ VBRSRQ_N_F
+ ])
+
;; MVE comparison iterators
(define_int_iterator MVE_CMP_M [
VCMPCSQ_M_U
@@ -900,6 +908,8 @@ (define_int_attr mve_insn [
(VBICQ_M_N_S "vbic") (VBICQ_M_N_U "vbic")
(VBICQ_M_S "vbic") (VBICQ_M_U "vbic") (VBICQ_M_F "vbic")
(VBICQ_N_S "vbic") (VBICQ_N_U "vbic")
+ (VBRSRQ_M_N_S "vbrsr") (VBRSRQ_M_N_U "vbrsr") (VBRSRQ_M_N_F "vbrsr")
+ (VBRSRQ_N_S "vbrsr") (VBRSRQ_N_U "vbrsr") (VBRSRQ_N_F "vbrsr")
(VCLSQ_M_S "vcls")
(VCLSQ_S "vcls")
(VCLZQ_M_S "vclz") (VCLZQ_M_U "vclz")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 7898361b859..beca74d4964 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -529,15 +529,15 @@ (define_insn "mve_vpnotv16bi"
;;
;; [vbrsrq_n_f])
;;
-(define_insn "mve_vbrsrq_n_f<mode>"
+(define_insn "@mve_<mve_insn>q_n_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w")
(match_operand:SI 2 "s_register_operand" "r")]
- VBRSRQ_N_F))
+ MVE_VBRSR_N_FP))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vbrsr.<V_sz_elem> %q0, %q1, %2"
+ "<mve_insn>.<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -826,7 +826,7 @@ (define_expand "mve_vbicq_s<mode>"
;;
;; [vbrsrq_n_u, vbrsrq_n_s])
;;
-(define_insn "mve_vbrsrq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
@@ -834,7 +834,7 @@ (define_insn "mve_vbrsrq_n_<supf><mode>"
VBRSRQ_N))
]
"TARGET_HAVE_MVE"
- "vbrsr.%#<V_sz_elem> %q0, %q1, %2"
+ "<mve_insn>.%#<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -2802,7 +2802,7 @@ (define_insn "@mve_<mve_insn>q_m_<supf><mode>"
;;
;; [vbrsrq_m_n_u, vbrsrq_m_n_s])
;;
-(define_insn "mve_vbrsrq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
@@ -2812,7 +2812,7 @@ (define_insn "mve_vbrsrq_m_n_<supf><mode>"
VBRSRQ_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
+ "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3257,17 +3257,17 @@ (define_insn "@mve_<mve_insn>q_m_f<mode>"
;;
;; [vbrsrq_m_n_f])
;;
-(define_insn "mve_vbrsrq_m_n_f<mode>"
+(define_insn "@mve_<mve_insn>q_m_n_f<mode>"
[
(set (match_operand:MVE_0 0 "s_register_operand" "=w")
(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0")
(match_operand:MVE_0 2 "s_register_operand" "w")
(match_operand:SI 3 "s_register_operand" "r")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VBRSRQ_M_N_F))
+ MVE_VBRSR_M_N_FP))
]
"TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT"
- "vpst\;vbrsrt.%#<V_sz_elem> %q0, %q2, %3"
+ "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
--
2.34.1
next prev parent reply other threads:[~2023-05-12 9:39 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-12 9:38 [PATCH 01/26] arm: [MVE intrinsics] add binary_widen_opt_n shape Christophe Lyon
2023-05-12 9:38 ` [PATCH 02/26] arm: [MVE intrinsics] factorize vqdmullbq vqdmulltq Christophe Lyon
2023-05-12 9:38 ` [PATCH 03/26] arm: [MVE intrinsics] rework " Christophe Lyon
2023-05-12 9:38 ` [PATCH 04/26] arm: [MVE intrinsics] factorize vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq vrmlsldavhaxq Christophe Lyon
2023-05-12 9:38 ` [PATCH 05/26] arm: [MVE intrinsics] rework " Christophe Lyon
2023-05-12 9:38 ` [PATCH 06/26] arm: [MVE intrinsics] add binary_lshift_unsigned shape Christophe Lyon
2023-05-12 9:38 ` [PATCH 07/26] arm: [MVE intrinsics] factorize vqshluq Christophe Lyon
2023-05-12 9:38 ` [PATCH 08/26] arm: [MVE intrinsics] rework vqshluq Christophe Lyon
2023-05-12 9:38 ` [PATCH 09/26] arm: [MVE intrinsics] add binary_imm32 shape Christophe Lyon
2023-05-12 9:38 ` Christophe Lyon [this message]
2023-05-12 9:38 ` [PATCH 11/26] arm: [MVE intrinsics] rework vbrsrq Christophe Lyon
2023-05-12 9:38 ` [PATCH 12/26] arm: [MVE intrinsics] add mvn shape Christophe Lyon
2023-05-12 9:38 ` [PATCH 13/26] arm: [MVE intrinsics] factorize vmvnq Christophe Lyon
2023-05-12 9:38 ` [PATCH 14/26] arm: [MVE intrinsics] rework vmvnq Christophe Lyon
2023-05-12 9:38 ` [PATCH 15/26] arm: [MVE intrinsics] add ternary_opt_n shape Christophe Lyon
2023-05-12 9:38 ` [PATCH 16/26] arm: [MVE intrinsics] factorize vfmaq vfmsq vfmasq Christophe Lyon
2023-05-12 9:38 ` [PATCH 17/26] arm: [MVE intrinsics] rework vfmaq vfmasq vfmsq Christophe Lyon
2023-05-12 9:38 ` [PATCH 18/26] arm: [MVE intrinsics] factorize vpselq Christophe Lyon
2023-05-12 9:38 ` [PATCH 19/26] arm: [MVE intrinsics] add vpsel shape Christophe Lyon
2023-05-12 9:38 ` [PATCH 20/26] arm: [MVE intrinsics] rework vpselq Christophe Lyon
2023-05-12 9:38 ` [PATCH 21/26] arm: [MVE intrinsics] add ternary_lshift shape Christophe Lyon
2023-05-12 9:38 ` [PATCH 22/26] arm: [MVE intrinsics] factorize vsliq Christophe Lyon
2023-05-12 9:38 ` [PATCH 23/26] arm: [MVE intrinsics] rework vsliq Christophe Lyon
2023-05-12 9:38 ` [PATCH 24/26] arm: [MVE intrinsics] add ternary_rshift shape Christophe Lyon
2023-05-12 9:38 ` [PATCH 25/26] arm: [MVE intrinsics] factorize vsriq Christophe Lyon
2023-05-12 9:38 ` [PATCH 26/26] arm: [MVE intrinsics] rework vsriq Christophe Lyon
2023-05-12 10:17 ` [PATCH 01/26] arm: [MVE intrinsics] add binary_widen_opt_n shape Kyrylo Tkachov
2023-05-12 10:38 ` Christophe Lyon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230512093855.79529-10-christophe.lyon@arm.com \
--to=christophe.lyon@arm.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=kyrylo.tkachov@arm.com \
--cc=richard.earnshaw@arm.com \
--cc=richard.sandiford@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).