From: Jin Ma <jinma@linux.alibaba.com>
To: gcc-patches@gcc.gnu.org
Cc: jeffreyalaw@gmail.com, kito.cheng@gmail.com,
jinma.contrib@gmail.com, Jin Ma <jinma@linux.alibaba.com>
Subject: [PATCH] RISC-V: Remove trailing spaces on lines.
Date: Wed, 17 May 2023 17:08:03 +0800 [thread overview]
Message-ID: <20230517090803.813-1-jinma@linux.alibaba.com> (raw)
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Remove
trailing spaces on lines.
* config/riscv/riscv.cc (riscv_legitimize_move): Likewise.
* config/riscv/riscv.h (enum reg_class): Likewise.
* config/riscv/riscv.md: Likewise.
---
gcc/common/config/riscv/riscv-common.cc | 2 +-
gcc/config/riscv/riscv.cc | 6 +++---
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/riscv.md | 4 ++--
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index 3a285dfbff0..e46ddf78132 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -104,7 +104,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zfh", "zfhmin"},
{"zfhmin", "f"},
-
+
{"zhinx", "zhinxmin"},
{"zhinxmin", "zfinx"},
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index b52e613c629..1eb3e142905 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2166,8 +2166,8 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
}
return true;
}
- /* Expand
- (set (reg:QI target) (mem:QI (address)))
+ /* Expand
+ (set (reg:QI target) (mem:QI (address)))
to
(set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
(set (reg:QI target) (subreg:QI (reg:DI temp) 0))
@@ -2182,7 +2182,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
temp_reg = gen_reg_rtx (word_mode);
zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND);
- emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
+ emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode,
zero_extend_p));
riscv_emit_move (dest, gen_lowpart (mode, temp_reg));
return true;
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index f74b70de562..70087d011f4 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -575,7 +575,7 @@ enum reg_class
#define POLY_SMALL_OPERAND_P(POLY_VALUE) \
(POLY_VALUE.is_constant () ? \
SMALL_OPERAND (POLY_VALUE.to_constant ()) : false)
-
+
/* True if VALUE can be loaded into a register using LUI. */
#define LUI_OPERAND(VALUE) \
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c5cf3af9868..f47ebb3a829 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -222,7 +222,7 @@ (define_attr "ext" "base,f,d,vector"
(define_attr "ext_enabled" "no,yes"
(cond [(eq_attr "ext" "base")
(const_string "yes")
-
+
(and (eq_attr "ext" "f")
(match_test "TARGET_HARD_FLOAT"))
(const_string "yes")
@@ -258,7 +258,7 @@ (define_attr "enabled" "no,yes"
;; logical integer logical instructions
;; shift integer shift instructions
;; slt set less than instructions
-;; imul integer multiply
+;; imul integer multiply
;; idiv integer divide
;; move integer register move (addi rd, rs1, 0)
;; fmove floating point register move
--
2.17.1
next reply other threads:[~2023-05-17 9:08 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 9:08 Jin Ma [this message]
2023-05-17 21:45 ` Jeff Law
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