From: Haochen Jiang <haochen.jiang@intel.com>
To: gcc-patches@gcc.gnu.org
Cc: hongtao.liu@intel.com, ubizjak@gmail.com
Subject: [PATCH 3/4] Support Intel SHA512
Date: Thu, 13 Jul 2023 14:03:34 +0800 [thread overview]
Message-ID: <20230713060335.203711-4-haochen.jiang@intel.com> (raw)
In-Reply-To: <20230713060335.203711-1-haochen.jiang@intel.com>
gcc/ChangeLog:
* common/config/i386/cpuinfo.h (get_available_features):
Detect SHA512.
* common/config/i386/i386-common.cc (OPTION_MASK_ISA2_SHA512_SET,
OPTION_MASK_ISA2_SHA512_UNSET): New.
(OPTION_MASK_ISA2_AVX_UNSET): Add SHA512.
(ix86_handle_option): Handle -msha512.
* common/config/i386/i386-cpuinfo.h (enum processor_features):
Add FEATURE_SHA512.
* common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
sha512.
* config.gcc: Add sha512intrin.h.
* config/i386/cpuid.h (bit_SHA512): New.
* config/i386/i386-builtin-types.def:
Add DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI).
* config/i386/i386-builtin.def (BDESC): Add new builtins.
* config/i386/i386-c.cc (ix86_target_macros_internal): Define
__SHA512__.
* config/i386/i386-expand.cc (ix86_expand_args_builtin): Handle
V4DI_FTYPE_V4DI_V4DI_V2DI and V4DI_FTYPE_V4DI_V2DI.
* config/i386/i386-isa.def (SHA512): Add DEF_PTA(SHA512).
* config/i386/i386-options.cc (isa2_opts): Add -msha512.
(ix86_valid_target_attribute_inner_p): Handle sha512.
* config/i386/i386.opt: Add option -msha512.
* config/i386/immintrin.h: Include sha512intrin.h.
* config/i386/sse.md (vsha512msg1): New define insn.
(vsha512msg2): Ditto.
(vsha512rnds2): Ditto.
* doc/extend.texi: Document sha512.
* doc/invoke.texi: Document -msha512.
* doc/sourcebuild.texi: Document target sha512.
* config/i386/sha512intrin.h: New file.
gcc/testsuite/ChangeLog:
* g++.dg/others/i386-2.C: Add -msha512.
* g++.dg/others/i386-3.C: Ditto.
* gcc.target/i386/funcspec-56.inc: Add new target attribute.
* gcc.target/i386/sse-12.c: Add -msha512.
* gcc.target/i386/sse-13.c: Ditto.
* gcc.target/i386/sse-14.c: Ditto.
* gcc.target/i386/sse-22.c: Add sha512.
* gcc.target/i386/sse-23.c: Ditto.
* lib/target-supports.exp (check_effective_target_sha512): New.
* gcc.target/i386/sha512-1.c: New test.
* gcc.target/i386/sha512-check.h: Ditto.
* gcc.target/i386/sha512msg1-2.c: Ditto.
* gcc.target/i386/sha512msg2-2.c: Ditto.
* gcc.target/i386/sha512rnds2-2.c: Ditto.
---
gcc/common/config/i386/cpuinfo.h | 2 +
gcc/common/config/i386/i386-common.cc | 19 ++++-
gcc/common/config/i386/i386-cpuinfo.h | 1 +
gcc/common/config/i386/i386-isas.h | 1 +
gcc/config.gcc | 2 +-
gcc/config/i386/cpuid.h | 1 +
gcc/config/i386/i386-builtin-types.def | 3 +
gcc/config/i386/i386-builtin.def | 5 ++
gcc/config/i386/i386-c.cc | 2 +
gcc/config/i386/i386-expand.cc | 2 +
gcc/config/i386/i386-isa.def | 1 +
gcc/config/i386/i386-options.cc | 4 +-
gcc/config/i386/i386.opt | 10 +++
gcc/config/i386/immintrin.h | 2 +
gcc/config/i386/sha512intrin.h | 64 ++++++++++++++
gcc/config/i386/sse.md | 40 +++++++++
gcc/doc/extend.texi | 5 ++
gcc/doc/invoke.texi | 10 ++-
gcc/doc/sourcebuild.texi | 3 +
gcc/testsuite/g++.dg/other/i386-2.C | 2 +-
gcc/testsuite/g++.dg/other/i386-3.C | 2 +-
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +
gcc/testsuite/gcc.target/i386/sha512-1.c | 18 ++++
gcc/testsuite/gcc.target/i386/sha512-check.h | 43 ++++++++++
gcc/testsuite/gcc.target/i386/sha512msg1-2.c | 48 +++++++++++
gcc/testsuite/gcc.target/i386/sha512msg2-2.c | 47 ++++++++++
gcc/testsuite/gcc.target/i386/sha512rnds2-2.c | 85 +++++++++++++++++++
gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-13.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-14.c | 2 +-
gcc/testsuite/gcc.target/i386/sse-22.c | 4 +-
gcc/testsuite/gcc.target/i386/sse-23.c | 2 +-
gcc/testsuite/lib/target-supports.exp | 14 +++
33 files changed, 436 insertions(+), 14 deletions(-)
create mode 100644 gcc/config/i386/sha512intrin.h
create mode 100644 gcc/testsuite/gcc.target/i386/sha512-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/sha512-check.h
create mode 100644 gcc/testsuite/gcc.target/i386/sha512msg1-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/sha512msg2-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/sha512rnds2-2.c
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index e5cdffe017a..0cfde3ebccd 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -879,6 +879,8 @@ get_available_features (struct __processor_model *cpu_model,
set_feature (FEATURE_AVXVNNIINT16);
if (eax & bit_SM3)
set_feature (FEATURE_SM3);
+ if (eax & bit_SHA512)
+ set_feature (FEATURE_SHA512);
}
if (avx512_usable)
{
diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
index 57b008ca3af..97c3cdfe5e1 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -121,6 +121,7 @@ along with GCC; see the file COPYING3. If not see
(OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX)
#define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
#define OPTION_MASK_ISA2_SM3_SET OPTION_MASK_ISA2_SM3
+#define OPTION_MASK_ISA2_SHA512_SET OPTION_MASK_ISA2_SHA512
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.2. */
@@ -305,6 +306,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
#define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
#define OPTION_MASK_ISA2_SM3_UNSET OPTION_MASK_ISA2_SM3
+#define OPTION_MASK_ISA2_SHA512_UNSET OPTION_MASK_ISA2_SHA512
/* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
as -mno-sse4.1. */
@@ -354,7 +356,7 @@ along with GCC; see the file COPYING3. If not see
OPTION_MASK_ISA2_SSE_UNSET
#define OPTION_MASK_ISA2_AVX_UNSET \
(OPTION_MASK_ISA2_AVX2_UNSET | OPTION_MASK_ISA2_VAES_UNSET \
- | OPTION_MASK_ISA2_SM3_UNSET)
+ | OPTION_MASK_ISA2_SM3_UNSET | OPTION_MASK_ISA2_SHA512_UNSET)
#define OPTION_MASK_ISA2_SSE4_2_UNSET OPTION_MASK_ISA2_AVX_UNSET
#define OPTION_MASK_ISA2_SSE4_1_UNSET OPTION_MASK_ISA2_SSE4_2_UNSET
#define OPTION_MASK_ISA2_SSE4_UNSET OPTION_MASK_ISA2_SSE4_1_UNSET
@@ -1306,6 +1308,21 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
+ case OPT_msha512:
+ if (value)
+ {
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_SHA512_SET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_SHA512_UNSET;
+ opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_SHA512_UNSET;
+ }
+ return true;
+
case OPT_mfma:
if (value)
{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
index c3403090c3b..a6e34d14f8e 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -257,6 +257,7 @@ enum processor_features
FEATURE_AMX_COMPLEX,
FEATURE_AVXVNNIINT16,
FEATURE_SM3,
+ FEATURE_SHA512,
CPU_FEATURE_MAX
};
diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
index 961a7f0ccd4..250dc87764f 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -189,4 +189,5 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("avxvnniint16", FEATURE_AVXVNNIINT16,
P_NONE, "-mavxvnniint16")
ISA_NAMES_TABLE_ENTRY("sm3", FEATURE_SM3, P_NONE, "-msm3")
+ ISA_NAMES_TABLE_ENTRY("sha512", FEATURE_SHA512, P_NONE, "-msha512")
ISA_NAMES_TABLE_END
diff --git a/gcc/config.gcc b/gcc/config.gcc
index fbd7360e355..4e753ba7c64 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -436,7 +436,7 @@ i[34567]86-*-* | x86_64-*-*)
avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h
cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h
raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h
- sm3intrin.h"
+ sm3intrin.h sha512intrin.h"
;;
ia64-*-*)
extra_headers=ia64intrin.h
diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
index 28a36ad0628..f9103f1b1c9 100644
--- a/gcc/config/i386/cpuid.h
+++ b/gcc/config/i386/cpuid.h
@@ -132,6 +132,7 @@
/* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */
/* %eax */
+#define bit_SHA512 (1 << 0)
#define bit_SM3 (1 << 1)
#define bit_RAOINT (1 << 3)
#define bit_AVXVNNI (1 << 4)
diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def
index 899eac1e014..e9463120eea 100644
--- a/gcc/config/i386/i386-builtin-types.def
+++ b/gcc/config/i386/i386-builtin-types.def
@@ -1419,3 +1419,6 @@ DEF_FUNCTION_TYPE (VOID, PCVOID, INT, INT, INT)
# SM3 builtins
DEF_FUNCTION_TYPE (V4SI, V4SI, V4SI, V4SI, INT)
+
+# SHA512 builtins
+DEF_FUNCTION_TYPE (V4DI, V4DI, V4DI, V2DI)
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 17db19c2495..b9e2bad8522 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -1660,6 +1660,11 @@ BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg1, "__builtin_
BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3msg2, "__builtin_ia32_vsm3msg2", IX86_BUILTIN_VSM3MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
BDESC (OPTION_MASK_ISA_AVX, OPTION_MASK_ISA2_SM3, CODE_FOR_vsm3rnds2, "__builtin_ia32_vsm3rnds2", IX86_BUILTIN_VSM3RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT)
+/* SHA512 */
+BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg1, "__builtin_ia32_vsha512msg1", IX86_BUILTIN_VSHA512MSG1, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI)
+BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512msg2, "__builtin_ia32_vsha512msg2", IX86_BUILTIN_VSHA512MSG2, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI)
+BDESC (0, OPTION_MASK_ISA2_SHA512, CODE_FOR_vsha512rnds2, "__builtin_ia32_vsha512rnds2", IX86_BUILTIN_VSHA512RNDS2, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V2DI)
+
/* AVX512VL. */
BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_USI_CONVERT)
BDESC (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UHI_CONVERT)
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 0cb5a6dcce5..c6311f12cf9 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -681,6 +681,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__AVXVNNIINT16__");
if (isa_flag2 & OPTION_MASK_ISA2_SM3)
def_or_undef (parse_in, "__SM3__");
+ if (isa_flag2 & OPTION_MASK_ISA2_SHA512)
+ def_or_undef (parse_in, "__SHA512__");
if (TARGET_IAMCU)
{
def_or_undef (parse_in, "__iamcu");
diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc
index f6ad54c0cfe..e99dcf19364 100644
--- a/gcc/config/i386/i386-expand.cc
+++ b/gcc/config/i386/i386-expand.cc
@@ -10733,6 +10733,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V4SF_FTYPE_V4SF_UINT:
case V4SF_FTYPE_V4SF_DI:
case V4SF_FTYPE_V4SF_SI:
+ case V4DI_FTYPE_V4DI_V2DI:
case V2DI_FTYPE_V2DI_V2DI:
case V2DI_FTYPE_V16QI_V16QI:
case V2DI_FTYPE_V4SI_V4SI:
@@ -11030,6 +11031,7 @@ ix86_expand_args_builtin (const struct builtin_description *d,
case V8HI_FTYPE_V8DI_V8HI_UQI:
case V8SI_FTYPE_V8DI_V8SI_UQI:
case V4SI_FTYPE_V4SI_V4SI_V4SI:
+ case V4DI_FTYPE_V4DI_V4DI_V2DI:
case V16SI_FTYPE_V16SI_V16SI_V16SI:
case V8DI_FTYPE_V8DI_V8DI_V8DI:
case V32HI_FTYPE_V32HI_V32HI_V32HI:
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 432c36e7f79..28f221753a9 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -119,3 +119,4 @@ DEF_PTA(RAOINT)
DEF_PTA(AMX_COMPLEX)
DEF_PTA(AVXVNNIINT16)
DEF_PTA(SM3)
+DEF_PTA(SHA512)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index db2ff0c7ae1..d79ab01bd79 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -241,7 +241,8 @@ static struct ix86_target_opts isa2_opts[] =
{ "-mraoint", OPTION_MASK_ISA2_RAOINT },
{ "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX },
{ "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 },
- { "-msm3", OPTION_MASK_ISA2_SM3 }
+ { "-msm3", OPTION_MASK_ISA2_SM3 },
+ { "-msha512", OPTION_MASK_ISA2_SHA512 }
};
static struct ix86_target_opts isa_opts[] =
{
@@ -1095,6 +1096,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
IX86_ATTR_ISA ("amx-complex", OPT_mamx_complex),
IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16),
IX86_ATTR_ISA ("sm3", OPT_msm3),
+ IX86_ATTR_ISA ("sha512", OPT_msha512),
/* enum options */
IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 80a8611993c..cf9dbca58b3 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -1288,3 +1288,13 @@ msm3
Target Mask(ISA2_SM3) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and
SM3 built-in functions and code generation.
+
+mvpinsrvpextr
+Target Mask(ISA2_VPINSRVPEXTR) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F,
+AVX512VL and VPINSRVPEXTR built-in functions and code generation.
+
+msha512
+Target Mask(ISA2_SHA512) Var(ix86_isa_flags2) Save
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and
+SHA512 built-in functions and code generation.
diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
index 7731990131c..6f2bcef6a8a 100644
--- a/gcc/config/i386/immintrin.h
+++ b/gcc/config/i386/immintrin.h
@@ -110,6 +110,8 @@
#include <sm3intrin.h>
+#include <sha512intrin.h>
+
#include <fmaintrin.h>
#include <f16cintrin.h>
diff --git a/gcc/config/i386/sha512intrin.h b/gcc/config/i386/sha512intrin.h
new file mode 100644
index 00000000000..884c2bc6340
--- /dev/null
+++ b/gcc/config/i386/sha512intrin.h
@@ -0,0 +1,64 @@
+/* Copyright (C) 2023 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+#error "Never use <sha512intrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _SHA512INTRIN_H_INCLUDED
+#define _SHA512INTRIN_H_INCLUDED
+
+#ifndef __SHA512__
+#pragma GCC push_options
+#pragma GCC target("sha512")
+#define __DISABLE_SHA512__
+#endif /* __SHA512__ */
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_sha512msg1_epi64 (__m256i __A, __m128i __B)
+{
+ return (__m256i) __builtin_ia32_vsha512msg1 ((__v4di) __A, (__v2di) __B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_sha512msg2_epi64 (__m256i __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A, (__v4di) __B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_sha512rnds2_epi64 (__m256i __A, __m256i __B, __m128i __C)
+{
+ return (__m256i) __builtin_ia32_vsha512rnds2 ((__v4di) __A, (__v4di) __B,
+ (__v2di) __C);
+}
+
+#ifdef __DISABLE_SHA512__
+#undef __DISABLE_SHA512__
+#pragma GCC pop_options
+#endif /* __DISABLE_SHA512__ */
+
+#endif /* _SHA512INTRIN_H_INCLUDED */
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 25a1e5dd780..e16b2b5a6c4 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -217,6 +217,12 @@
UNSPEC_VPDPWSUDS
UNSPEC_VPDPWUUD
UNSPEC_VPDPWUUDS
+
+ ;; For SHA512 support
+ UNSPEC_SHA512MSG1
+ UNSPEC_SHA512MSG2
+ UNSPEC_SHA512RNDS2
+
])
(define_c_enum "unspecv" [
@@ -28640,6 +28646,40 @@
(set_attr "mode" "TI")
(set_attr "length_immediate" "1")])
+(define_insn "vsha512msg1"
+ [(set (match_operand:V4DI 0 "register_operand" "=x")
+ (unspec:V4DI
+ [(match_operand:V4DI 1 "register_operand" "0")
+ (match_operand:V2DI 2 "register_operand" "x")]
+ UNSPEC_SHA512MSG1))]
+ "TARGET_SHA512"
+ "vsha512msg1\t{%2, %0|%0, %2}"
+ [(set_attr "type" "sselog1")
+ (set_attr "mode" "OI")])
+
+(define_insn "vsha512msg2"
+ [(set (match_operand:V4DI 0 "register_operand" "=x")
+ (unspec:V4DI
+ [(match_operand:V4DI 1 "register_operand" "0")
+ (match_operand:V4DI 2 "register_operand" "x")]
+ UNSPEC_SHA512MSG2))]
+ "TARGET_SHA512"
+ "vsha512msg2\t{%2, %0|%0, %2}"
+ [(set_attr "type" "sselog1")
+ (set_attr "mode" "OI")])
+
+(define_insn "vsha512rnds2"
+ [(set (match_operand:V4DI 0 "register_operand" "=x")
+ (unspec:V4DI
+ [(match_operand:V4DI 1 "register_operand" "0")
+ (match_operand:V4DI 2 "register_operand" "x")
+ (match_operand:V2DI 3 "register_operand" "x")]
+ UNSPEC_SHA512RNDS2))]
+ "TARGET_SHA512"
+ "vsha512rnds2\t{%3, %2, %0|%0, %2, %3}"
+ [(set_attr "type" "sselog1")
+ (set_attr "mode" "OI")])
+
(define_insn_and_split "avx512f_<castmode><avxsizesuffix>_<castmode>"
[(set (match_operand:AVX512MODE2P 0 "nonimmediate_operand" "=x,m")
(vec_concat:AVX512MODE2P
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index e76cd399a83..5250990050b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -7173,6 +7173,11 @@ Enable/disable the generation of the AVXVNNIINT16 instructions.
@itemx no-sm3
Enable/disable the generation of the SM3 instructions.
+@cindex @code{target("sha512")} function attribute, x86
+@item sha512
+@itemx no-sha512
+Enable/disable the generation of the SHA512 instructions.
+
@cindex @code{target("cld")} function attribute, x86
@item cld
@itemx no-cld
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2671d70736f..433ccf35505 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options.
-mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk
-mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni
-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
--mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3
+-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@@ -33558,6 +33558,9 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@need 200
@opindex msm3
@itemx -msm3
+@need 200
+@opindex msha512
+@itemx -msha512
These switches enable the use of instructions in the MMX, SSE,
AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
@@ -33568,8 +33571,9 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
-AMX-COMPLEX, AVXVNNIINT16, SM3 or CLDEMOTE extended instruction sets. Each has a
-corresponding @option{-mno-} option to disable use of these instructions.
+AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512 or CLDEMOTE extended instruction sets.
+Each has a corresponding @option{-mno-} option to disable use of these
+instructions.
These extensions are also available as built-in functions: see
@ref{x86 Built-in Functions}, for details of the functions enabled and
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index dae51132c42..54a062db3fe 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2589,6 +2589,9 @@ Target supports the execution of @code{raoint} instructions.
@item rdrand
Target supports x86 @code{rdrand} instruction.
+@item sha512
+Target supports the execution of @code{sha512} instructions.
+
@item sm3
Target supports the execution of @code{sm3} instructions.
diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C
index 2ec93261cac..985f14abcbc 100644
--- a/gcc/testsuite/g++.dg/other/i386-2.C
+++ b/gcc/testsuite/g++.dg/other/i386-2.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C
index fe03143e39b..274b0e6256f 100644
--- a/gcc/testsuite/g++.dg/other/i386-3.C
+++ b/gcc/testsuite/g++.dg/other/i386-3.C
@@ -1,5 +1,5 @@
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index 8dd8d9bf9d8..eb9309819ab 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -90,6 +90,7 @@ extern void test_raoint (void) __attribute__((__target__("raoin
extern void test_amx_complex (void) __attribute__((__target__("amx-complex")));
extern void test_avxvnniint16 (void) __attribute__((__target__("avxvnniint16")));
extern void test_sm3 (void) __attribute__((__target__("sm3")));
+extern void test_sha512 (void) __attribute__((__target__("sha512")));
extern void test_no_sgx (void) __attribute__((__target__("no-sgx")));
extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps")));
@@ -181,6 +182,7 @@ extern void test_no_raoint (void) __attribute__((__target__("no-ra
extern void test_no_amx_complex (void) __attribute__((__target__("no-amx-complex")));
extern void test_no_avxvnniint16 (void) __attribute__((__target__("no-avxvnniint16")));
extern void test_no_sm3 (void) __attribute__((__target__("no-sm3")));
+extern void test_no_sha512 (void) __attribute__((__target__("no-sha512")));
extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona")));
extern void test_arch_core2 (void) __attribute__((__target__("arch=core2")));
diff --git a/gcc/testsuite/gcc.target/i386/sha512-1.c b/gcc/testsuite/gcc.target/i386/sha512-1.c
new file mode 100644
index 00000000000..c66e8124d6b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sha512-1.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msha512" } */
+/* { dg-final { scan-assembler "vsha512msg1\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%ymm\[0-9\]" } } */
+/* { dg-final { scan-assembler "vsha512msg2\[ \\t\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]" } } */
+/* { dg-final { scan-assembler "vsha512rnds2\[ \\t\]+\[^\n\]*%xmm\[0-9\]+\[^\n\]*%ymm\[0-9\]+\[^\n\]*%ymm\[0-9\]" } } */
+
+#include <immintrin.h>
+
+volatile __m128i x;
+volatile __m256i y;
+
+void extern
+sha512_test (void)
+{
+ y = _mm256_sha512msg1_epi64(y, x);
+ y = _mm256_sha512msg2_epi64(y, y);
+ y = _mm256_sha512rnds2_epi64(y, y, x);
+}
diff --git a/gcc/testsuite/gcc.target/i386/sha512-check.h b/gcc/testsuite/gcc.target/i386/sha512-check.h
new file mode 100644
index 00000000000..083bf3b6a1b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sha512-check.h
@@ -0,0 +1,43 @@
+#include <stdlib.h>
+#include "m256-check.h"
+
+static void sha512_test (void);
+
+static unsigned long long
+ror64 (unsigned long long w, int n)
+{
+ int count = n % 64;
+ return ((w >> n) | (w << (64 - n)));
+}
+
+static unsigned long long
+shr64 (unsigned long long w, int n)
+{
+ return (w >> n);
+}
+
+static void
+__attribute__ ((noinline))
+do_test(void)
+{
+ sha512_test ();
+}
+
+int
+main ()
+{
+ /* Check CPU support for SHA512. */
+ if (__builtin_cpu_supports ("sha512"))
+ {
+ do_test ();
+#ifdef DEBUG
+ printf ("PASSED\n");
+#endif
+ return 0;
+ }
+
+#ifdef DEBUG
+ printf ("SKIPPED\n");
+#endif
+ return 0;
+}
diff --git a/gcc/testsuite/gcc.target/i386/sha512msg1-2.c b/gcc/testsuite/gcc.target/i386/sha512msg1-2.c
new file mode 100644
index 00000000000..b7baff1cfb4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sha512msg1-2.c
@@ -0,0 +1,48 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha512" } */
+/* { dg-require-effective-target sha512 } */
+
+#include "sha512-check.h"
+#include <emmintrin.h>
+#include <immintrin.h>
+
+static unsigned long long
+s0 (unsigned long long w)
+{
+ return ror64 (w, 1) ^ ror64 (w, 8) ^ shr64 (w, 7);
+}
+
+static void
+compute_sha512msg1(long long* src1, long long* src2, long long* res)
+{
+ unsigned long long w0, w1, w2, w3, w4;
+
+ w0 = src1[0];
+ w1 = src1[1];
+ w2 = src1[2];
+ w3 = src1[3];
+ w4 = src2[0];
+
+ res[0] = w0 + s0 (w1);
+ res[1] = w1 + s0 (w2);
+ res[2] = w2 + s0 (w3);
+ res[3] = w3 + s0 (w4);
+}
+
+static void
+sha512_test(void)
+{
+ union256i_q s1, res;
+ union128i_q s2;
+ long long res_ref[4];
+
+ s1.x = _mm256_set_epi64x (111, 222, 333, 444);
+ s2.x = _mm_set_epi64x (0, 555);
+
+ res.x = _mm256_sha512msg1_epi64 (s1.x, s2.x);
+
+ compute_sha512msg1 (s1.a, s2.a, res_ref);
+
+ if (check_union256i_q (res, res_ref))
+ abort();
+}
diff --git a/gcc/testsuite/gcc.target/i386/sha512msg2-2.c b/gcc/testsuite/gcc.target/i386/sha512msg2-2.c
new file mode 100644
index 00000000000..e5033903f06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sha512msg2-2.c
@@ -0,0 +1,47 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha512" } */
+/* { dg-require-effective-target sha512 } */
+
+#include "sha512-check.h"
+#include <immintrin.h>
+
+static unsigned long long
+s1 (unsigned long long w)
+{
+ return ror64 (w, 19) ^ ror64 (w, 61) ^ shr64 (w, 6);
+}
+
+static void
+compute_sha512msg2 (long long* src1, long long* src2, long long* res)
+{
+ unsigned long long w14, w15, w16, w17, w18, w19;
+
+ w14 = src2[2];
+ w15 = src2[3];
+ w16 = src1[0] + s1 (w14);
+ w17 = src1[1] + s1 (w15);
+ w18 = src1[2] + s1 (w16);
+ w19 = src1[3] + s1 (w17);
+
+ res[0] = w16;
+ res[1] = w17;
+ res[2] = w18;
+ res[3] = w19;
+}
+
+static void
+sha512_test (void)
+{
+ union256i_q s1, s2, res;
+ long long res_ref[4];
+
+ s1.x = _mm256_set_epi64x (111, 222, 333, 444);
+ s2.x = _mm256_set_epi64x (555, 666, 0, 0);
+
+ res.x = _mm256_sha512msg2_epi64 (s1.x, s2.x);
+
+ compute_sha512msg2 (s1.a, s2.a, res_ref);
+
+ if (check_union256i_q (res, res_ref))
+ abort();
+}
diff --git a/gcc/testsuite/gcc.target/i386/sha512rnds2-2.c b/gcc/testsuite/gcc.target/i386/sha512rnds2-2.c
new file mode 100644
index 00000000000..3bc6a00a05b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/sha512rnds2-2.c
@@ -0,0 +1,85 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msha512" } */
+/* { dg-require-effective-target sha512 } */
+
+#include "sha512-check.h"
+#include <emmintrin.h>
+#include <immintrin.h>
+
+static unsigned long long
+ch (unsigned long long e, unsigned long long f, unsigned long long g)
+{
+ return (e & f) ^ (~e & g);
+}
+
+static unsigned long long
+maj (unsigned long long a, unsigned long long b, unsigned long long c)
+{
+ return (a & b) ^ (a & c) ^ (b & c);
+}
+
+static unsigned long long
+s0 (unsigned long long w)
+{
+ return ror64 (w, 28) ^ ror64 (w, 34) ^ ror64 (w, 39);
+}
+
+static unsigned long long
+s1 (unsigned long long w)
+{
+ return ror64 (w, 14) ^ ror64 (w, 18) ^ ror64 (w, 41);
+}
+
+static void
+compute_sha512rnds2(long long* src0, long long* src1, long long* src2, long long* res)
+{
+ unsigned long long wk[2] = { src2[0], src2[1] };
+ unsigned long long a[3], b[3], c[3], d[3], e[3], f[3], g[3], h[3];
+
+ a[0] = src1[3];
+ b[0] = src1[2];
+ c[0] = src0[3];
+ d[0] = src0[2];
+ e[0] = src1[1];
+ f[0] = src1[0];
+ g[0] = src0[1];
+ h[0] = src0[0];
+
+ int i;
+ for (i = 0; i <= 1; i++)
+ {
+ a[i + 1] = ch (e[i], f[i], g[i]) + s1 (e[i]) + wk[i] + h[i]
+ + maj (a[i], b[i], c[i]) + s0 (a[i]);
+ b[i + 1] = a[i];
+ c[i + 1] = b[i];
+ d[i + 1] = c[i];
+ e[i + 1] = ch (e[i], f[i], g[i]) + s1 (e[i]) + wk[i] + h[i] + d[i];
+ f[i + 1] = e[i];
+ g[i + 1] = f[i];
+ h[i + 1] = g[i];
+ }
+
+ res[0] = f[2];
+ res[1] = e[2];
+ res[2] = b[2];
+ res[3] = a[2];
+}
+
+static void
+sha512_test (void)
+{
+ union256i_q s0, s1, res;
+ union128i_q s2;
+ long long res_ref[4];
+
+ s0.x = _mm256_set_epi64x (111, 222, 333, 444);
+ s1.x = _mm256_set_epi64x (555, 666, 777, 888);
+ s2.x = _mm_set_epi64x (999, 123);
+
+ res.x = _mm256_sha512rnds2_epi64 (s0.x, s1.x, s2.x);
+
+ compute_sha512rnds2 (s0.a, s1.a, s2.a, res_ref);
+
+ if (check_union256i_q (res, res_ref))
+ abort();
+}
diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c
index 5058be6f6e9..976541389ea 100644
--- a/gcc/testsuite/gcc.target/i386/sse-12.c
+++ b/gcc/testsuite/gcc.target/i386/sse-12.c
@@ -3,7 +3,7 @@
popcntintrin.h gfniintrin.h and mm_malloc.h are usable
with -O -std=c89 -pedantic-errors. */
/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
+/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */
#include <x86intrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
index d30b365564a..8c314e70e31 100644
--- a/gcc/testsuite/gcc.target/i386/sse-13.c
+++ b/gcc/testsuite/gcc.target/i386/sse-13.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
index 7842005a98b..2b4d7bc9079 100644
--- a/gcc/testsuite/gcc.target/i386/sse-14.c
+++ b/gcc/testsuite/gcc.target/i386/sse-14.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512" } */
/* { dg-add-options bind_pic_locally } */
#include <mm_malloc.h>
diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
index 7537db1ac30..d6f19b5e20a 100644
--- a/gcc/testsuite/gcc.target/i386/sse-22.c
+++ b/gcc/testsuite/gcc.target/i386/sse-22.c
@@ -103,7 +103,7 @@
#ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512")
#endif
/* Following intrinsics require immediate arguments. They
@@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
/* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3")
+#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16,sm3,sha512")
#endif
#include <immintrin.h>
test_1 (_cvtss_sh, unsigned short, float, 1)
diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
index 3fc61b50fe6..1df66b525ca 100644
--- a/gcc/testsuite/gcc.target/i386/sse-23.c
+++ b/gcc/testsuite/gcc.target/i386/sse-23.c
@@ -850,6 +850,6 @@
/* sm3intrin.h */
#define __builtin_ia32_vsm3rnds2(A, B, C, D) __builtin_ia32_vsm3rnds2 (A, B, C, 1)
-#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3")
+#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16,sm3,sha512")
#include <x86intrin.h>
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index c911a824d31..f376d835f8b 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -9883,6 +9883,20 @@ proc check_effective_target_sm3 { } {
} "-msm3" ]
}
+# Return 1 if sha512 instructions can be compiled.
+proc check_effective_target_sha512 { } {
+ return [check_no_compiler_messages sha512 object {
+ typedef long long __m256i __attribute__ ((__vector_size__ (32)));
+ typedef long long __v4di __attribute__ ((__vector_size__ (32)));
+ __m256i
+ _mm256_sha512msg2_epi64 (__m256i __A, __m256i __B)
+ {
+ return (__m256i) __builtin_ia32_vsha512msg2 ((__v4di) __A,
+ (__v4di) __B);
+ }
+ } "-msha512" ]
+}
+
# Return 1 if sse instructions can be compiled.
proc check_effective_target_sse { } {
return [check_no_compiler_messages sse object {
--
2.31.1
next prev parent reply other threads:[~2023-07-13 6:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-13 6:03 [PATCH 0/4] Support Intel Arrow Lake/Lunar Lake ISAs Haochen Jiang
2023-07-13 6:03 ` [PATCH 1/4] Support Intel AVX-VNNI-INT16 Haochen Jiang
2023-07-17 1:39 ` Hongtao Liu
2023-07-13 6:03 ` [PATCH 2/4] Support Intel SM3 Haochen Jiang
2023-07-17 1:39 ` Hongtao Liu
2023-07-13 6:03 ` Haochen Jiang [this message]
2023-07-17 1:40 ` [PATCH 3/4] Support Intel SHA512 Hongtao Liu
2023-07-13 6:03 ` [PATCH 4/4] Support Intel SM4 Haochen Jiang
2023-07-17 1:40 ` Hongtao Liu
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