From: Hongtao Liu <crazylht@gmail.com>
To: Haochen Jiang <haochen.jiang@intel.com>
Cc: gcc-patches@gcc.gnu.org, hongtao.liu@intel.com,
ubizjak@gmail.com, Kong Lingling <lingling.kong@intel.com>
Subject: Re: [PATCH 1/4] Support Intel AVX-VNNI-INT16
Date: Mon, 17 Jul 2023 09:39:19 +0800 [thread overview]
Message-ID: <CAMZc-bzK+E+TyEPPK1oEvrUbRMKwucs2WXBL2TSYFMyEu0uHSg@mail.gmail.com> (raw)
In-Reply-To: <20230713060335.203711-2-haochen.jiang@intel.com>
On Thu, Jul 13, 2023 at 2:06 PM Haochen Jiang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Kong Lingling <lingling.kong@intel.com>
>
> gcc/ChangeLog
>
> * common/config/i386/cpuinfo.h (get_available_features): Detect
> avxvnniint16.
> * common/config/i386/i386-common.cc
> (OPTION_MASK_ISA2_AVXVNNIINT16_SET): New.
> (OPTION_MASK_ISA2_AVXVNNIINT16_UNSET): Ditto.
> (ix86_handle_option): Handle -mavxvnniint16.
> * common/config/i386/i386-cpuinfo.h (enum processor_features):
> Add FEATURE_AVXVNNIINT16.
> * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for
> avxvnniint16.
> * config.gcc: Add avxvnniint16.h.
> * config/i386/avxvnniint16intrin.h: New file.
> * config/i386/cpuid.h (bit_AVXVNNIINT16): New.
> * config/i386/i386-builtin.def: Add new builtins.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Define
> __AVXVNNIINT16__.
> * config/i386/i386-options.cc (isa2_opts): Add -mavxvnniint16.
> (ix86_valid_target_attribute_inner_p): Handle avxvnniint16intrin.h.
> * config/i386/i386-isa.def: Add DEF_PTA(AVXVNNIINT16).
> * config/i386/i386.opt: Add option -mavxvnniint16.
> * config/i386/immintrin.h: Include avxvnniint16.h.
> * config/i386/sse.md
> (vpdp<vpdpwprodtype>_<mode>): New define_insn.
> * doc/extend.texi: Document avxvnniint16.
> * doc/invoke.texi: Document -mavxvnniint16.
> * doc/sourcebuild.texi: Document target avxvnniint16.
Ok.
>
> gcc/testsuite/ChangeLog
>
> * g++.dg/other/i386-2.C: Add -mavxvnniint16.
> * g++.dg/other/i386-3.C: Ditto.
> * gcc.target/i386/avx-check.h: Add avxvnniint16 check.
> * gcc.target/i386/sse-12.c: Add -mavxvnniint16.
> * gcc.target/i386/sse-13.c: Ditto.
> * gcc.target/i386/sse-14.c: Ditto.
> * gcc.target/i386/sse-22.c: Ditto.
> * gcc.target/i386/sse-23.c: Ditto.
> * gcc.target/i386/funcspec-56.inc: Add new target attribute.
> * lib/target-supports.exp
> (check_effective_target_avxvnniint16): New.
> * gcc.target/i386/avxvnniint16-1.c: Ditto.
> * gcc.target/i386/avxvnniint16-vpdpwusd-2.c: Ditto.
> * gcc.target/i386/avxvnniint16-vpdpwusds-2.c: Ditto.
> * gcc.target/i386/avxvnniint16-vpdpwsud-2.c: Ditto.
> * gcc.target/i386/avxvnniint16-vpdpwsuds-2.c: Ditto.
> * gcc.target/i386/avxvnniint16-vpdpwuud-2.c: Ditto.
> * gcc.target/i386/avxvnniint16-vpdpwuuds-2.c: Ditto.
>
> Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
> ---
> gcc/common/config/i386/cpuinfo.h | 2 +
> gcc/common/config/i386/i386-common.cc | 22 ++-
> gcc/common/config/i386/i386-cpuinfo.h | 1 +
> gcc/common/config/i386/i386-isas.h | 2 +
> gcc/config.gcc | 2 +-
> gcc/config/i386/avxvnniint16intrin.h | 138 ++++++++++++++++++
> gcc/config/i386/cpuid.h | 1 +
> gcc/config/i386/i386-builtin.def | 14 ++
> gcc/config/i386/i386-c.cc | 2 +
> gcc/config/i386/i386-isa.def | 1 +
> gcc/config/i386/i386-options.cc | 4 +-
> gcc/config/i386/i386.opt | 5 +
> gcc/config/i386/immintrin.h | 2 +
> gcc/config/i386/sse.md | 32 ++++
> gcc/doc/extend.texi | 5 +
> gcc/doc/invoke.texi | 10 +-
> gcc/doc/sourcebuild.texi | 3 +
> gcc/testsuite/g++.dg/other/i386-2.C | 2 +-
> gcc/testsuite/g++.dg/other/i386-3.C | 2 +-
> gcc/testsuite/gcc.target/i386/avx-check.h | 3 +
> .../gcc.target/i386/avxvnniint16-1.c | 43 ++++++
> .../gcc.target/i386/avxvnniint16-vpdpwsud-2.c | 71 +++++++++
> .../i386/avxvnniint16-vpdpwsuds-2.c | 72 +++++++++
> .../gcc.target/i386/avxvnniint16-vpdpwusd-2.c | 71 +++++++++
> .../i386/avxvnniint16-vpdpwusds-2.c | 72 +++++++++
> .../gcc.target/i386/avxvnniint16-vpdpwuud-2.c | 71 +++++++++
> .../i386/avxvnniint16-vpdpwuuds-2.c | 71 +++++++++
> gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 +
> gcc/testsuite/gcc.target/i386/sse-12.c | 2 +-
> gcc/testsuite/gcc.target/i386/sse-13.c | 2 +-
> gcc/testsuite/gcc.target/i386/sse-14.c | 2 +-
> gcc/testsuite/gcc.target/i386/sse-22.c | 4 +-
> gcc/testsuite/gcc.target/i386/sse-23.c | 2 +-
> gcc/testsuite/lib/target-supports.exp | 12 ++
> 34 files changed, 735 insertions(+), 15 deletions(-)
> create mode 100644 gcc/config/i386/avxvnniint16intrin.h
> create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsud-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsuds-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusd-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusds-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuud-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuuds-2.c
>
> diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
> index 7c2565c1d93..3599f9def2c 100644
> --- a/gcc/common/config/i386/cpuinfo.h
> +++ b/gcc/common/config/i386/cpuinfo.h
> @@ -875,6 +875,8 @@ get_available_features (struct __processor_model *cpu_model,
> set_feature (FEATURE_AVXVNNIINT8);
> if (edx & bit_AVXNECONVERT)
> set_feature (FEATURE_AVXNECONVERT);
> + if (edx & bit_AVXVNNIINT16)
> + set_feature (FEATURE_AVXVNNIINT16);
> }
> if (avx512_usable)
> {
> diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc
> index 8cea3669239..32c6d00580d 100644
> --- a/gcc/common/config/i386/i386-common.cc
> +++ b/gcc/common/config/i386/i386-common.cc
> @@ -119,6 +119,7 @@ along with GCC; see the file COPYING3. If not see
> #define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT
> #define OPTION_MASK_ISA2_AMX_COMPLEX_SET \
> (OPTION_MASK_ISA2_AMX_TILE | OPTION_MASK_ISA2_AMX_COMPLEX)
> +#define OPTION_MASK_ISA2_AVXVNNIINT16_SET OPTION_MASK_ISA2_AVXVNNIINT16
>
> /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
> as -msse4.2. */
> @@ -228,7 +229,7 @@ along with GCC; see the file COPYING3. If not see
> #define OPTION_MASK_ISA2_AVX2_UNSET \
> (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
> | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
> - | OPTION_MASK_ISA2_AVX512F_UNSET)
> + | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
> #define OPTION_MASK_ISA_AVX512F_UNSET \
> (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
> | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
> @@ -301,6 +302,7 @@ along with GCC; see the file COPYING3. If not see
> #define OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI
> #define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT
> #define OPTION_MASK_ISA2_AMX_COMPLEX_UNSET OPTION_MASK_ISA2_AMX_COMPLEX
> +#define OPTION_MASK_ISA2_AVXVNNIINT16_UNSET OPTION_MASK_ISA2_AVXVNNIINT16
>
> /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
> as -mno-sse4.1. */
> @@ -1268,6 +1270,24 @@ ix86_handle_option (struct gcc_options *opts,
> }
> return true;
>
> + case OPT_mavxvnniint16:
> + if (value)
> + {
> + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVXVNNIINT16_SET;
> + opts->x_ix86_isa_flags2_explicit |=
> + OPTION_MASK_ISA2_AVXVNNIINT16_SET;
> + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
> + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
> + }
> + else
> + {
> + opts->x_ix86_isa_flags2 &=
> + ~OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
> + opts->x_ix86_isa_flags2_explicit |=
> + OPTION_MASK_ISA2_AVXVNNIINT16_UNSET;
> + }
> + return true;
> +
> case OPT_mfma:
> if (value)
> {
> diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h
> index 254dfec70e5..ae4e6a02f7f 100644
> --- a/gcc/common/config/i386/i386-cpuinfo.h
> +++ b/gcc/common/config/i386/i386-cpuinfo.h
> @@ -255,6 +255,7 @@ enum processor_features
> FEATURE_PREFETCHI,
> FEATURE_RAOINT,
> FEATURE_AMX_COMPLEX,
> + FEATURE_AVXVNNIINT16,
> CPU_FEATURE_MAX
> };
>
> diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h
> index d4b0b23b417..fc6abdedf24 100644
> --- a/gcc/common/config/i386/i386-isas.h
> +++ b/gcc/common/config/i386/i386-isas.h
> @@ -186,4 +186,6 @@ ISA_NAMES_TABLE_START
> ISA_NAMES_TABLE_ENTRY("raoint", FEATURE_RAOINT, P_NONE, "-mraoint")
> ISA_NAMES_TABLE_ENTRY("amx-complex", FEATURE_AMX_COMPLEX,
> P_NONE, "-mamx-complex")
> + ISA_NAMES_TABLE_ENTRY("avxvnniint16", FEATURE_AVXVNNIINT16,
> + P_NONE, "-mavxvnniint16")
> ISA_NAMES_TABLE_END
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index 1446eb2b3ca..fc74d776048 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -435,7 +435,7 @@ i[34567]86-*-* | x86_64-*-*)
> mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h
> avxifmaintrin.h avxvnniint8intrin.h avxneconvertintrin.h
> cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h
> - raointintrin.h amxcomplexintrin.h"
> + raointintrin.h amxcomplexintrin.h avxvnniint16intrin.h"
> ;;
> ia64-*-*)
> extra_headers=ia64intrin.h
> diff --git a/gcc/config/i386/avxvnniint16intrin.h b/gcc/config/i386/avxvnniint16intrin.h
> new file mode 100644
> index 00000000000..f87d76cb9f3
> --- /dev/null
> +++ b/gcc/config/i386/avxvnniint16intrin.h
> @@ -0,0 +1,138 @@
> +/* Copyright (C) 2023 Free Software Foundation, Inc.
> +
> + This file is part of GCC.
> +
> + GCC is free software; you can redistribute it and/or modify
> + it under the terms of the GNU General Public License as published by
> + the Free Software Foundation; either version 3, or (at your option)
> + any later version.
> +
> + GCC is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + GNU General Public License for more details.
> +
> + Under Section 7 of GPL version 3, you are granted additional
> + permissions described in the GCC Runtime Library Exception, version
> + 3.1, as published by the Free Software Foundation.
> +
> + You should have received a copy of the GNU General Public License and
> + a copy of the GCC Runtime Library Exception along with this program;
> + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
> + <http://www.gnu.org/licenses/>. */
> +
> +#if !defined _IMMINTRIN_H_INCLUDED
> +#error "Never use <avxvnniint16intrin.h> directly; include <immintrin.h> instead."
> +#endif
> +
> +#ifndef _AVXVNNIINT16INTRIN_H_INCLUDED
> +#define _AVXVNNIINT16INTRIN_H_INCLUDED
> +
> +#if !defined(__AVXVNNIINT16__)
> +#pragma GCC push_options
> +#pragma GCC target("avxvnniint16")
> +#define __DISABLE_AVXVNNIINT16__
> +#endif /* __AVXVNNIINT16__ */
> +
> +extern __inline __m128i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_dpwsud_avx_epi32 (__m128i __W, __m128i __A, __m128i __B)
> +{
> + return (__m128i)
> + __builtin_ia32_vpdpwsud128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);
> +}
> +
> +extern __inline __m128i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_dpwsuds_avx_epi32 (__m128i __W, __m128i __A, __m128i __B)
> +{
> + return (__m128i)
> + __builtin_ia32_vpdpwsuds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);
> +}
> +
> +extern __inline __m128i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_dpwusd_avx_epi32 (__m128i __W, __m128i __A, __m128i __B)
> +{
> + return (__m128i)
> + __builtin_ia32_vpdpwusd128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);
> +}
> +
> +extern __inline __m128i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_dpwusds_avx_epi32 (__m128i __W, __m128i __A, __m128i __B)
> +{
> + return (__m128i)
> + __builtin_ia32_vpdpwusds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);
> +}
> +
> +extern __inline __m128i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_dpwuud_avx_epi32 (__m128i __W, __m128i __A, __m128i __B)
> +{
> + return (__m128i)
> + __builtin_ia32_vpdpwuud128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);
> +}
> +
> +extern __inline __m128i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm_dpwuuds_avx_epi32 (__m128i __W, __m128i __A, __m128i __B)
> +{
> + return (__m128i)
> + __builtin_ia32_vpdpwuuds128 ((__v4si) __W, (__v4si) __A, (__v4si) __B);
> +}
> +
> +extern __inline __m256i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_dpwsud_avx_epi32 (__m256i __W, __m256i __A, __m256i __B)
> +{
> + return (__m256i)
> + __builtin_ia32_vpdpwsud256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);
> +}
> +
> +extern __inline __m256i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_dpwsuds_avx_epi32 (__m256i __W, __m256i __A, __m256i __B)
> +{
> + return (__m256i)
> + __builtin_ia32_vpdpwsuds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);
> +}
> +
> +extern __inline __m256i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_dpwusd_avx_epi32 (__m256i __W, __m256i __A, __m256i __B)
> +{
> + return (__m256i)
> + __builtin_ia32_vpdpwusd256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);
> +}
> +
> +extern __inline __m256i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_dpwusds_avx_epi32 (__m256i __W, __m256i __A, __m256i __B)
> +{
> + return (__m256i)
> + __builtin_ia32_vpdpwusds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);
> +}
> +
> +extern __inline __m256i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_dpwuud_avx_epi32 (__m256i __W, __m256i __A, __m256i __B)
> +{
> + return (__m256i)
> + __builtin_ia32_vpdpwuud256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);
> +}
> +
> +extern __inline __m256i
> +__attribute__((__gnu_inline__, __always_inline__, __artificial__))
> +_mm256_dpwuuds_avx_epi32 (__m256i __W, __m256i __A, __m256i __B)
> +{
> + return (__m256i)
> + __builtin_ia32_vpdpwuuds256 ((__v8si) __W, (__v8si) __A, (__v8si) __B);
> +}
> +
> +#ifdef __DISABLE_AVXVNNIINT16__
> +#undef __DISABLE_AVXVNNIINT16__
> +#pragma GCC pop_options
> +#endif /* __DISABLE_AVXVNNIINT16__ */
> +
> +#endif /* __AVXVNNIINT16INTRIN_H_INCLUDED */
> diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h
> index 4cc44615cf6..98d0f193d22 100644
> --- a/gcc/config/i386/cpuid.h
> +++ b/gcc/config/i386/cpuid.h
> @@ -144,6 +144,7 @@
> /* %edx */
> #define bit_AVXVNNIINT8 (1 << 4)
> #define bit_AVXNECONVERT (1 << 5)
> +#define bit_AVXVNNIINT16 (1 << 10)
> #define bit_PREFETCHI (1 << 14)
>
> /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
> diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
> index 7ba5b6a9d11..ff5b3dcbcd3 100644
> --- a/gcc/config/i386/i386-builtin.def
> +++ b/gcc/config/i386/i386-builtin.def
> @@ -2740,6 +2740,20 @@ BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbsuds_v4si, "__builtin_ia32
> BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbuud_v4si, "__builtin_ia32_vpdpbuud128", IX86_BUILTIN_VPDPBUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
> BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT8, CODE_FOR_vpdpbuuds_v4si, "__builtin_ia32_vpdpbuuds128", IX86_BUILTIN_VPDPBUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
>
> +/* AVXVNNIINT16 */
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwusd_v8si, "__builtin_ia32_vpdpwusd256", IX86_BUILTIN_VPDPWUSDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwusds_v8si, "__builtin_ia32_vpdpwusds256", IX86_BUILTIN_VPDPWUSDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwsud_v8si, "__builtin_ia32_vpdpwsud256", IX86_BUILTIN_VPDPWSUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwsuds_v8si, "__builtin_ia32_vpdpwsuds256", IX86_BUILTIN_VPDPWSUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwuud_v8si, "__builtin_ia32_vpdpwuud256", IX86_BUILTIN_VPDPWUUDV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwuuds_v8si, "__builtin_ia32_vpdpwuuds256", IX86_BUILTIN_VPDPWUUDSV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwusd_v4si, "__builtin_ia32_vpdpwusd128", IX86_BUILTIN_VPDPWUSDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwusds_v4si, "__builtin_ia32_vpdpwusds128", IX86_BUILTIN_VPDPWUSDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwsud_v4si, "__builtin_ia32_vpdpwsud128", IX86_BUILTIN_VPDPWSUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwsuds_v4si, "__builtin_ia32_vpdpwsuds128", IX86_BUILTIN_VPDPWSUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwuud_v4si, "__builtin_ia32_vpdpwuud128", IX86_BUILTIN_VPDPWUUDV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
> +BDESC (0, OPTION_MASK_ISA2_AVXVNNIINT16, CODE_FOR_vpdpwuuds_v4si, "__builtin_ia32_vpdpwuuds128", IX86_BUILTIN_VPDPWUUDSV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI)
> +
> /* VPCLMULQDQ */
> BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX512VL, 0, CODE_FOR_vpclmulqdq_v2di, "__builtin_ia32_vpclmulqdq_v2di", IX86_BUILTIN_VPCLMULQDQ2, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT)
> BDESC (OPTION_MASK_ISA_VPCLMULQDQ | OPTION_MASK_ISA_AVX, 0, CODE_FOR_vpclmulqdq_v4di, "__builtin_ia32_vpclmulqdq_v4di", IX86_BUILTIN_VPCLMULQDQ4, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT)
> diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
> index e7bd7cc706c..d3514dd46ac 100644
> --- a/gcc/config/i386/i386-c.cc
> +++ b/gcc/config/i386/i386-c.cc
> @@ -677,6 +677,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
> def_or_undef (parse_in, "__RAOINT__");
> if (isa_flag2 & OPTION_MASK_ISA2_AMX_COMPLEX)
> def_or_undef (parse_in, "__AMX_COMPLEX__");
> + if (isa_flag2 & OPTION_MASK_ISA2_AVXVNNIINT16)
> + def_or_undef (parse_in, "__AVXVNNIINT16__");
> if (TARGET_IAMCU)
> {
> def_or_undef (parse_in, "__iamcu");
> diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
> index 0634c6f5bac..fbf22f7270a 100644
> --- a/gcc/config/i386/i386-isa.def
> +++ b/gcc/config/i386/i386-isa.def
> @@ -117,3 +117,4 @@ DEF_PTA(AMX_FP16)
> DEF_PTA(PREFETCHI)
> DEF_PTA(RAOINT)
> DEF_PTA(AMX_COMPLEX)
> +DEF_PTA(AVXVNNIINT16)
> diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
> index 37cb5a0dcc4..d981666dd87 100644
> --- a/gcc/config/i386/i386-options.cc
> +++ b/gcc/config/i386/i386-options.cc
> @@ -239,7 +239,8 @@ static struct ix86_target_opts isa2_opts[] =
> { "-mamx-fp16", OPTION_MASK_ISA2_AMX_FP16 },
> { "-mprefetchi", OPTION_MASK_ISA2_PREFETCHI },
> { "-mraoint", OPTION_MASK_ISA2_RAOINT },
> - { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX }
> + { "-mamx-complex", OPTION_MASK_ISA2_AMX_COMPLEX },
> + { "-mavxvnniint16", OPTION_MASK_ISA2_AVXVNNIINT16 },
> };
> static struct ix86_target_opts isa_opts[] =
> {
> @@ -1091,6 +1092,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[],
> IX86_ATTR_ISA ("prefetchi", OPT_mprefetchi),
> IX86_ATTR_ISA ("raoint", OPT_mraoint),
> IX86_ATTR_ISA ("amx-complex", OPT_mamx_complex),
> + IX86_ATTR_ISA ("avxvnniint16", OPT_mavxvnniint16),
>
> /* enum options */
> IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_),
> diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
> index d74f6b1f8fc..618d713530f 100644
> --- a/gcc/config/i386/i386.opt
> +++ b/gcc/config/i386/i386.opt
> @@ -1278,3 +1278,8 @@ Enum(lam_type) String(u57) Value(lam_u57)
> mamx-complex
> Target Mask(ISA2_AMX_COMPLEX) Var(ix86_isa_flags2) Save
> Support AMX-COMPLEX built-in functions and code generation.
> +
> +mavxvnniint16
> +Target Mask(ISA2_AVXVNNIINT16) Var(ix86_isa_flags2) Save
> +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2 and
> +AVXVNNIINT16 built-in functions and code generation.
> diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h
> index b220d871942..52dc35d8398 100644
> --- a/gcc/config/i386/immintrin.h
> +++ b/gcc/config/i386/immintrin.h
> @@ -48,6 +48,8 @@
>
> #include <avxvnniint8intrin.h>
>
> +#include <avxvnniint16intrin.h>
> +
> #include <avx2intrin.h>
>
> #include <avx512fintrin.h>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 6bf9c99a2c1..85a5f801e7a 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -204,6 +204,14 @@
> UNSPEC_VPDPBSUDS
> UNSPEC_VPDPBUUD
> UNSPEC_VPDPBUUDS
> +
> + ;; For AVX-VNNI-INT16 support
> + UNSPEC_VPDPWUSD
> + UNSPEC_VPDPWUSDS
> + UNSPEC_VPDPWSUD
> + UNSPEC_VPDPWSUDS
> + UNSPEC_VPDPWUUD
> + UNSPEC_VPDPWUUDS
> ])
>
> (define_c_enum "unspecv" [
> @@ -30209,3 +30217,27 @@
> "vcvtneo<bf16_ph>2ps\t{%1, %0|%0, %1}"
> [(set_attr "prefix" "vex")
> (set_attr "mode" "<sseinsnmode>")])
> +
> +(define_int_iterator VPDPWPROD
> + [UNSPEC_VPDPWUSD
> + UNSPEC_VPDPWUSDS
> + UNSPEC_VPDPWSUD
> + UNSPEC_VPDPWSUDS
> + UNSPEC_VPDPWUUD
> + UNSPEC_VPDPWUUDS])
> +
> +(define_int_attr vpdpwprodtype
> + [(UNSPEC_VPDPWUSD "wusd") (UNSPEC_VPDPWUSDS "wusds")
> + (UNSPEC_VPDPWSUD "wsud") (UNSPEC_VPDPWSUDS "wsuds")
> + (UNSPEC_VPDPWUUD "wuud") (UNSPEC_VPDPWUUDS "wuuds")])
> +
> +(define_insn "vpdp<vpdpwprodtype>_<mode>"
> + [(set (match_operand:VI4_AVX 0 "register_operand" "=x")
> + (unspec:VI4_AVX
> + [(match_operand:VI4_AVX 1 "register_operand" "0")
> + (match_operand:VI4_AVX 2 "register_operand" "x")
> + (match_operand:VI4_AVX 3 "nonimmediate_operand" "xm")]
> + VPDPWPROD))]
> + "TARGET_AVXVNNIINT16"
> + "vpdp<vpdpwprodtype>\t{%3, %2, %0|%0, %2, %3}"
> + [(set_attr "prefix" "vex")])
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 7e4c5541b11..565bf1352e2 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -7163,6 +7163,11 @@ Enable/disable the generation of the RAOINT instructions.
> @itemx no-amx-complex
> Enable/disable the generation of the AMX-COMPLEX instructions.
>
> +@cindex @code{target("avxvnniint16")} function attribute, x86
> +@item avxvnniint16
> +@itemx no-avxvnniint16
> +Enable/disable the generation of the AVXVNNIINT16 instructions.
> +
> @cindex @code{target("cld")} function attribute, x86
> @item cld
> @itemx no-cld
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index cbc1282c274..359887db5fd 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -1433,7 +1433,7 @@ See RS/6000 and PowerPC Options.
> -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk
> -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni
> -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
> --mprefetchi -mraoint -mamx-complex
> +-mprefetchi -mraoint -mamx-complex -mavxvnniint16
> -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
> -minline-stringops-dynamically -mstringop-strategy=@var{alg}
> -mkl -mwidekl
> @@ -33552,8 +33552,10 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
> @need 200
> @opindex mamx-complex
> @itemx -mamx-complex
> +@need 200
> +@opindex mavxvnniint16
> +@itemx -mavxvnniint16
> These switches enable the use of instructions in the MMX, SSE,
> -SSE2, SSE3, SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF,
> AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA,
> AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG,
> WBNOINVD, FMA4, PREFETCHW, RDPID, PREFETCHWT1, RDSEED, SGX, XOP, LWP,
> @@ -33563,8 +33565,8 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16,
> ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE,
> UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16,
> AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT,
> -AMX-COMPLEX or CLDEMOTE extended instruction sets. Each has a corresponding
> -@option{-mno-} option to disable use of these instructions.
> +AMX-COMPLEX, AVXVNNIINT16 or CLDEMOTE extended instruction sets. Each has a
> +corresponding @option{-mno-} option to disable use of these instructions.
>
> These extensions are also available as built-in functions: see
> @ref{x86 Built-in Functions}, for details of the functions enabled and
> diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
> index ffb6eb1a48c..40919b30a62 100644
> --- a/gcc/doc/sourcebuild.texi
> +++ b/gcc/doc/sourcebuild.texi
> @@ -2511,6 +2511,9 @@ Target supports the execution of @code{avxneconvert} instructions.
> @item avxvnniint8
> Target supports the execution of @code{avxvnniint8} instructions.
>
> +@item avxvnniint16
> +Target supports the execution of @code{avxvnniint16} instructions.
> +
> @item amx_tile
> Target supports the execution of @code{amx-tile} instructions.
>
> diff --git a/gcc/testsuite/g++.dg/other/i386-2.C b/gcc/testsuite/g++.dg/other/i386-2.C
> index 6fe07e18fc6..53622df2bb8 100644
> --- a/gcc/testsuite/g++.dg/other/i386-2.C
> +++ b/gcc/testsuite/g++.dg/other/i386-2.C
> @@ -1,5 +1,5 @@
> /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
> -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */
> +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */
>
> /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
> xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
> diff --git a/gcc/testsuite/g++.dg/other/i386-3.C b/gcc/testsuite/g++.dg/other/i386-3.C
> index 55c81677300..3b76cee3af8 100644
> --- a/gcc/testsuite/g++.dg/other/i386-3.C
> +++ b/gcc/testsuite/g++.dg/other/i386-3.C
> @@ -1,5 +1,5 @@
> /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
> -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */
> +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */
>
> /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h,
> xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h,
> diff --git a/gcc/testsuite/gcc.target/i386/avx-check.h b/gcc/testsuite/gcc.target/i386/avx-check.h
> index 666eff50780..3d417ea1ed5 100644
> --- a/gcc/testsuite/gcc.target/i386/avx-check.h
> +++ b/gcc/testsuite/gcc.target/i386/avx-check.h
> @@ -31,6 +31,9 @@ main ()
> #endif
> #ifdef AVXNECONVERT
> && __builtin_cpu_supports ("avxneconvert")
> +#endif
> +#ifdef AVXVNNIINT16
> + && __builtin_cpu_supports ("avxvnniint16")
> #endif
> )
> {
> diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-1.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-1.c
> new file mode 100644
> index 00000000000..6ae57b150fe
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-1.c
> @@ -0,0 +1,43 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavxvnniint16 -O2" } */
> +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwusd\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwusds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwsud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwsuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwuud\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +/* { dg-final { scan-assembler-times "vpdpwuuds\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
> +
> +
> +#include <immintrin.h>
> +
> +volatile __m256i x,y,z;
> +volatile __m128i x_,y_,z_;
> +volatile __mmask8 m;
> +
> +void extern
> +avxvnniint16_test (void)
> +{
> + x = _mm256_dpwusd_avx_epi32 (x, y, z);
> + x_ = _mm_dpwusd_avx_epi32 (x_, y_, z_);
> +
> + x = _mm256_dpwusds_avx_epi32 (x, y, z);
> + x_ = _mm_dpwusds_avx_epi32 (x_, y_, z_);
> +
> + x = _mm256_dpwsud_avx_epi32 (x, y, z);
> + x_ = _mm_dpwsud_avx_epi32 (x_, y_, z_);
> +
> + x = _mm256_dpwsuds_avx_epi32 (x, y, z);
> + x_ = _mm_dpwsuds_avx_epi32 (x_, y_, z_);
> +
> + x = _mm256_dpwuud_avx_epi32 (x, y, z);
> + x_ = _mm_dpwuud_avx_epi32 (x_, y_, z_);
> +
> + x = _mm256_dpwuuds_avx_epi32 (x, y, z);
> + x_ = _mm_dpwuuds_avx_epi32 (x_, y_, z_);
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsud-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsud-2.c
> new file mode 100644
> index 00000000000..bc57a8a8078
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsud-2.c
> @@ -0,0 +1,71 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mavxvnniint16" } */
> +/* { dg-require-effective-target avxvnniint16 } */
> +#define AVXVNNIINT16
> +#ifndef CHECK
> +#define CHECK "avx-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST avx_test
> +#endif
> +
> +#include CHECK
> +
> +static void
> +CALC (int *r, int *dst, short *s1, unsigned short *s2, int size)
> +{
> + int tempres[16];
> + for (int i = 0; i < size; i++)
> + tempres[i] = (int) s1[i] * (unsigned int) s2[i];
> + for (int i = 0; i < size / 2; i++)
> + {
> + int test = (int) dst[i] + tempres[i * 2] + tempres[i * 2 + 1];
> + r[i] = test;
> + }
> +}
> +
> +void
> +TEST (void)
> +{
> + int i;
> + union256i_d res_256;
> + union256i_w src1_256;
> + union256i_uw src2_256;
> + int res_ref_256[8];
> +
> + for (i = 0; i < 16; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_256.a[i] = 10 + 3 * i + sign;
> + src2_256.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 8; i++)
> + res_256.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16);
> + res_256.x = _mm256_dpwsud_avx_epi32 (res_256.x, src1_256.x, src2_256.x);
> + if (check_union256i_d (res_256, res_ref_256))
> + abort ();
> +
> + union128i_d res_128;
> + union128i_w src1_128;
> + union128i_uw src2_128;
> + int res_ref_128[4];
> +
> + for (i = 0; i < 8; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_128.a[i] = 10 + 3 * i * i + sign;
> + src2_128.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 4; i++)
> + res_128.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8);
> + res_128.x = _mm_dpwsud_avx_epi32 (res_128.x, src1_128.x, src2_128.x);
> + if (check_union128i_d (res_128, res_ref_128))
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsuds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsuds-2.c
> new file mode 100644
> index 00000000000..fbcf46a4827
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwsuds-2.c
> @@ -0,0 +1,72 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mavxvnniint16" } */
> +/* { dg-require-effective-target avxvnniint16 } */
> +#define AVXVNNIINT16
> +#ifndef CHECK
> +#define CHECK "avx-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST avx_test
> +#endif
> +
> +#include CHECK
> +
> +static void
> +CALC (int *r, int *dst, short *s1, unsigned short *s2, int size)
> +{
> + int tempres[16];
> + for (int i = 0; i < size; i++)
> + tempres[i] = (int) s1[i] * (unsigned int) s2[i];
> + for (int i = 0; i < size / 2; i++)
> + {
> + long long test = (long long) dst[i] + tempres[i * 2] + tempres[i * 2 + 1];
> + r[i] = test > 0x7FFFFFFF ? 0x7FFFFFFF :
> + (test < 0xffffffff80000000LL ? 0x80000000 : test);
> + }
> +}
> +
> +void
> +TEST (void)
> +{
> + int i;
> + union256i_d res_256;
> + union256i_w src1_256;
> + union256i_uw src2_256;
> + int res_ref_256[8];
> +
> + for (i = 0; i < 16; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_256.a[i] = 10 + 3 * i + sign;
> + src2_256.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 8; i++)
> + res_256.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16);
> + res_256.x = _mm256_dpwsuds_avx_epi32 (res_256.x, src1_256.x, src2_256.x);
> + if (check_union256i_d (res_256, res_ref_256))
> + abort ();
> +
> + union128i_d res_128;
> + union128i_w src1_128;
> + union128i_uw src2_128;
> + int res_ref_128[4];
> +
> + for (i = 0; i < 8; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_128.a[i] = 10 + 3 * i * i + sign;
> + src2_128.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 4; i++)
> + res_128.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8);
> + res_128.x = _mm_dpwsuds_avx_epi32 (res_128.x, src1_128.x, src2_128.x);
> + if (check_union128i_d (res_128, res_ref_128))
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusd-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusd-2.c
> new file mode 100644
> index 00000000000..54cf271acbf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusd-2.c
> @@ -0,0 +1,71 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mavxvnniint16" } */
> +/* { dg-require-effective-target avxvnniint16 } */
> +#define AVXVNNIINT16
> +#ifndef CHECK
> +#define CHECK "avx-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST avx_test
> +#endif
> +
> +#include CHECK
> +
> +static void
> +CALC (int *r, int *dst, unsigned short *s1, short *s2, int size)
> +{
> + int tempres[16];
> + for (int i = 0; i < size; i++)
> + tempres[i] = (unsigned int) s1[i] * (int) s2[i];
> + for (int i = 0; i < size / 2; i++)
> + {
> + int test = (int) dst[i] + tempres[i * 2] + tempres[i * 2 + 1];
> + r[i] = test;
> + }
> +}
> +
> +void
> +TEST (void)
> +{
> + int i;
> + union256i_d res_256;
> + union256i_uw src1_256;
> + union256i_w src2_256;
> + int res_ref_256[8];
> +
> + for (i = 0; i < 16; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_256.a[i] = 10 + 3 * i + sign;
> + src2_256.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 8; i++)
> + res_256.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16);
> + res_256.x = _mm256_dpwusd_avx_epi32 (res_256.x, src1_256.x, src2_256.x);
> + if (check_union256i_d (res_256, res_ref_256))
> + abort ();
> +
> + union128i_d res_128;
> + union128i_uw src1_128;
> + union128i_w src2_128;
> + int res_ref_128[4];
> +
> + for (i = 0; i < 8; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_128.a[i] = 10 + 3 * i * i + sign;
> + src2_128.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 4; i++)
> + res_128.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8);
> + res_128.x = _mm_dpwusd_avx_epi32 (res_128.x, src1_128.x, src2_128.x);
> + if (check_union128i_d (res_128, res_ref_128))
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusds-2.c
> new file mode 100644
> index 00000000000..ed9594c708b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwusds-2.c
> @@ -0,0 +1,72 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mavxvnniint16" } */
> +/* { dg-require-effective-target avxvnniint16 } */
> +#define AVXVNNIINT16
> +#ifndef CHECK
> +#define CHECK "avx-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST avx_test
> +#endif
> +
> +#include CHECK
> +
> +static void
> +CALC (int *r, int *dst, unsigned short *s1, short *s2, int size)
> +{
> + int tempres[16];
> + for (int i = 0; i < size; i++)
> + tempres[i] = (unsigned int) s1[i] * (int) s2[i];
> + for (int i = 0; i < size / 2; i++)
> + {
> + long long test = (long long) dst[i] + tempres[i * 2] + tempres[i * 2 + 1];
> + r[i] = test > 0x7FFFFFFF ? 0x7FFFFFFF :
> + (test < 0xffffffff80000000LL ? 0x80000000 : test);
> + }
> +}
> +
> +void
> +TEST (void)
> +{
> + int i;
> + union256i_d res_256;
> + union256i_uw src1_256;
> + union256i_w src2_256;
> + int res_ref_256[8];
> +
> + for (i = 0; i < 16; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_256.a[i] = 10 + 3 * i + sign;
> + src2_256.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 8; i++)
> + res_256.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16);
> + res_256.x = _mm256_dpwusds_avx_epi32 (res_256.x, src1_256.x, src2_256.x);
> + if (check_union256i_d (res_256, res_ref_256))
> + abort ();
> +
> + union128i_d res_128;
> + union128i_uw src1_128;
> + union128i_w src2_128;
> + int res_ref_128[4];
> +
> + for (i = 0; i < 8; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_128.a[i] = 10 + 3 * i * i + sign;
> + src2_128.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 4; i++)
> + res_128.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8);
> + res_128.x = _mm_dpwusds_avx_epi32 (res_128.x, src1_128.x, src2_128.x);
> + if (check_union128i_d (res_128, res_ref_128))
> + abort();
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuud-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuud-2.c
> new file mode 100644
> index 00000000000..8bdc4330ef0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuud-2.c
> @@ -0,0 +1,71 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mavxvnniint16" } */
> +/* { dg-require-effective-target avxvnniint16 } */
> +#define AVXVNNIINT16
> +#ifndef CHECK
> +#define CHECK "avx-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST avx_test
> +#endif
> +
> +#include CHECK
> +
> +static void
> +CALC (unsigned int *r, unsigned int *dst, unsigned short *s1, unsigned short *s2, int size)
> +{
> + unsigned int tempres[16];
> + for (int i = 0; i < size; i++)
> + tempres[i] = (unsigned int) s1[i] * (unsigned int) s2[i];
> + for (int i = 0; i < size / 2; i++)
> + {
> + unsigned int test = (unsigned) dst[i] + tempres[i * 2] + tempres[i * 2 + 1];
> + r[i] = test;
> + }
> +}
> +
> +void
> +TEST (void)
> +{
> + int i;
> + union256i_ud res_256;
> + union256i_uw src1_256;
> + union256i_uw src2_256;
> + unsigned int res_ref_256[8];
> +
> + for (i = 0; i < 16; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_256.a[i] = 10 + 3 * i + sign;
> + src2_256.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 8; i++)
> + res_256.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16);
> + res_256.x = _mm256_dpwuud_avx_epi32 (res_256.x, src1_256.x, src2_256.x);
> + if (check_union256i_ud (res_256, res_ref_256))
> + abort ();
> +
> + union128i_ud res_128;
> + union128i_uw src2_128;
> + union128i_uw src1_128;
> + unsigned int res_ref_128[4];
> +
> + for (i = 0; i < 8; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_128.a[i] = 10 + 3 * i * i + sign;
> + src2_128.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 4; i++)
> + res_128.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8);
> + res_128.x = _mm_dpwuud_avx_epi32 (res_128.x, src1_128.x, src2_128.x);
> + if (check_union128i_ud (res_128, res_ref_128))
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuuds-2.c b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuuds-2.c
> new file mode 100644
> index 00000000000..32204122f1c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avxvnniint16-vpdpwuuds-2.c
> @@ -0,0 +1,71 @@
> +/* { dg-do run } */
> +/* { dg-options "-O2 -mavxvnniint16" } */
> +/* { dg-require-effective-target avxvnniint16 } */
> +#define AVXVNNIINT16
> +#ifndef CHECK
> +#define CHECK "avx-check.h"
> +#endif
> +
> +#ifndef TEST
> +#define TEST avx_test
> +#endif
> +
> +#include CHECK
> +
> +static void
> +CALC (unsigned int *r, unsigned int *dst, unsigned short *s1, unsigned short *s2, int size)
> +{
> + unsigned int tempres[16];
> + for (int i = 0; i < size; i++)
> + tempres[i] = (unsigned int) s1[i] * (unsigned int) s2[i];
> + for (int i = 0; i < size / 2; i++)
> + {
> + unsigned int test = (unsigned) dst[i] + tempres[i * 2] + tempres[i * 2 + 1];
> + r[i] = test > 0xFFFFFFFF ? 0xFFFFFFFF : test;
> + }
> +}
> +
> +void
> +TEST (void)
> +{
> + int i;
> + union256i_ud res_256;
> + union256i_uw src1_256;
> + union256i_uw src2_256;
> + unsigned int res_ref_256[8];
> +
> + for (i = 0; i < 16; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_256.a[i] = 10 + 3 * i + sign;
> + src2_256.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 8; i++)
> + res_256.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_256, res_256.a, src1_256.a, src2_256.a, 16);
> + res_256.x = _mm256_dpwuuds_avx_epi32 (res_256.x, src1_256.x, src2_256.x);
> + if (check_union256i_ud (res_256, res_ref_256))
> + abort ();
> +
> + union128i_ud res_128;
> + union128i_uw src2_128;
> + union128i_uw src1_128;
> + unsigned int res_ref_128[4];
> +
> + for (i = 0; i < 8; i++)
> + {
> + int sign = i % 2 ? 1 : -1;
> + src1_128.a[i] = 10 + 3 * i * i + sign;
> + src2_128.a[i] = sign * 10 * i * i;
> + }
> +
> + for (i = 0; i < 4; i++)
> + res_128.a[i] = 0x7fffffff;
> +
> + CALC (res_ref_128, res_128.a, src1_128.a, src2_128.a, 8);
> + res_128.x = _mm_dpwuuds_avx_epi32 (res_128.x, src1_128.x, src2_128.x);
> + if (check_union128i_ud (res_128, res_ref_128))
> + abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
> index f466962c36c..bba0fa37efd 100644
> --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
> +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
> @@ -88,6 +88,7 @@ extern void test_amx_fp16 (void) __attribute__((__target__("amx-fp16")));
> extern void test_prefetchi (void) __attribute__((__target__("prefetchi")));
> extern void test_raoint (void) __attribute__((__target__("raoint")));
> extern void test_amx_complex (void) __attribute__((__target__("amx-complex")));
> +extern void test_avxvnniint16 (void) __attribute__((__target__("avxvnniint16")));
>
> extern void test_no_sgx (void) __attribute__((__target__("no-sgx")));
> extern void test_no_avx5124fmaps(void) __attribute__((__target__("no-avx5124fmaps")));
> @@ -177,6 +178,7 @@ extern void test_no_amx_fp16 (void) __attribute__((__target__("no-amx-fp16")));
> extern void test_no_prefetchi (void) __attribute__((__target__("no-prefetchi")));
> extern void test_no_raoint (void) __attribute__((__target__("no-raoint")));
> extern void test_no_amx_complex (void) __attribute__((__target__("no-amx-complex")));
> +extern void test_no_avxvnniint16 (void) __attribute__((__target__("no-avxvnniint16")));
>
> extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona")));
> extern void test_arch_core2 (void) __attribute__((__target__("arch=core2")));
> diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c b/gcc/testsuite/gcc.target/i386/sse-12.c
> index ae4ffd1975f..2b7d78c51d3 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-12.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-12.c
> @@ -3,7 +3,7 @@
> popcntintrin.h gfniintrin.h and mm_malloc.h are usable
> with -O -std=c89 -pedantic-errors. */
> /* { dg-do compile } */
> -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex" } */
> +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16" } */
>
> #include <x86intrin.h>
>
> diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c
> index f046a68ddbb..33693484d2a 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-13.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-13.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex" } */
> +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16" } */
> /* { dg-add-options bind_pic_locally } */
>
> #include <mm_malloc.h>
> diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c b/gcc/testsuite/gcc.target/i386/sse-14.c
> index 05322f7e914..51c2946b25a 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-14.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-14.c
> @@ -1,5 +1,5 @@
> /* { dg-do compile } */
> -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex" } */
> +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mraoint -mamx-complex -mavxvnniint16" } */
> /* { dg-add-options bind_pic_locally } */
>
> #include <mm_malloc.h>
> diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c b/gcc/testsuite/gcc.target/i386/sse-22.c
> index 53c38b70241..4982fde2a76 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-22.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-22.c
> @@ -103,7 +103,7 @@
>
>
> #ifndef DIFFERENT_PRAGMAS
> -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex")
> +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16")
> #endif
>
> /* Following intrinsics require immediate arguments. They
> @@ -220,7 +220,7 @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
>
> /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */
> #ifdef DIFFERENT_PRAGMAS
> -#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex")
> +#pragma GCC target ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,raoint,amx-complex,avxvnniint16")
> #endif
> #include <immintrin.h>
> test_1 (_cvtss_sh, unsigned short, float, 1)
> diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c
> index 50bf85a3392..7e9c9f2ca2b 100644
> --- a/gcc/testsuite/gcc.target/i386/sse-23.c
> +++ b/gcc/testsuite/gcc.target/i386/sse-23.c
> @@ -847,6 +847,6 @@
> #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, C, 1)
> #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, B, C, 1)
>
> -#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex")
> +#pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi,raoint,amx-complex,avxvnniint16")
>
> #include <x86intrin.h>
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index 33482b2fa9a..60de239f1ce 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -9856,6 +9856,18 @@ proc check_effective_target_amx_complex { } {
> } "-mamx-complex" ]
> }
>
> +# Return 1 if avxvnniint16 instructions can be compiled.
> +proc check_effective_target_avxvnniint16 { } {
> + return [check_no_compiler_messages avxvnniint16 object {
> + typedef int __v8si __attribute__ ((__vector_size__ (32)));
> + __v8si
> + _mm256_dpwsud_avx_epi32 (__v8si __A, __v8si __B, __v8si __C)
> + {
> + return __builtin_ia32_vpdpwsud256 (__A, __B, __C);
> + }
> + } "-O0 -mavxvnniint16" ]
> +}
> +
> # Return 1 if sse instructions can be compiled.
> proc check_effective_target_sse { } {
> return [check_no_compiler_messages sse object {
> --
> 2.31.1
>
--
BR,
Hongtao
next prev parent reply other threads:[~2023-07-17 1:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-13 6:03 [PATCH 0/4] Support Intel Arrow Lake/Lunar Lake ISAs Haochen Jiang
2023-07-13 6:03 ` [PATCH 1/4] Support Intel AVX-VNNI-INT16 Haochen Jiang
2023-07-17 1:39 ` Hongtao Liu [this message]
2023-07-13 6:03 ` [PATCH 2/4] Support Intel SM3 Haochen Jiang
2023-07-17 1:39 ` Hongtao Liu
2023-07-13 6:03 ` [PATCH 3/4] Support Intel SHA512 Haochen Jiang
2023-07-17 1:40 ` Hongtao Liu
2023-07-13 6:03 ` [PATCH 4/4] Support Intel SM4 Haochen Jiang
2023-07-17 1:40 ` Hongtao Liu
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