* [PATCH 1/9] LoongArch: Introduce loongarch32 target
@ 2023-08-06 12:49 Jiajie Chen
2023-08-06 12:49 ` [PATCH 2/9] LoongArch: Fix default ISA setting Jiajie Chen
` (8 more replies)
0 siblings, 9 replies; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:49 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
Introduce loongarch32 target and ilp32 abi variants. The ilp32d abi
variant is selected as the default abi of loongarch32 target.
contrib/ChangeLog:
* config-list.mk: Add loongarch32-linux-gnu*.
gcc/ChangeLog:
* config.gcc: Add target triple loongarch32-*-*-* and
corresponding abi ilp32f, ilp32d and ilp32s.
* config/loongarch/genopts/loongarch-strings: Add strings for
loongarch32 and ilp32 abi variants.
* config/loongarch/genopts/loongarch.opt.in: Add
-march=loongarch32 and -mabi=ilp32d/ilp32f/ilp32s.
* config/loongarch/gnu-user.h: Add ilp32 abi variants to spec.
* config/loongarch/linux.h: Add ABI_LIBDIR for ilp32 abi
variants.
* config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins):
Add builtin definitions for loongarch32 target.
* config/loongarch/loongarch-def.c: Add loongarch32 and ilp32
definitions.
* config/loongarch/loongarch-def.h: Add loongarch32 and ilp32
definitions.
* config/loongarch/loongarch-driver.h: Add ilp32 abi variants to
spec.
* config/loongarch/loongarch-opts.cc: Handle ilp32 abi variants.
* config/loongarch/loongarch-opts.h: Add loongarch32 case to
macros.
* config/loongarch/loongarch-str.h: Add loongarch32 and ilp32
strings.
* config/loongarch/loongarch.cc: Disable -fpcc-struct-return for
ilp32.
* config/loongarch/loongarch.opt: Add -march=loongarch32 and
-mabi=ilp32d/ilp32f/ilp32s.
* config/loongarch/t-linux: Add ilp32 abi variants to multilib.
---
contrib/config-list.mk | 1 +
gcc/config.gcc | 61 ++++++++++++++++---
.../loongarch/genopts/loongarch-strings | 5 ++
gcc/config/loongarch/genopts/loongarch.opt.in | 12 ++++
gcc/config/loongarch/gnu-user.h | 3 +
gcc/config/loongarch/linux.h | 8 ++-
gcc/config/loongarch/loongarch-c.cc | 12 ++++
gcc/config/loongarch/loongarch-def.c | 33 ++++++++++
gcc/config/loongarch/loongarch-def.h | 25 +++++---
gcc/config/loongarch/loongarch-driver.h | 4 ++
gcc/config/loongarch/loongarch-opts.cc | 22 ++++++-
gcc/config/loongarch/loongarch-opts.h | 20 ++++--
gcc/config/loongarch/loongarch-str.h | 5 ++
gcc/config/loongarch/loongarch.cc | 2 +-
gcc/config/loongarch/loongarch.opt | 12 ++++
gcc/config/loongarch/t-linux | 16 ++++-
16 files changed, 210 insertions(+), 31 deletions(-)
diff --git a/contrib/config-list.mk b/contrib/config-list.mk
index e570b13c71b..3c00ce5410a 100644
--- a/contrib/config-list.mk
+++ b/contrib/config-list.mk
@@ -57,6 +57,7 @@ LIST = aarch64-elf aarch64-freebsd13 aarch64-linux-gnu aarch64-rtems \
i686-cygwinOPT-enable-threads=yes i686-mingw32crt ia64-elf \
ia64-linux ia64-hpux ia64-hp-vms iq2000-elf lm32-elf \
lm32-rtems lm32-uclinux \
+ loongarch32-linux-gnuf64 loongarch32-linux-gnuf32 loongarch32-linux-gnusf \
loongarch64-linux-gnuf64 loongarch64-linux-gnuf32 loongarch64-linux-gnusf \
m32c-elf m32r-elf m32rle-elf \
m68k-elf m68k-netbsdelf \
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 415e0e1ebc5..45e69b24b44 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4901,10 +4901,24 @@ case "${target}" in
arch_pattern arch_default \
fpu_pattern fpu_default \
tune_pattern tune_default \
- triplet_os triplet_abi
+ triplet_os triplet_abi \
+ triplet_cpu
# Infer ABI from the triplet.
case ${target} in
+ loongarch32-*-*-*f64)
+ abi_pattern="ilp32d"
+ ;;
+ loongarch32-*-*-*f32)
+ abi_pattern="ilp32f"
+ ;;
+ loongarch32-*-*-*sf)
+ abi_pattern="ilp32s"
+ ;;
+ loongarch32-*-*-*)
+ abi_pattern="ilp32[dfs]"
+ abi_default="ilp32d"
+ ;;
loongarch64-*-*-*f64)
abi_pattern="lp64d"
;;
@@ -4939,7 +4953,7 @@ case "${target}" in
# Perform initial sanity checks on --with-* options.
case ${with_arch} in
- "" | loongarch64 | la464) ;; # OK, append here.
+ "" | loongarch32 | loongarch64 | la464) ;; # OK, append here.
native)
if test x${host} != x${target}; then
echo "--with-arch=native is illegal for cross-compiler." 1>&2
@@ -4958,7 +4972,7 @@ case "${target}" in
esac
case ${with_abi} in
- "" | lp64d | lp64f | lp64s) ;; # OK, append here.
+ "" | ilp32d | ilp32f | ilp32s | lp64d | lp64f | lp64s) ;; # OK, append here.
*)
echo "Unsupported ABI given in --with-abi=$with_abi" 1>&2
exit 1
@@ -5007,12 +5021,21 @@ case "${target}" in
;;
esac
+ case ${target} in
+ loongarch32-*-*-*)
+ triplet_cpu="loongarch32"
+ ;;
+ loongarch64-*-*-*)
+ triplet_cpu="loongarch64"
+ ;;
+ esac
+
case ${with_abi} in
- "lp64d") triplet_abi="";;
- "lp64f") triplet_abi="f32";;
- "lp64s") triplet_abi="sf";;
+ "ilp32d" | "lp64d") triplet_abi="";;
+ "ilp32f" | "lp64f") triplet_abi="f32";;
+ "ilp32s" | "lp64s") triplet_abi="sf";;
esac
- la_canonical_triplet="loongarch64-${triplet_os}${triplet_abi}"
+ la_canonical_triplet="${triplet_cpu}-${triplet_os}${triplet_abi}"
# Set default value for with_abiext (internal)
case ${with_abiext} in
@@ -5038,6 +5061,12 @@ case "${target}" in
# Infer ISA-related default options from the ABI: pass 1
case ${with_abi}/${with_abiext} in
+ ilp32*/base)
+ # architectures that support ilp32* ABI
+ arch_pattern="native|loongarch32"
+ # default architecture for ilp32* ABI
+ arch_default="loongarch32"
+ ;;
lp64*/base)
# architectures that support lp64* ABI
arch_pattern="native|loongarch64|la464"
@@ -5052,14 +5081,14 @@ case "${target}" in
# Infer ISA-related default options from the ABI: pass 2
case ${with_abi}/${with_abiext} in
- lp64d/base)
+ ilp32d/base | lp64d/base)
fpu_pattern="64"
;;
- lp64f/base)
+ ilp32f/base | lp64f/base)
fpu_pattern="32|64"
fpu_default="32"
;;
- lp64s/base)
+ ilp32s/base | lp64s/base)
fpu_pattern="none|32|64"
fpu_default="none"
;;
@@ -5118,6 +5147,10 @@ case "${target}" in
tune_pattern="*"
tune_default="native"
;;
+ loongarch32)
+ tune_pattern="loongarch32"
+ tune_default="loongarch32"
+ ;;
loongarch64)
tune_pattern="loongarch64|la464"
tune_default="la464"
@@ -5187,6 +5220,9 @@ case "${target}" in
1)
# Component 1: Base ABI type
case ${component} in
+ ilp32d) elem_tmp="ABI_BASE_ILP32D,";;
+ ilp32f) elem_tmp="ABI_BASE_ILP32F,";;
+ ilp32s) elem_tmp="ABI_BASE_ILP32S,";;
lp64d) elem_tmp="ABI_BASE_LP64D,";;
lp64f) elem_tmp="ABI_BASE_LP64F,";;
lp64s) elem_tmp="ABI_BASE_LP64S,";;
@@ -5741,17 +5777,22 @@ case ${target} in
# See macro definitions from loongarch-opts.h and loongarch-cpu.h.
case ${with_arch} in
native) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_NATIVE" ;;
+ loongarch32) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LOONGARCH32" ;;
la464) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LA464" ;;
loongarch64) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LOONGARCH64" ;;
esac
case ${with_tune} in
native) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_NATIVE" ;;
+ loongarch32) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LOONGARCH32" ;;
la464) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LA464" ;;
loongarch64) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LOONGARCH64" ;;
esac
case ${with_abi} in
+ ilp32d) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32D" ;;
+ ilp32f) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32F" ;;
+ ilp32s) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32S" ;;
lp64d) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64D" ;;
lp64f) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64F" ;;
lp64s) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64S" ;;
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index a40998ead97..1e20b70dde2 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -23,10 +23,12 @@ OPTSTR_ARCH arch
OPTSTR_TUNE tune
STR_CPU_NATIVE native
+STR_CPU_LOONGARCH32 loongarch32
STR_CPU_LOONGARCH64 loongarch64
STR_CPU_LA464 la464
# Base architecture
+STR_ISA_BASE_LA32V100 la32
STR_ISA_BASE_LA64V100 la64
# -mfpu
@@ -42,6 +44,9 @@ OPTSTR_DOUBLE_FLOAT double-float
# -mabi=
OPTSTR_ABI_BASE abi
+STR_ABI_BASE_ILP32D ilp32d
+STR_ABI_BASE_ILP32F ilp32f
+STR_ABI_BASE_ILP32S ilp32s
STR_ABI_BASE_LP64D lp64d
STR_ABI_BASE_LP64F lp64f
STR_ABI_BASE_LP64S lp64s
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 4b9b4ac273e..47f77345890 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -85,6 +85,9 @@ LoongArch CPU types:
EnumValue
Enum(cpu_type) String(@@STR_CPU_NATIVE@@) Value(CPU_NATIVE)
+EnumValue
+Enum(cpu_type) String(@@STR_CPU_LOONGARCH32@@) Value(CPU_LOONGARCH32)
+
EnumValue
Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64)
@@ -108,6 +111,15 @@ Enum
Name(abi_base) Type(int)
Base ABI types for LoongArch:
+EnumValue
+Enum(abi_base) String(@@STR_ABI_BASE_ILP32D@@) Value(ABI_BASE_ILP32D)
+
+EnumValue
+Enum(abi_base) String(@@STR_ABI_BASE_ILP32F@@) Value(ABI_BASE_ILP32F)
+
+EnumValue
+Enum(abi_base) String(@@STR_ABI_BASE_ILP32S@@) Value(ABI_BASE_ILP32S)
+
EnumValue
Enum(abi_base) String(@@STR_ABI_BASE_LP64D@@) Value(ABI_BASE_LP64D)
diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h
index fa1a5211419..bf6d3a4fe98 100644
--- a/gcc/config/loongarch/gnu-user.h
+++ b/gcc/config/loongarch/gnu-user.h
@@ -34,6 +34,9 @@ along with GCC; see the file COPYING3. If not see
"/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1"
#define MUSL_ABI_SPEC \
+ "%{mabi=ilp32d:-ilp32d}" \
+ "%{mabi=ilp32f:-ilp32f}" \
+ "%{mabi=ilp32s:-ilp32s}" \
"%{mabi=lp64d:-lp64d}" \
"%{mabi=lp64f:-lp64f}" \
"%{mabi=lp64s:-lp64s}"
diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
index 9059d244190..45aa3531cd3 100644
--- a/gcc/config/loongarch/linux.h
+++ b/gcc/config/loongarch/linux.h
@@ -23,7 +23,13 @@ along with GCC; see the file COPYING3. If not see
#if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
- #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
+ #if DEFAULT_ABI_BASE == ABI_BASE_ILP32D
+ #define ABI_LIBDIR "lib32"
+ #elif DEFAULT_ABI_BASE == ABI_BASE_ILP32F
+ #define ABI_LIBDIR "lib32/f32"
+ #elif DEFAULT_ABI_BASE == ABI_BASE_ILP32S
+ #define ABI_LIBDIR "lib32/sf"
+ #elif DEFAULT_ABI_BASE == ABI_BASE_LP64D
#define ABI_LIBDIR "lib64"
#elif DEFAULT_ABI_BASE == ABI_BASE_LP64F
#define ABI_LIBDIR "lib64/f32"
diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc
index 67911b78f28..e3783a325d7 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -65,12 +65,24 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_TUNE", LARCH_ACTUAL_TUNE);
/* Base architecture / ABI. */
+ if (TARGET_32BIT)
+ {
+ builtin_define ("__loongarch_grlen=32");
+ builtin_define ("__loongarch32");
+ }
if (TARGET_64BIT)
{
builtin_define ("__loongarch_grlen=64");
builtin_define ("__loongarch64");
}
+ if (TARGET_ABI_ILP32)
+ {
+ builtin_define ("_ABILP32=3");
+ builtin_define ("_LOONGARCH_SIM=_ABILP32");
+ builtin_define ("__loongarch_ilp32");
+ }
+
if (TARGET_ABI_LP64)
{
builtin_define ("_ABILP64=3");
diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
index 6729c857f7c..5ae8bd24c9f 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -40,12 +40,17 @@ along with GCC; see the file COPYING3. If not see
const char*
loongarch_cpu_strings[N_TUNE_TYPES] = {
[CPU_NATIVE] = STR_CPU_NATIVE,
+ [CPU_LOONGARCH32] = STR_CPU_LOONGARCH32,
[CPU_LOONGARCH64] = STR_CPU_LOONGARCH64,
[CPU_LA464] = STR_CPU_LA464,
};
struct loongarch_isa
loongarch_cpu_default_isa[N_ARCH_TYPES] = {
+ [CPU_LOONGARCH32] = {
+ .base = ISA_BASE_LA32V100,
+ .fpu = ISA_EXT_FPU32,
+ },
[CPU_LOONGARCH64] = {
.base = ISA_BASE_LA64V100,
.fpu = ISA_EXT_FPU64,
@@ -58,6 +63,12 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = {
struct loongarch_cache
loongarch_cpu_cache[N_TUNE_TYPES] = {
+ [CPU_LOONGARCH32] = {
+ .l1d_line_size = 64,
+ .l1d_size = 64,
+ .l2d_size = 256,
+ .simultaneous_prefetches = 4,
+ },
[CPU_LOONGARCH64] = {
.l1d_line_size = 64,
.l1d_size = 64,
@@ -74,6 +85,10 @@ loongarch_cpu_cache[N_TUNE_TYPES] = {
struct loongarch_align
loongarch_cpu_align[N_TUNE_TYPES] = {
+ [CPU_LOONGARCH32] = {
+ .function = "32",
+ .label = "16",
+ },
[CPU_LOONGARCH64] = {
.function = "32",
.label = "16",
@@ -94,6 +109,9 @@ loongarch_cpu_rtx_cost_data[N_TUNE_TYPES] = {
[CPU_NATIVE] = {
DEFAULT_COSTS
},
+ [CPU_LOONGARCH32] = {
+ DEFAULT_COSTS
+ },
[CPU_LOONGARCH64] = {
DEFAULT_COSTS
},
@@ -121,6 +139,7 @@ loongarch_rtx_cost_optimize_size = {
int
loongarch_cpu_issue_rate[N_TUNE_TYPES] = {
[CPU_NATIVE] = 4,
+ [CPU_LOONGARCH32] = 4,
[CPU_LOONGARCH64] = 4,
[CPU_LA464] = 4,
};
@@ -128,6 +147,7 @@ loongarch_cpu_issue_rate[N_TUNE_TYPES] = {
int
loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
[CPU_NATIVE] = 4,
+ [CPU_LOONGARCH32] = 4,
[CPU_LOONGARCH64] = 4,
[CPU_LA464] = 4,
};
@@ -139,6 +159,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
const char*
loongarch_isa_base_strings[N_ISA_BASE_TYPES] = {
+ [ISA_BASE_LA32V100] = STR_ISA_BASE_LA32V100,
[ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100,
};
@@ -151,6 +172,9 @@ loongarch_isa_ext_strings[N_ISA_EXT_TYPES] = {
const char*
loongarch_abi_base_strings[N_ABI_BASE_TYPES] = {
+ [ABI_BASE_ILP32D] = STR_ABI_BASE_ILP32D,
+ [ABI_BASE_ILP32F] = STR_ABI_BASE_ILP32F,
+ [ABI_BASE_ILP32S] = STR_ABI_BASE_ILP32S,
[ABI_BASE_LP64D] = STR_ABI_BASE_LP64D,
[ABI_BASE_LP64F] = STR_ABI_BASE_LP64F,
[ABI_BASE_LP64S] = STR_ABI_BASE_LP64S,
@@ -182,6 +206,15 @@ loongarch_switch_strings[] = {
/* ABI-related definitions. */
const struct loongarch_isa
abi_minimal_isa[N_ABI_BASE_TYPES][N_ABI_EXT_TYPES] = {
+ [ABI_BASE_ILP32D] = {
+ [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_FPU64},
+ },
+ [ABI_BASE_ILP32F] = {
+ [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_FPU32},
+ },
+ [ABI_BASE_ILP32S] = {
+ [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_NOFPU},
+ },
[ABI_BASE_LP64D] = {
[ABI_EXT_BASE] = {.base = ISA_BASE_LA64V100, .fpu = ISA_EXT_FPU64},
},
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index fb8bb88eb52..6c4b9fa3385 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -54,8 +54,9 @@ extern "C" {
/* enum isa_base */
extern const char* loongarch_isa_base_strings[];
-#define ISA_BASE_LA64V100 0
-#define N_ISA_BASE_TYPES 1
+#define ISA_BASE_LA32V100 0
+#define ISA_BASE_LA64V100 1
+#define N_ISA_BASE_TYPES 2
/* enum isa_ext_* */
extern const char* loongarch_isa_ext_strings[];
@@ -67,10 +68,13 @@ extern const char* loongarch_isa_ext_strings[];
/* enum abi_base */
extern const char* loongarch_abi_base_strings[];
-#define ABI_BASE_LP64D 0
-#define ABI_BASE_LP64F 1
-#define ABI_BASE_LP64S 2
-#define N_ABI_BASE_TYPES 3
+#define ABI_BASE_ILP32D 0
+#define ABI_BASE_ILP32F 1
+#define ABI_BASE_ILP32S 2
+#define ABI_BASE_LP64D 3
+#define ABI_BASE_LP64F 4
+#define ABI_BASE_LP64S 5
+#define N_ABI_BASE_TYPES 6
/* enum abi_ext */
extern const char* loongarch_abi_ext_strings[];
@@ -132,10 +136,11 @@ struct loongarch_target
/* CPU properties. */
/* index */
#define CPU_NATIVE 0
-#define CPU_LOONGARCH64 1
-#define CPU_LA464 2
-#define N_ARCH_TYPES 3
-#define N_TUNE_TYPES 3
+#define CPU_LOONGARCH32 1
+#define CPU_LOONGARCH64 2
+#define CPU_LA464 3
+#define N_ARCH_TYPES 4
+#define N_TUNE_TYPES 4
/* parallel tables. */
extern const char* loongarch_cpu_strings[];
diff --git a/gcc/config/loongarch/loongarch-driver.h b/gcc/config/loongarch/loongarch-driver.h
index ba8817a4621..0a22acab803 100644
--- a/gcc/config/loongarch/loongarch-driver.h
+++ b/gcc/config/loongarch/loongarch-driver.h
@@ -58,9 +58,13 @@ driver_get_normalized_m_opts (int argc, const char **argv);
/* ABI spec strings. */
#define ABI_GRLEN_SPEC \
+ "%{mabi=ilp32*:32}" \
"%{mabi=lp64*:64}" \
#define ABI_SPEC \
+ "%{mabi=ilp32d:ilp32d}" \
+ "%{mabi=ilp32f:ilp32f}" \
+ "%{mabi=ilp32s:ilp32s}" \
"%{mabi=lp64d:lp64d}" \
"%{mabi=lp64f:lp64f}" \
"%{mabi=lp64s:lp64s}" \
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index a52e25236ea..9fc0bbbcb6e 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -36,6 +36,9 @@ struct loongarch_target la_target;
#define ABI_COUNT (sizeof(abi_priority_list)/sizeof(struct loongarch_abi))
static const struct loongarch_abi
abi_priority_list[] = {
+ {ABI_BASE_ILP32D, ABI_EXT_BASE},
+ {ABI_BASE_ILP32F, ABI_EXT_BASE},
+ {ABI_BASE_ILP32S, ABI_EXT_BASE},
{ABI_BASE_LP64D, ABI_EXT_BASE},
{ABI_BASE_LP64F, ABI_EXT_BASE},
{ABI_BASE_LP64S, ABI_EXT_BASE},
@@ -410,17 +413,23 @@ isa_default_abi (const struct loongarch_isa *isa)
switch (isa->fpu)
{
case ISA_EXT_FPU64:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base == ISA_BASE_LA32V100)
+ abi.base = ABI_BASE_ILP32D;
+ else if (isa->base == ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64D;
break;
case ISA_EXT_FPU32:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base == ISA_BASE_LA32V100)
+ abi.base = ABI_BASE_ILP32F;
+ else if (isa->base == ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64F;
break;
case ISA_EXT_NOFPU:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base == ISA_BASE_LA32V100)
+ abi.base = ABI_BASE_ILP32S;
+ else if (isa->base == ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64S;
break;
@@ -439,6 +448,8 @@ isa_base_compat_p (const struct loongarch_isa *set1,
{
switch (set2->base)
{
+ case ISA_BASE_LA32V100:
+ return (set1->base == ISA_BASE_LA32V100);
case ISA_BASE_LA64V100:
return (set1->base == ISA_BASE_LA64V100);
@@ -487,6 +498,11 @@ abi_default_cpu_arch (struct loongarch_abi abi)
{
switch (abi.base)
{
+ case ABI_BASE_ILP32D:
+ case ABI_BASE_ILP32F:
+ case ABI_BASE_ILP32S:
+ if (abi.ext == ABI_EXT_BASE)
+ return CPU_LOONGARCH32;
case ABI_BASE_LP64D:
case ABI_BASE_LP64F:
case ABI_BASE_LP64S:
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index b1ff54426e4..c8794dff0ad 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -51,15 +51,25 @@ loongarch_config_target (struct loongarch_target *target,
#define TARGET_CMODEL_EXTREME (la_target.cmodel == CMODEL_EXTREME)
#define TARGET_HARD_FLOAT (la_target.isa.fpu != ISA_EXT_NOFPU)
-#define TARGET_HARD_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D \
+#define TARGET_HARD_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32D \
+ || la_target.abi.base == ABI_BASE_ILP32F \
+ || la_target.abi.base == ABI_BASE_LP64D \
|| la_target.abi.base == ABI_BASE_LP64F)
#define TARGET_SOFT_FLOAT (la_target.isa.fpu == ISA_EXT_NOFPU)
-#define TARGET_SOFT_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64S)
+#define TARGET_SOFT_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32S \
+ || la_target.abi.base == ABI_BASE_LP64S)
#define TARGET_SINGLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU32)
-#define TARGET_SINGLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64F)
+#define TARGET_SINGLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32F \
+ || la_target.abi.base == ABI_BASE_LP64F)
#define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64)
-#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D)
+#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32D \
+ || la_target.abi.base == ABI_BASE_LP64D)
+
+#define TARGET_32BIT (la_target.isa.base == ISA_BASE_LA32V100)
+#define TARGET_ABI_ILP32 (la_target.abi.base == ABI_BASE_ILP32D \
+ || la_target.abi.base == ABI_BASE_ILP32F \
+ || la_target.abi.base == ABI_BASE_ILP32S)
#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100)
#define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \
@@ -78,9 +88,11 @@ loongarch_config_target (struct loongarch_target *target,
? (la_target.cpu_native) : (CPU_NATIVE)) \
: (la_target.cpu_tune))
+#define TARGET_ARCH_LOONGARCH32 (LARCH_ACTUAL_ARCH == CPU_LOONGARCH32)
#define TARGET_ARCH_LOONGARCH64 (LARCH_ACTUAL_ARCH == CPU_LOONGARCH64)
#define TARGET_ARCH_LA464 (LARCH_ACTUAL_ARCH == CPU_LA464)
+#define TARGET_TUNE_LOONGARCH32 (LARCH_ACTUAL_TUNE == CPU_LOONGARCH32)
#define TARGET_TUNE_LOONGARCH64 (LARCH_ACTUAL_TUNE == CPU_LOONGARCH64)
#define TARGET_TUNE_LA464 (LARCH_ACTUAL_TUNE == CPU_LA464)
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index af2e82a321f..60588da45e2 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -27,9 +27,11 @@ along with GCC; see the file COPYING3. If not see
#define OPTSTR_TUNE "tune"
#define STR_CPU_NATIVE "native"
+#define STR_CPU_LOONGARCH32 "loongarch32"
#define STR_CPU_LOONGARCH64 "loongarch64"
#define STR_CPU_LA464 "la464"
+#define STR_ISA_BASE_LA32V100 "la32"
#define STR_ISA_BASE_LA64V100 "la64"
#define OPTSTR_ISA_EXT_FPU "fpu"
@@ -43,6 +45,9 @@ along with GCC; see the file COPYING3. If not see
#define OPTSTR_DOUBLE_FLOAT "double-float"
#define OPTSTR_ABI_BASE "abi"
+#define STR_ABI_BASE_ILP32D "ilp32d"
+#define STR_ABI_BASE_ILP32F "ilp32f"
+#define STR_ABI_BASE_ILP32S "ilp32s"
#define STR_ABI_BASE_LP64D "lp64d"
#define STR_ABI_BASE_LP64F "lp64f"
#define STR_ABI_BASE_LP64S "lp64s"
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 5b8b93eb24b..ff7904d49d5 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -6208,7 +6208,7 @@ loongarch_option_override_internal (struct gcc_options *opts)
la_opt_cpu_arch, la_opt_cpu_tune, la_opt_fpu,
la_opt_abi_base, la_opt_abi_ext, la_opt_cmodel, 0);
- if (TARGET_ABI_LP64)
+ if (TARGET_ABI_LP64 || TARGET_ABI_ILP32)
flag_pcc_struct_return = 0;
/* Decide which rtx_costs structure to use. */
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index 68018ade73f..2cd36c5e8fa 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -92,6 +92,9 @@ LoongArch CPU types:
EnumValue
Enum(cpu_type) String(native) Value(CPU_NATIVE)
+EnumValue
+Enum(cpu_type) String(loongarch32) Value(CPU_LOONGARCH32)
+
EnumValue
Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
@@ -115,6 +118,15 @@ Enum
Name(abi_base) Type(int)
Base ABI types for LoongArch:
+EnumValue
+Enum(abi_base) String(ilp32d) Value(ABI_BASE_ILP32D)
+
+EnumValue
+Enum(abi_base) String(ilp32f) Value(ABI_BASE_ILP32F)
+
+EnumValue
+Enum(abi_base) String(ilp32s) Value(ABI_BASE_ILP32S)
+
EnumValue
Enum(abi_base) String(lp64d) Value(ABI_BASE_LP64D)
diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
index e40da179203..1718c3e11a2 100644
--- a/gcc/config/loongarch/t-linux
+++ b/gcc/config/loongarch/t-linux
@@ -17,8 +17,8 @@
# <http://www.gnu.org/licenses/>.
# Multilib
-MULTILIB_OPTIONS = mabi=lp64d/mabi=lp64f/mabi=lp64s
-MULTILIB_DIRNAMES = base/lp64d base/lp64f base/lp64s
+MULTILIB_OPTIONS = mabi=ilp32d/mabi=ilp32f/mabi=ilp32s/mabi=lp64d/mabi=lp64f/mabi=lp64s
+MULTILIB_DIRNAMES = base/ilp32d base/ilp32f base/ilp32s base/lp64d base/lp64f base/lp64s
# The GCC driver always gets all abi-related options on the command line.
# (see loongarch-driver.c:driver_get_normalized_m_opts)
@@ -38,6 +38,18 @@ endif
# Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
+ MULTILIB_OSDIRNAMES = \
+ mabi.ilp32d=../lib32$\
+ $(call if_multiarch,:loongarch32-linux-gnu)
+
+ MULTILIB_OSDIRNAMES += \
+ mabi.ilp32f=../lib32/f32$\
+ $(call if_multiarch,:loongarch32-linux-gnuf32)
+
+ MULTILIB_OSDIRNAMES += \
+ mabi.ilp32s=../lib32/sf$\
+ $(call if_multiarch,:loongarch32-linux-gnusf)
+
MULTILIB_OSDIRNAMES = \
mabi.lp64d=../lib64$\
$(call if_multiarch,:loongarch64-linux-gnu)
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/9] LoongArch: Fix default ISA setting
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
@ 2023-08-06 12:49 ` Jiajie Chen
2023-08-09 3:38 ` Xi Ruoyao
2023-08-06 12:50 ` [PATCH 3/9] LoongArch: Fix SI division for loongarch32 target Jiajie Chen
` (7 subsequent siblings)
8 siblings, 1 reply; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:49 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
When loongarch_arch_target is called, la_target has not been
initialized, thus the macro LARCH_ACTUAL_ARCH always equals to zero.
This commit fixes by expanding the macro and reading the latest value.
It permits -march=loongarch64 when the default target is loongarch32 and
vice versa.
gcc/ChangeLog:
* config/loongarch/loongarch-opts.cc (loongarch_config_target):
Fix -march detection.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/arch-1.c: New test.
* gcc.target/loongarch/arch-2.c: New test.
* gcc.target/loongarch/arch-3.c: New test.
---
gcc/config/loongarch/loongarch-opts.cc | 5 ++++-
gcc/testsuite/gcc.target/loongarch/arch-1.c | 5 +++++
gcc/testsuite/gcc.target/loongarch/arch-2.c | 5 +++++
gcc/testsuite/gcc.target/loongarch/arch-3.c | 6 ++++++
4 files changed, 20 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/loongarch/arch-1.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/arch-2.c
create mode 100644 gcc/testsuite/gcc.target/loongarch/arch-3.c
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index 9fc0bbbcb6e..29c0c4468bb 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -246,7 +246,10 @@ loongarch_config_target (struct loongarch_target *target,
config_target_isa:
/* Get default ISA from "-march" or its default value. */
- t.isa = loongarch_cpu_default_isa[LARCH_ACTUAL_ARCH];
+ if (t.cpu_arch == TARGET_ARCH_NATIVE)
+ t.isa = loongarch_cpu_default_isa[t.cpu_native];
+ else
+ t.isa = loongarch_cpu_default_isa[t.cpu_arch];
/* Apply incremental changes. */
/* "-march=native" overrides the default FPU type. */
diff --git a/gcc/testsuite/gcc.target/loongarch/arch-1.c b/gcc/testsuite/gcc.target/loongarch/arch-1.c
new file mode 100644
index 00000000000..379036ec76f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/arch-1.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/arch-2.c b/gcc/testsuite/gcc.target/loongarch/arch-2.c
new file mode 100644
index 00000000000..55d646902a6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/arch-2.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch32 -mabi=ilp32d" } */
+int foo()
+{
+}
diff --git a/gcc/testsuite/gcc.target/loongarch/arch-3.c b/gcc/testsuite/gcc.target/loongarch/arch-3.c
new file mode 100644
index 00000000000..543b93883bd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/arch-3.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-march=loongarch64 -mabi=ilp32d" } */
+int foo()
+{
+}
+/* { dg-error "unable to implement ABI 'ilp32d' with instruction set 'la64/fpu64'" "" { target *-*-* } 0 } */
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/9] LoongArch: Fix SI division for loongarch32 target
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
2023-08-06 12:49 ` [PATCH 2/9] LoongArch: Fix default ISA setting Jiajie Chen
@ 2023-08-06 12:50 ` Jiajie Chen
2023-08-06 12:50 ` [PATCH 4/9] LoongArch: Fix movgr2frh.w operand order Jiajie Chen
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:50 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
Add TARGET_64BIT check for loongarch64-only handling of SI division. It
shall not promote SI to DI before division in loongarch32 target.
gcc/ChangeLog:
* config/loongarch/loongarch.md: Add TARGET_64BIT check for
loongarch64-only handling of SI division.
---
gcc/config/loongarch/loongarch.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index b37e070660f..95c5b25d22a 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -851,7 +851,7 @@
(match_operand:GPR 2 "register_operand")))]
""
{
- if (GET_MODE (operands[0]) == SImode)
+ if (GET_MODE (operands[0]) == SImode && TARGET_64BIT)
{
rtx reg1 = gen_reg_rtx (DImode);
rtx reg2 = gen_reg_rtx (DImode);
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 4/9] LoongArch: Fix movgr2frh.w operand order
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
2023-08-06 12:49 ` [PATCH 2/9] LoongArch: Fix default ISA setting Jiajie Chen
2023-08-06 12:50 ` [PATCH 3/9] LoongArch: Fix SI division for loongarch32 target Jiajie Chen
@ 2023-08-06 12:50 ` Jiajie Chen
2023-08-06 12:50 ` [PATCH 5/9] LoongArch: Fix 64-bit move for loongarch32 target Jiajie Chen
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:50 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
The operand order of movgr2frh.w was wrong. The correct order should be
`movgr2frh.w fd, rj`.
gcc/ChangeLog:
* config/loongarch/loongarch.md (movgr2frh<mode>): Correct
movgr2frh.w operand order.
---
gcc/config/loongarch/loongarch.md | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 95c5b25d22a..93d8bf5bcca 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -2297,7 +2297,7 @@
(match_operand:SPLITF 2 "register_operand" "0")]
UNSPEC_MOVGR2FRH))]
"TARGET_DOUBLE_FLOAT"
- "movgr2frh.w\t%z1,%0"
+ "movgr2frh.w\t%0,%z1"
[(set_attr "move_type" "mgtf")
(set_attr "mode" "<HALFMODE>")])
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 5/9] LoongArch: Fix 64-bit move for loongarch32 target
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
` (2 preceding siblings ...)
2023-08-06 12:50 ` [PATCH 4/9] LoongArch: Fix movgr2frh.w operand order Jiajie Chen
@ 2023-08-06 12:50 ` Jiajie Chen
2023-08-06 12:50 ` [PATCH 6/9] LoongArch: Fix 64-bit immediate " Jiajie Chen
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:50 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
Bring back 64-bit move splitting for loongarch32. The code was removed
in commit 16fc26d4e7a (`LoongArch: Support split symbol.`) for unknown
reason.
gcc/ChangeLog:
* config/loongarch/loongarch.md: Handle move splitting for
64-bit operands.
---
gcc/config/loongarch/loongarch.md | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 93d8bf5bcca..9eb6bb75c35 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1965,6 +1965,16 @@
[(set_attr "move_type" "move,load,store")
(set_attr "mode" "DF")])
+(define_split
+ [(set (match_operand:MOVE64 0 "nonimmediate_operand")
+ (match_operand:MOVE64 1 "move_operand"))]
+ "reload_completed && loongarch_split_move_p (operands[0], operands[1])"
+ [(const_int 0)]
+{
+ loongarch_split_move (operands[0], operands[1], curr_insn);
+ DONE;
+})
+
;; Emit a doubleword move in which exactly one of the operands is
;; a floating-point register. We can't just emit two normal moves
;; because of the constraints imposed by the FPU register model;
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 6/9] LoongArch: Fix 64-bit immediate move for loongarch32 target
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
` (3 preceding siblings ...)
2023-08-06 12:50 ` [PATCH 5/9] LoongArch: Fix 64-bit move for loongarch32 target Jiajie Chen
@ 2023-08-06 12:50 ` Jiajie Chen
2023-08-06 12:50 ` [PATCH 7/9] LoongArch: Fix signed 32-bit overflow " Jiajie Chen
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:50 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
loongarch_move_integer does not support splitting 64-bit integer into
two 32-bit ones. Thus, define_split is removed from movdi_32bit and
TARGET_64BIT is added to the split condition of movdi_64bit to avoid
using it for loongarch32.
gcc/ChangeLog:
* config/loongarch/loongarch.md (movdi_32bit): Remove not
working split, use existing loongarch_split_move instead.
(movdi_64bit) Add TARGET_64BIT to split condition.
---
gcc/config/loongarch/loongarch.md | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 9eb6bb75c35..c611a8a822a 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1777,22 +1777,13 @@
DONE;
})
-(define_insn_and_split "*movdi_32bit"
+(define_insn "*movdi_32bit"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,w,*f,*f,*r,*m")
(match_operand:DI 1 "move_operand" "r,i,w,r,*J*r,*m,*f,*f"))]
"!TARGET_64BIT
&& (register_operand (operands[0], DImode)
|| reg_or_0_operand (operands[1], DImode))"
{ return loongarch_output_move (operands[0], operands[1]); }
- "CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
- (operands[0]))"
- [(const_int 0)]
- "
-{
- loongarch_move_integer (operands[0], operands[0], INTVAL (operands[1]));
- DONE;
-}
- "
[(set_attr "move_type" "move,const,load,store,mgtf,fpload,mftg,fpstore")
(set_attr "mode" "DI")])
@@ -1804,7 +1795,7 @@
|| reg_or_0_operand (operands[1], DImode))"
{ return loongarch_output_move (operands[0], operands[1]); }
"CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
- (operands[0]))"
+ (operands[0])) && TARGET_64BIT"
[(const_int 0)]
"
{
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 7/9] LoongArch: Fix signed 32-bit overflow for loongarch32 target
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
` (4 preceding siblings ...)
2023-08-06 12:50 ` [PATCH 6/9] LoongArch: Fix 64-bit immediate " Jiajie Chen
@ 2023-08-06 12:50 ` Jiajie Chen
2023-08-06 12:50 ` [PATCH 8/9] LoongArch: Do not emit SF/DF <-> DI conversion in loongarch32 Jiajie Chen
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:50 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
When rhs equals to 0x7fffffff, adding 1 to rhs overflows SI, generating
invalid const_int.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_emit_int_compare):
Call trunc_int_mode to ensure valid rhs.
---
gcc/config/loongarch/loongarch.cc | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index ff7904d49d5..5a9c99afc99 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -4283,6 +4283,7 @@ loongarch_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1)
break;
new_rhs = rhs + (increment ? 1 : -1);
+ new_rhs = trunc_int_for_mode (new_rhs, GET_MODE (*op0));
if (loongarch_integer_cost (new_rhs)
< loongarch_integer_cost (rhs))
{
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 8/9] LoongArch: Do not emit SF/DF <-> DI conversion in loongarch32
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
` (5 preceding siblings ...)
2023-08-06 12:50 ` [PATCH 7/9] LoongArch: Fix signed 32-bit overflow " Jiajie Chen
@ 2023-08-06 12:50 ` Jiajie Chen
2023-08-06 12:50 ` [PATCH 9/9] LoongArch: Add: Add -march=loongarch64 to tests with -mabi=lp64d Jiajie Chen
2023-08-09 2:50 ` [PATCH 1/9] LoongArch: Introduce loongarch32 target Chenghua Xu
8 siblings, 0 replies; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:50 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
In loongarch32 target, conversions between SF/DF and DI are not
supported.
gcc/ChangeLog:
* config/loongarch/loongarch.md: Check TARGET_64BIT in insns
regarding SF/DF <-> DI conversion.
---
gcc/config/loongarch/loongarch.md | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index c611a8a822a..bced4b08569 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -1504,7 +1504,7 @@
(define_insn "floatdidf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(float:DF (match_operand:DI 1 "register_operand" "f")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT && TARGET_64BIT"
"ffint.d.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "DF")
@@ -1522,7 +1522,7 @@
(define_insn "floatdisf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(float:SF (match_operand:DI 1 "register_operand" "f")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT && TARGET_64BIT"
"ffint.s.l\t%0,%1"
[(set_attr "type" "fcvt")
(set_attr "mode" "SF")
@@ -1576,7 +1576,7 @@
(define_expand "fixuns_truncdfdi2"
[(set (match_operand:DI 0 "register_operand")
(unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT && TARGET_64BIT"
{
rtx reg1 = gen_reg_rtx (DFmode);
rtx reg2 = gen_reg_rtx (DFmode);
@@ -1658,7 +1658,7 @@
(define_expand "fixuns_truncsfdi2"
[(set (match_operand:DI 0 "register_operand")
(unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
- "TARGET_DOUBLE_FLOAT"
+ "TARGET_DOUBLE_FLOAT && TARGET_64BIT"
{
rtx reg1 = gen_reg_rtx (SFmode);
rtx reg2 = gen_reg_rtx (SFmode);
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 9/9] LoongArch: Add: Add -march=loongarch64 to tests with -mabi=lp64d
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
` (6 preceding siblings ...)
2023-08-06 12:50 ` [PATCH 8/9] LoongArch: Do not emit SF/DF <-> DI conversion in loongarch32 Jiajie Chen
@ 2023-08-06 12:50 ` Jiajie Chen
2023-08-09 2:50 ` [PATCH 1/9] LoongArch: Introduce loongarch32 target Chenghua Xu
8 siblings, 0 replies; 11+ messages in thread
From: Jiajie Chen @ 2023-08-06 12:50 UTC (permalink / raw)
To: gcc-patches; +Cc: Jiajie Chen
The compiler emits a warning if the current target (-march=loongarch32)
mismatches with abi(-march-lp64d). Adding: Add -march=loongarch64
explicitly fixes the tests.
gcc/testsuite/ChangeLog:
* g++.target/loongarch/bytepick.C: Add -march=loongarch64
* g++.target/loongarch/pr106828.C: Add -march=loongarch64
* gcc.target/loongarch/add-const.c: Add -march=loongarch64
* gcc.target/loongarch/arch-1.c: Add -march=loongarch64
* gcc.target/loongarch/attr-model-1.c: Add -march=loongarch64
* gcc.target/loongarch/attr-model-2.c: Add -march=loongarch64
* gcc.target/loongarch/flt-abi-isa-1.c: Add -march=loongarch64
* gcc.target/loongarch/fscaleb.c: Add -march=loongarch64
* gcc.target/loongarch/ftint-no-inexact.c: Add
-march=loongarch64
* gcc.target/loongarch/ftint.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-1.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-2.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-3.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-4.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-5.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-6.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-7.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-8.c: Add -march=loongarch64
* gcc.target/loongarch/func-call-extreme-1.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-extreme-2.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-medium-1.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-medium-2.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-medium-3.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-medium-4.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-medium-5.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-medium-6.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-medium-7.c: Add
-march=loongarch64
* gcc.target/loongarch/func-call-medium-8.c: Add
-march=loongarch64
* gcc.target/loongarch/imm-load.c: Add -march=loongarch64
* gcc.target/loongarch/imm-load1.c: Add -march=loongarch64
* gcc.target/loongarch/mulw_d_w.c: Add -march=loongarch64
* gcc.target/loongarch/pr109465-1.c: Add -march=loongarch64
* gcc.target/loongarch/pr109465-2.c: Add -march=loongarch64
* gcc.target/loongarch/pr109465-3.c: Add -march=loongarch64
* gcc.target/loongarch/prolog-opt.c: Add -march=loongarch64
* gcc.target/loongarch/relocs-symbol-noaddend.c: Add
-march=loongarch64
* gcc.target/loongarch/zero-size-field-pass.c: Add
-march=loongarch64
* gcc.target/loongarch/zero-size-field-ret.c: Add
-march=loongarch64
---
gcc/testsuite/g++.target/loongarch/bytepick.C | 2 +-
gcc/testsuite/g++.target/loongarch/pr106828.C | 2 +-
gcc/testsuite/gcc.target/loongarch/add-const.c | 2 +-
gcc/testsuite/gcc.target/loongarch/arch-1.c | 2 +-
gcc/testsuite/gcc.target/loongarch/attr-model-1.c | 2 +-
gcc/testsuite/gcc.target/loongarch/attr-model-2.c | 2 +-
gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c | 2 +-
gcc/testsuite/gcc.target/loongarch/fscaleb.c | 2 +-
gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c | 2 +-
gcc/testsuite/gcc.target/loongarch/ftint.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-1.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-2.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-3.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-4.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-5.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-6.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-7.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-8.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c | 2 +-
gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c | 2 +-
gcc/testsuite/gcc.target/loongarch/imm-load.c | 2 +-
gcc/testsuite/gcc.target/loongarch/imm-load1.c | 2 +-
gcc/testsuite/gcc.target/loongarch/mulw_d_w.c | 2 +-
gcc/testsuite/gcc.target/loongarch/pr109465-1.c | 2 +-
gcc/testsuite/gcc.target/loongarch/pr109465-2.c | 2 +-
gcc/testsuite/gcc.target/loongarch/pr109465-3.c | 2 +-
gcc/testsuite/gcc.target/loongarch/prolog-opt.c | 2 +-
gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c | 2 +-
gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c | 2 +-
gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c | 2 +-
38 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/gcc/testsuite/g++.target/loongarch/bytepick.C b/gcc/testsuite/g++.target/loongarch/bytepick.C
index a39e2fa65b7..c2b0dd5e513 100644
--- a/gcc/testsuite/g++.target/loongarch/bytepick.C
+++ b/gcc/testsuite/g++.target/loongarch/bytepick.C
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mabi=lp64d" } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
/* { dg-final { scan-assembler-times "bytepick.w\t\\\$r4,\\\$r5,\\\$r4" 3 } } */
/* { dg-final { scan-assembler-times "bytepick.d\t\\\$r4,\\\$r5,\\\$r4" 7 } } */
/* { dg-final { scan-assembler-not "slli.w" } } */
diff --git a/gcc/testsuite/g++.target/loongarch/pr106828.C b/gcc/testsuite/g++.target/loongarch/pr106828.C
index 190c1db715f..74590891a67 100644
--- a/gcc/testsuite/g++.target/loongarch/pr106828.C
+++ b/gcc/testsuite/g++.target/loongarch/pr106828.C
@@ -1,4 +1,4 @@
/* { dg-do-preprocess } */
-/* { dg-options "-mabi=lp64d -fsanitize=address" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -fsanitize=address" } */
/* Tests whether the compiler supports compile option '-fsanitize=address'. */
diff --git a/gcc/testsuite/gcc.target/loongarch/add-const.c b/gcc/testsuite/gcc.target/loongarch/add-const.c
index 7b6a7cb92aa..04286afad49 100644
--- a/gcc/testsuite/gcc.target/loongarch/add-const.c
+++ b/gcc/testsuite/gcc.target/loongarch/add-const.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O -mabi=lp64d" } */
+/* { dg-options "-O -march=loongarch64 -mabi=lp64d" } */
/* None of these functions should load the const operand into a temp
register. */
diff --git a/gcc/testsuite/gcc.target/loongarch/arch-1.c b/gcc/testsuite/gcc.target/loongarch/arch-1.c
index 379036ec76f..551c999c4e3 100644
--- a/gcc/testsuite/gcc.target/loongarch/arch-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/arch-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=loongarch64 -mabi=lp64d" } */
+/* { dg-options "-march=loongarch64 -march=loongarch64 -mabi=lp64d" } */
int foo()
{
}
diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-1.c b/gcc/testsuite/gcc.target/loongarch/attr-model-1.c
index 916d715b98b..005c7cd727e 100644
--- a/gcc/testsuite/gcc.target/loongarch/attr-model-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/attr-model-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mexplicit-relocs -mcmodel=normal -O2" } */
+/* { dg-options "-mexplicit-relocs -mcmodel=normal -O2 -march=loongarch64" } */
/* { dg-final { scan-assembler-times "%pc64_hi12" 2 } } */
#define ATTR_MODEL_TEST
diff --git a/gcc/testsuite/gcc.target/loongarch/attr-model-2.c b/gcc/testsuite/gcc.target/loongarch/attr-model-2.c
index a74c795ac3e..242c40161e9 100644
--- a/gcc/testsuite/gcc.target/loongarch/attr-model-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/attr-model-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mexplicit-relocs -mcmodel=extreme -O2" } */
+/* { dg-options "-mexplicit-relocs -mcmodel=extreme -O2 -march=loongarch64" } */
/* { dg-final { scan-assembler-times "%pc64_hi12" 3 } } */
#define ATTR_MODEL_TEST
diff --git a/gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c b/gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c
index 1c9490f6a87..9cc2d439bf1 100644
--- a/gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/flt-abi-isa-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -mfpu=64 -march=loongarch64 -O2" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -mfpu=64 -march=loongarch64 -O2" } */
/* { dg-final { scan-assembler "frecip\\.d" } } */
/* { dg-final { scan-assembler-not "movgr2fr\\.d" } } */
/* { dg-final { scan-assembler-not "movfr2gr\\.d" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/fscaleb.c b/gcc/testsuite/gcc.target/loongarch/fscaleb.c
index f18470fbb8f..d39cdc63ae8 100644
--- a/gcc/testsuite/gcc.target/loongarch/fscaleb.c
+++ b/gcc/testsuite/gcc.target/loongarch/fscaleb.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno" } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mdouble-float -fno-math-errno" } */
/* { dg-final { scan-assembler-times "fscaleb\\.s" 3 } } */
/* { dg-final { scan-assembler-times "fscaleb\\.d" 4 } } */
/* { dg-final { scan-assembler-times "slli\\.w" 1 } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c b/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c
index 88b83a9c056..e98d26070bc 100644
--- a/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c
+++ b/gcc/testsuite/gcc.target/loongarch/ftint-no-inexact.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno -fno-fp-int-builtin-inexact" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -mdouble-float -fno-math-errno -fno-fp-int-builtin-inexact" } */
/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */
/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */
/* { dg-final { scan-assembler-not "ftintrm\\.l\\.s" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/ftint.c b/gcc/testsuite/gcc.target/loongarch/ftint.c
index 7a326a454d8..1002293aee9 100644
--- a/gcc/testsuite/gcc.target/loongarch/ftint.c
+++ b/gcc/testsuite/gcc.target/loongarch/ftint.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno -ffp-int-builtin-inexact" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -mdouble-float -fno-math-errno -ffp-int-builtin-inexact" } */
/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */
/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */
/* { dg-final { scan-assembler "ftintrm\\.l\\.s" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-1.c
index 76bf11b0c03..d25a71e6a4c 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fplt -mno-explicit-relocs -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fplt -mno-explicit-relocs -mcmodel=normal" } */
/* { dg-final { scan-assembler "test:.*bl\t%plt\\(g\\)\n" } } */
/* { dg-final { scan-assembler "test1:.*bl\t%plt\\(f\\)\n" } } */
/* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-2.c
index 4b468fef8b4..ac1d3b0cec2 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fplt -mno-explicit-relocs -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fplt -mno-explicit-relocs -mcmodel=normal" } */
/* { dg-final { scan-assembler "test:.*bl\t%plt\\(g\\)\n" } } */
/* { dg-final { scan-assembler "test1:.*bl\tf\n" } } */
/* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-3.c b/gcc/testsuite/gcc.target/loongarch/func-call-3.c
index dd3a4882d60..e8156cb4eff 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-3.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mno-explicit-relocs -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mno-explicit-relocs -mcmodel=normal" } */
/* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */
/* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-4.c b/gcc/testsuite/gcc.target/loongarch/func-call-4.c
index f8158ec349f..684475bc3bb 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-4.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mno-explicit-relocs -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mno-explicit-relocs -mcmodel=normal" } */
/* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*bl\tf\n" } } */
/* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-5.c b/gcc/testsuite/gcc.target/loongarch/func-call-5.c
index 37994af430d..0411d8b6421 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-5.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fplt -mexplicit-relocs -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fplt -mexplicit-relocs -mcmodel=normal" } */
/* { dg-final { scan-assembler "test:.*bl\t%plt\\(g\\)\n" } } */
/* { dg-final { scan-assembler "test1:.*bl\t%plt\\(f\\)\n" } } */
/* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-6.c b/gcc/testsuite/gcc.target/loongarch/func-call-6.c
index 8e366e376e7..beae892c8fd 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-6.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fplt -mexplicit-relocs -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fplt -mexplicit-relocs -mcmodel=normal" } */
/* { dg-final { scan-assembler "test:.*bl\t%plt\\(g\\)\n" } } */
/* { dg-final { scan-assembler "test1:.*bl\tf\n" } } */
/* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-7.c b/gcc/testsuite/gcc.target/loongarch/func-call-7.c
index 4177c3d962e..6f6d0456836 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-7.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=normal" } */
/* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*pcalau12i\t.*%got_pc_hi20\\(f\\)\n\tld\.d\t.*%got_pc_lo12\\(f\\)\n\tjirl" } } */
/* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-8.c b/gcc/testsuite/gcc.target/loongarch/func-call-8.c
index 4254eaa16d4..ebb68b368ed 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-8.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=normal" } */
/* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*bl\tf\n" } } */
/* { dg-final { scan-assembler "test2:.*bl\tl\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
index db1e0f85396..5e83d3107ed 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
/* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
/* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
/* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
index 21bf81ae837..e09defff24b 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-extreme-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=extreme" } */
/* { dg-final { scan-assembler "test:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
/* { dg-final { scan-assembler "test1:.*pcalau12i.*%got_pc_hi20.*\n\taddi\.d.*%got_pc_lo12.*\n\tlu32i\.d.*%got64_pc_lo20.*\n\tlu52i\.d.*%got64_pc_hi12.*\n\tldx\.d" } } */
/* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20.*\n\taddi\.d.*%pc_lo12.*\n\tlu32i\.d.*%pc64_lo20.*\n\tlu52i\.d.*pc64_hi12.*\n\tadd\.d" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c
index 6339e832fe5..e43b4b0fe40 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fplt -mno-explicit-relocs -mcmodel=medium" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fplt -mno-explicit-relocs -mcmodel=medium" } */
/* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */
/* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c
index a53e75e0bf9..17bfedd4d0d 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fplt -mno-explicit-relocs -mcmodel=medium" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fplt -mno-explicit-relocs -mcmodel=medium" } */
/* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*la\.local\t.*f\n\tjirl" } } */
/* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c
index 0da7bf98e3c..00439c6ab9e 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mno-explicit-relocs -mcmodel=medium" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mno-explicit-relocs -mcmodel=medium" } */
/* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*la\.global\t.*f\n\tjirl" } } */
/* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c
index 0219688ae80..ed23a4ebecc 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mno-explicit-relocs -mcmodel=medium" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mno-explicit-relocs -mcmodel=medium" } */
/* { dg-final { scan-assembler "test:.*la\.global\t.*g\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*la\.local\t.*f\n\tjirl" } } */
/* { dg-final { scan-assembler "test2:.*la\.local\t.*l\n\tjirl" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c
index 8a47b5afcba..4693517843e 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-5.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fplt -mexplicit-relocs -mcmodel=medium" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fplt -mexplicit-relocs -mcmodel=medium" } */
/* { dg-final { scan-assembler "test:.*pcalau12i.*%pc_hi20\\(g\\)\n\tjirl.*pc_lo12\\(g\\)" } } */
/* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */
/* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c
index 1e75e60e01a..ef8228ec361 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-6.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fplt -mexplicit-relocs -mcmodel=medium" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fplt -mexplicit-relocs -mcmodel=medium" } */
/* { dg-final { scan-assembler "test:.*pcalau12i.*%pc_hi20\\(g\\)\n\tjirl.*pc_lo12\\(g\\)" } } */
/* { dg-final { scan-assembler "test1:.*pcalau12i.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */
/* { dg-final { scan-assembler "test2:.*pcalau12i.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c
index 9e89085ca19..12f2ef37b0e 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-7.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=medium" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fpic -fno-plt -mexplicit-relocs -mcmodel=medium" } */
/* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*pcalau12i\t.*%got_pc_hi20\\(f\\)\n\tld\.d\t.*%got_pc_lo12\\(f\\)\n\tjirl" } } */
/* { dg-final { scan-assembler "test2:.*pcalau12i\t.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c b/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c
index fde9c6e0ef4..251f207dfe0 100644
--- a/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c
+++ b/gcc/testsuite/gcc.target/loongarch/func-call-medium-8.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=medium" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O0 -fno-pic -fno-plt -mexplicit-relocs -mcmodel=medium" } */
/* { dg-final { scan-assembler "test:.*pcalau12i\t.*%got_pc_hi20\\(g\\)\n\tld\.d\t.*%got_pc_lo12\\(g\\)\n\tjirl" } } */
/* { dg-final { scan-assembler "test1:.*pcalau12i\t.*%pc_hi20\\(f\\)\n\tjirl.*%pc_lo12\\(f\\)" } } */
/* { dg-final { scan-assembler "test2:.*pcalau12i\t.*%pc_hi20\\(l\\)\n\tjirl.*%pc_lo12\\(l\\)" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/imm-load.c b/gcc/testsuite/gcc.target/loongarch/imm-load.c
index c04ca33996f..18102efacde 100644
--- a/gcc/testsuite/gcc.target/loongarch/imm-load.c
+++ b/gcc/testsuite/gcc.target/loongarch/imm-load.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O2 -fdump-rtl-split1" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2 -fdump-rtl-split1" } */
long int
test (void)
diff --git a/gcc/testsuite/gcc.target/loongarch/imm-load1.c b/gcc/testsuite/gcc.target/loongarch/imm-load1.c
index 2ff02971239..4a0fe4fd30c 100644
--- a/gcc/testsuite/gcc.target/loongarch/imm-load1.c
+++ b/gcc/testsuite/gcc.target/loongarch/imm-load1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -O2" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -O2" } */
/* { dg-final { scan-assembler "test:.*lu52i\.d.*\n\taddi\.w.*\n\.L2:" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
index 4ab7df8836b..0abe7b014b9 100644
--- a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
+++ b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mabi=lp64d" } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d" } */
/* { dg-final { scan-assembler "mulw.d.w" } } */
/* This should be optimized to mulw.d.w for LA64. */
diff --git a/gcc/testsuite/gcc.target/loongarch/pr109465-1.c b/gcc/testsuite/gcc.target/loongarch/pr109465-1.c
index 4cd35d13904..1f36f4e0ab6 100644
--- a/gcc/testsuite/gcc.target/loongarch/pr109465-1.c
+++ b/gcc/testsuite/gcc.target/loongarch/pr109465-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mabi=lp64d -mno-strict-align" } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mno-strict-align" } */
/* { dg-final { scan-assembler-times "st\\.d|stptr\\.d" 1 } } */
/* { dg-final { scan-assembler-times "st\\.w|stptr\\.w" 1 } } */
/* { dg-final { scan-assembler-times "st\\.h" 1 } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/pr109465-2.c b/gcc/testsuite/gcc.target/loongarch/pr109465-2.c
index 703eb951c6d..3e934567d0e 100644
--- a/gcc/testsuite/gcc.target/loongarch/pr109465-2.c
+++ b/gcc/testsuite/gcc.target/loongarch/pr109465-2.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mabi=lp64d -mstrict-align" } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mstrict-align" } */
/* { dg-final { scan-assembler-times "st\\.d|stptr\\.d" 1 } } */
/* { dg-final { scan-assembler-times "st\\.w|stptr\\.w" 1 } } */
/* { dg-final { scan-assembler-times "st\\.h" 1 } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/pr109465-3.c b/gcc/testsuite/gcc.target/loongarch/pr109465-3.c
index d6a80659b31..7c684b2a5bf 100644
--- a/gcc/testsuite/gcc.target/loongarch/pr109465-3.c
+++ b/gcc/testsuite/gcc.target/loongarch/pr109465-3.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -mabi=lp64d -mstrict-align" } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -mstrict-align" } */
/* Three loop iterations each contains 4 st.b, and 3 st.b after the loop */
/* { dg-final { scan-assembler-times "st\\.b" 7 } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/prolog-opt.c b/gcc/testsuite/gcc.target/loongarch/prolog-opt.c
index e6a64263384..682d34ae750 100644
--- a/gcc/testsuite/gcc.target/loongarch/prolog-opt.c
+++ b/gcc/testsuite/gcc.target/loongarch/prolog-opt.c
@@ -1,7 +1,7 @@
/* Test that LoongArch backend stack drop operation optimized. */
/* { dg-do compile } */
-/* { dg-options "-O2 -mabi=lp64d -fno-stack-protector" } */
+/* { dg-options "-O2 -march=loongarch64 -mabi=lp64d -fno-stack-protector" } */
/* { dg-final { scan-assembler "addi.d\t\\\$r3,\\\$r3,-16" } } */
extern int printf (char *, ...);
diff --git a/gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c b/gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c
index 3ec8bd229fd..7d018ba0e4b 100644
--- a/gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c
+++ b/gcc/testsuite/gcc.target/loongarch/relocs-symbol-noaddend.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mabi=lp64d -mexplicit-relocs -fno-pic -O2 -mcmodel=normal" } */
+/* { dg-options "-march=loongarch64 -mabi=lp64d -mexplicit-relocs -fno-pic -O2 -mcmodel=normal" } */
/* { dg-final { scan-assembler "pcalau12i.*%pc_hi20\\(\.LANCHOR0\\)\n" } } */
/* { dg-final { scan-assembler "addi\.d.*%pc_lo12\\(\.LANCHOR0\\)\n" } } */
/* { dg-final { scan-assembler "ldptr.d\t\\\$r4,.*,0\n" } } */
diff --git a/gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c b/gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c
index 999dc913a71..7931cc2623c 100644
--- a/gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c
+++ b/gcc/testsuite/gcc.target/loongarch/zero-size-field-pass.c
@@ -2,7 +2,7 @@
argument passing. */
/* { dg-do compile } */
-/* { dg-options "-O2 -mdouble-float -mabi=lp64d" } */
+/* { dg-options "-O2 -mdouble-float -march=loongarch64 -mabi=lp64d" } */
/* { dg-final { scan-assembler "\\\$f1" } } */
struct test
diff --git a/gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c b/gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c
index 40137d97555..ef1cb6b35c7 100644
--- a/gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c
+++ b/gcc/testsuite/gcc.target/loongarch/zero-size-field-ret.c
@@ -2,7 +2,7 @@
returning. */
/* { dg-do compile } */
-/* { dg-options "-O2 -mdouble-float -mabi=lp64d" } */
+/* { dg-options "-O2 -mdouble-float -march=loongarch64 -mabi=lp64d" } */
/* { dg-final { scan-assembler-not "\\\$r4" } } */
struct test
--
2.41.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/9] LoongArch: Introduce loongarch32 target
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
` (7 preceding siblings ...)
2023-08-06 12:50 ` [PATCH 9/9] LoongArch: Add: Add -march=loongarch64 to tests with -mabi=lp64d Jiajie Chen
@ 2023-08-09 2:50 ` Chenghua Xu
8 siblings, 0 replies; 11+ messages in thread
From: Chenghua Xu @ 2023-08-09 2:50 UTC (permalink / raw)
To: Jiajie Chen; +Cc: gcc-patches
Hi Jiajie,
Thanks for you contribution. But we need some time to
define/write/public ilp32d abi doc.
Jiajie Chen via Gcc-patches writes:
> Introduce loongarch32 target and ilp32 abi variants. The ilp32d abi
> variant is selected as the default abi of loongarch32 target.
>
> contrib/ChangeLog:
>
> * config-list.mk: Add loongarch32-linux-gnu*.
>
> gcc/ChangeLog:
>
> * config.gcc: Add target triple loongarch32-*-*-* and
> corresponding abi ilp32f, ilp32d and ilp32s.
> * config/loongarch/genopts/loongarch-strings: Add strings for
> loongarch32 and ilp32 abi variants.
> * config/loongarch/genopts/loongarch.opt.in: Add
> -march=loongarch32 and -mabi=ilp32d/ilp32f/ilp32s.
> * config/loongarch/gnu-user.h: Add ilp32 abi variants to spec.
> * config/loongarch/linux.h: Add ABI_LIBDIR for ilp32 abi
> variants.
> * config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins):
> Add builtin definitions for loongarch32 target.
> * config/loongarch/loongarch-def.c: Add loongarch32 and ilp32
> definitions.
> * config/loongarch/loongarch-def.h: Add loongarch32 and ilp32
> definitions.
> * config/loongarch/loongarch-driver.h: Add ilp32 abi variants to
> spec.
> * config/loongarch/loongarch-opts.cc: Handle ilp32 abi variants.
> * config/loongarch/loongarch-opts.h: Add loongarch32 case to
> macros.
> * config/loongarch/loongarch-str.h: Add loongarch32 and ilp32
> strings.
> * config/loongarch/loongarch.cc: Disable -fpcc-struct-return for
> ilp32.
> * config/loongarch/loongarch.opt: Add -march=loongarch32 and
> -mabi=ilp32d/ilp32f/ilp32s.
> * config/loongarch/t-linux: Add ilp32 abi variants to multilib.
> ---
> contrib/config-list.mk | 1 +
> gcc/config.gcc | 61 ++++++++++++++++---
> .../loongarch/genopts/loongarch-strings | 5 ++
> gcc/config/loongarch/genopts/loongarch.opt.in | 12 ++++
> gcc/config/loongarch/gnu-user.h | 3 +
> gcc/config/loongarch/linux.h | 8 ++-
> gcc/config/loongarch/loongarch-c.cc | 12 ++++
> gcc/config/loongarch/loongarch-def.c | 33 ++++++++++
> gcc/config/loongarch/loongarch-def.h | 25 +++++---
> gcc/config/loongarch/loongarch-driver.h | 4 ++
> gcc/config/loongarch/loongarch-opts.cc | 22 ++++++-
> gcc/config/loongarch/loongarch-opts.h | 20 ++++--
> gcc/config/loongarch/loongarch-str.h | 5 ++
> gcc/config/loongarch/loongarch.cc | 2 +-
> gcc/config/loongarch/loongarch.opt | 12 ++++
> gcc/config/loongarch/t-linux | 16 ++++-
> 16 files changed, 210 insertions(+), 31 deletions(-)
>
> diff --git a/contrib/config-list.mk b/contrib/config-list.mk
> index e570b13c71b..3c00ce5410a 100644
> --- a/contrib/config-list.mk
> +++ b/contrib/config-list.mk
> @@ -57,6 +57,7 @@ LIST = aarch64-elf aarch64-freebsd13 aarch64-linux-gnu aarch64-rtems \
> i686-cygwinOPT-enable-threads=yes i686-mingw32crt ia64-elf \
> ia64-linux ia64-hpux ia64-hp-vms iq2000-elf lm32-elf \
> lm32-rtems lm32-uclinux \
> + loongarch32-linux-gnuf64 loongarch32-linux-gnuf32 loongarch32-linux-gnusf \
> loongarch64-linux-gnuf64 loongarch64-linux-gnuf32 loongarch64-linux-gnusf \
> m32c-elf m32r-elf m32rle-elf \
> m68k-elf m68k-netbsdelf \
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index 415e0e1ebc5..45e69b24b44 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -4901,10 +4901,24 @@ case "${target}" in
> arch_pattern arch_default \
> fpu_pattern fpu_default \
> tune_pattern tune_default \
> - triplet_os triplet_abi
> + triplet_os triplet_abi \
> + triplet_cpu
>
> # Infer ABI from the triplet.
> case ${target} in
> + loongarch32-*-*-*f64)
> + abi_pattern="ilp32d"
> + ;;
> + loongarch32-*-*-*f32)
> + abi_pattern="ilp32f"
> + ;;
> + loongarch32-*-*-*sf)
> + abi_pattern="ilp32s"
> + ;;
> + loongarch32-*-*-*)
> + abi_pattern="ilp32[dfs]"
> + abi_default="ilp32d"
> + ;;
> loongarch64-*-*-*f64)
> abi_pattern="lp64d"
> ;;
> @@ -4939,7 +4953,7 @@ case "${target}" in
>
> # Perform initial sanity checks on --with-* options.
> case ${with_arch} in
> - "" | loongarch64 | la464) ;; # OK, append here.
> + "" | loongarch32 | loongarch64 | la464) ;; # OK, append here.
> native)
> if test x${host} != x${target}; then
> echo "--with-arch=native is illegal for cross-compiler." 1>&2
> @@ -4958,7 +4972,7 @@ case "${target}" in
> esac
>
> case ${with_abi} in
> - "" | lp64d | lp64f | lp64s) ;; # OK, append here.
> + "" | ilp32d | ilp32f | ilp32s | lp64d | lp64f | lp64s) ;; # OK, append here.
> *)
> echo "Unsupported ABI given in --with-abi=$with_abi" 1>&2
> exit 1
> @@ -5007,12 +5021,21 @@ case "${target}" in
> ;;
> esac
>
> + case ${target} in
> + loongarch32-*-*-*)
> + triplet_cpu="loongarch32"
> + ;;
> + loongarch64-*-*-*)
> + triplet_cpu="loongarch64"
> + ;;
> + esac
> +
> case ${with_abi} in
> - "lp64d") triplet_abi="";;
> - "lp64f") triplet_abi="f32";;
> - "lp64s") triplet_abi="sf";;
> + "ilp32d" | "lp64d") triplet_abi="";;
> + "ilp32f" | "lp64f") triplet_abi="f32";;
> + "ilp32s" | "lp64s") triplet_abi="sf";;
> esac
> - la_canonical_triplet="loongarch64-${triplet_os}${triplet_abi}"
> + la_canonical_triplet="${triplet_cpu}-${triplet_os}${triplet_abi}"
>
> # Set default value for with_abiext (internal)
> case ${with_abiext} in
> @@ -5038,6 +5061,12 @@ case "${target}" in
>
> # Infer ISA-related default options from the ABI: pass 1
> case ${with_abi}/${with_abiext} in
> + ilp32*/base)
> + # architectures that support ilp32* ABI
> + arch_pattern="native|loongarch32"
> + # default architecture for ilp32* ABI
> + arch_default="loongarch32"
> + ;;
> lp64*/base)
> # architectures that support lp64* ABI
> arch_pattern="native|loongarch64|la464"
> @@ -5052,14 +5081,14 @@ case "${target}" in
>
> # Infer ISA-related default options from the ABI: pass 2
> case ${with_abi}/${with_abiext} in
> - lp64d/base)
> + ilp32d/base | lp64d/base)
> fpu_pattern="64"
> ;;
> - lp64f/base)
> + ilp32f/base | lp64f/base)
> fpu_pattern="32|64"
> fpu_default="32"
> ;;
> - lp64s/base)
> + ilp32s/base | lp64s/base)
> fpu_pattern="none|32|64"
> fpu_default="none"
> ;;
> @@ -5118,6 +5147,10 @@ case "${target}" in
> tune_pattern="*"
> tune_default="native"
> ;;
> + loongarch32)
> + tune_pattern="loongarch32"
> + tune_default="loongarch32"
> + ;;
> loongarch64)
> tune_pattern="loongarch64|la464"
> tune_default="la464"
> @@ -5187,6 +5220,9 @@ case "${target}" in
> 1)
> # Component 1: Base ABI type
> case ${component} in
> + ilp32d) elem_tmp="ABI_BASE_ILP32D,";;
> + ilp32f) elem_tmp="ABI_BASE_ILP32F,";;
> + ilp32s) elem_tmp="ABI_BASE_ILP32S,";;
> lp64d) elem_tmp="ABI_BASE_LP64D,";;
> lp64f) elem_tmp="ABI_BASE_LP64F,";;
> lp64s) elem_tmp="ABI_BASE_LP64S,";;
> @@ -5741,17 +5777,22 @@ case ${target} in
> # See macro definitions from loongarch-opts.h and loongarch-cpu.h.
> case ${with_arch} in
> native) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_NATIVE" ;;
> + loongarch32) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LOONGARCH32" ;;
> la464) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LA464" ;;
> loongarch64) tm_defines="${tm_defines} DEFAULT_CPU_ARCH=CPU_LOONGARCH64" ;;
> esac
>
> case ${with_tune} in
> native) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_NATIVE" ;;
> + loongarch32) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LOONGARCH32" ;;
> la464) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LA464" ;;
> loongarch64) tm_defines="${tm_defines} DEFAULT_CPU_TUNE=CPU_LOONGARCH64" ;;
> esac
>
> case ${with_abi} in
> + ilp32d) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32D" ;;
> + ilp32f) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32F" ;;
> + ilp32s) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_ILP32S" ;;
> lp64d) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64D" ;;
> lp64f) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64F" ;;
> lp64s) tm_defines="${tm_defines} DEFAULT_ABI_BASE=ABI_BASE_LP64S" ;;
> diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
> index a40998ead97..1e20b70dde2 100644
> --- a/gcc/config/loongarch/genopts/loongarch-strings
> +++ b/gcc/config/loongarch/genopts/loongarch-strings
> @@ -23,10 +23,12 @@ OPTSTR_ARCH arch
> OPTSTR_TUNE tune
>
> STR_CPU_NATIVE native
> +STR_CPU_LOONGARCH32 loongarch32
> STR_CPU_LOONGARCH64 loongarch64
> STR_CPU_LA464 la464
>
> # Base architecture
> +STR_ISA_BASE_LA32V100 la32
> STR_ISA_BASE_LA64V100 la64
>
> # -mfpu
> @@ -42,6 +44,9 @@ OPTSTR_DOUBLE_FLOAT double-float
>
> # -mabi=
> OPTSTR_ABI_BASE abi
> +STR_ABI_BASE_ILP32D ilp32d
> +STR_ABI_BASE_ILP32F ilp32f
> +STR_ABI_BASE_ILP32S ilp32s
> STR_ABI_BASE_LP64D lp64d
> STR_ABI_BASE_LP64F lp64f
> STR_ABI_BASE_LP64S lp64s
> diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
> index 4b9b4ac273e..47f77345890 100644
> --- a/gcc/config/loongarch/genopts/loongarch.opt.in
> +++ b/gcc/config/loongarch/genopts/loongarch.opt.in
> @@ -85,6 +85,9 @@ LoongArch CPU types:
> EnumValue
> Enum(cpu_type) String(@@STR_CPU_NATIVE@@) Value(CPU_NATIVE)
>
> +EnumValue
> +Enum(cpu_type) String(@@STR_CPU_LOONGARCH32@@) Value(CPU_LOONGARCH32)
> +
> EnumValue
> Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64)
>
> @@ -108,6 +111,15 @@ Enum
> Name(abi_base) Type(int)
> Base ABI types for LoongArch:
>
> +EnumValue
> +Enum(abi_base) String(@@STR_ABI_BASE_ILP32D@@) Value(ABI_BASE_ILP32D)
> +
> +EnumValue
> +Enum(abi_base) String(@@STR_ABI_BASE_ILP32F@@) Value(ABI_BASE_ILP32F)
> +
> +EnumValue
> +Enum(abi_base) String(@@STR_ABI_BASE_ILP32S@@) Value(ABI_BASE_ILP32S)
> +
> EnumValue
> Enum(abi_base) String(@@STR_ABI_BASE_LP64D@@) Value(ABI_BASE_LP64D)
>
> diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h
> index fa1a5211419..bf6d3a4fe98 100644
> --- a/gcc/config/loongarch/gnu-user.h
> +++ b/gcc/config/loongarch/gnu-user.h
> @@ -34,6 +34,9 @@ along with GCC; see the file COPYING3. If not see
> "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1"
>
> #define MUSL_ABI_SPEC \
> + "%{mabi=ilp32d:-ilp32d}" \
> + "%{mabi=ilp32f:-ilp32f}" \
> + "%{mabi=ilp32s:-ilp32s}" \
> "%{mabi=lp64d:-lp64d}" \
> "%{mabi=lp64f:-lp64f}" \
> "%{mabi=lp64s:-lp64s}"
> diff --git a/gcc/config/loongarch/linux.h b/gcc/config/loongarch/linux.h
> index 9059d244190..45aa3531cd3 100644
> --- a/gcc/config/loongarch/linux.h
> +++ b/gcc/config/loongarch/linux.h
> @@ -23,7 +23,13 @@ along with GCC; see the file COPYING3. If not see
>
> #if defined(LA_DISABLE_MULTILIB) && defined(LA_DISABLE_MULTIARCH)
>
> - #if DEFAULT_ABI_BASE == ABI_BASE_LP64D
> + #if DEFAULT_ABI_BASE == ABI_BASE_ILP32D
> + #define ABI_LIBDIR "lib32"
> + #elif DEFAULT_ABI_BASE == ABI_BASE_ILP32F
> + #define ABI_LIBDIR "lib32/f32"
> + #elif DEFAULT_ABI_BASE == ABI_BASE_ILP32S
> + #define ABI_LIBDIR "lib32/sf"
> + #elif DEFAULT_ABI_BASE == ABI_BASE_LP64D
> #define ABI_LIBDIR "lib64"
> #elif DEFAULT_ABI_BASE == ABI_BASE_LP64F
> #define ABI_LIBDIR "lib64/f32"
> diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc
> index 67911b78f28..e3783a325d7 100644
> --- a/gcc/config/loongarch/loongarch-c.cc
> +++ b/gcc/config/loongarch/loongarch-c.cc
> @@ -65,12 +65,24 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
> LARCH_CPP_SET_PROCESSOR ("_LOONGARCH_TUNE", LARCH_ACTUAL_TUNE);
>
> /* Base architecture / ABI. */
> + if (TARGET_32BIT)
> + {
> + builtin_define ("__loongarch_grlen=32");
> + builtin_define ("__loongarch32");
> + }
> if (TARGET_64BIT)
> {
> builtin_define ("__loongarch_grlen=64");
> builtin_define ("__loongarch64");
> }
>
> + if (TARGET_ABI_ILP32)
> + {
> + builtin_define ("_ABILP32=3");
> + builtin_define ("_LOONGARCH_SIM=_ABILP32");
> + builtin_define ("__loongarch_ilp32");
> + }
> +
> if (TARGET_ABI_LP64)
> {
> builtin_define ("_ABILP64=3");
> diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
> index 6729c857f7c..5ae8bd24c9f 100644
> --- a/gcc/config/loongarch/loongarch-def.c
> +++ b/gcc/config/loongarch/loongarch-def.c
> @@ -40,12 +40,17 @@ along with GCC; see the file COPYING3. If not see
> const char*
> loongarch_cpu_strings[N_TUNE_TYPES] = {
> [CPU_NATIVE] = STR_CPU_NATIVE,
> + [CPU_LOONGARCH32] = STR_CPU_LOONGARCH32,
> [CPU_LOONGARCH64] = STR_CPU_LOONGARCH64,
> [CPU_LA464] = STR_CPU_LA464,
> };
>
> struct loongarch_isa
> loongarch_cpu_default_isa[N_ARCH_TYPES] = {
> + [CPU_LOONGARCH32] = {
> + .base = ISA_BASE_LA32V100,
> + .fpu = ISA_EXT_FPU32,
> + },
> [CPU_LOONGARCH64] = {
> .base = ISA_BASE_LA64V100,
> .fpu = ISA_EXT_FPU64,
> @@ -58,6 +63,12 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = {
>
> struct loongarch_cache
> loongarch_cpu_cache[N_TUNE_TYPES] = {
> + [CPU_LOONGARCH32] = {
> + .l1d_line_size = 64,
> + .l1d_size = 64,
> + .l2d_size = 256,
> + .simultaneous_prefetches = 4,
> + },
> [CPU_LOONGARCH64] = {
> .l1d_line_size = 64,
> .l1d_size = 64,
> @@ -74,6 +85,10 @@ loongarch_cpu_cache[N_TUNE_TYPES] = {
>
> struct loongarch_align
> loongarch_cpu_align[N_TUNE_TYPES] = {
> + [CPU_LOONGARCH32] = {
> + .function = "32",
> + .label = "16",
> + },
> [CPU_LOONGARCH64] = {
> .function = "32",
> .label = "16",
> @@ -94,6 +109,9 @@ loongarch_cpu_rtx_cost_data[N_TUNE_TYPES] = {
> [CPU_NATIVE] = {
> DEFAULT_COSTS
> },
> + [CPU_LOONGARCH32] = {
> + DEFAULT_COSTS
> + },
> [CPU_LOONGARCH64] = {
> DEFAULT_COSTS
> },
> @@ -121,6 +139,7 @@ loongarch_rtx_cost_optimize_size = {
> int
> loongarch_cpu_issue_rate[N_TUNE_TYPES] = {
> [CPU_NATIVE] = 4,
> + [CPU_LOONGARCH32] = 4,
> [CPU_LOONGARCH64] = 4,
> [CPU_LA464] = 4,
> };
> @@ -128,6 +147,7 @@ loongarch_cpu_issue_rate[N_TUNE_TYPES] = {
> int
> loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
> [CPU_NATIVE] = 4,
> + [CPU_LOONGARCH32] = 4,
> [CPU_LOONGARCH64] = 4,
> [CPU_LA464] = 4,
> };
> @@ -139,6 +159,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
>
> const char*
> loongarch_isa_base_strings[N_ISA_BASE_TYPES] = {
> + [ISA_BASE_LA32V100] = STR_ISA_BASE_LA32V100,
> [ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100,
> };
>
> @@ -151,6 +172,9 @@ loongarch_isa_ext_strings[N_ISA_EXT_TYPES] = {
>
> const char*
> loongarch_abi_base_strings[N_ABI_BASE_TYPES] = {
> + [ABI_BASE_ILP32D] = STR_ABI_BASE_ILP32D,
> + [ABI_BASE_ILP32F] = STR_ABI_BASE_ILP32F,
> + [ABI_BASE_ILP32S] = STR_ABI_BASE_ILP32S,
> [ABI_BASE_LP64D] = STR_ABI_BASE_LP64D,
> [ABI_BASE_LP64F] = STR_ABI_BASE_LP64F,
> [ABI_BASE_LP64S] = STR_ABI_BASE_LP64S,
> @@ -182,6 +206,15 @@ loongarch_switch_strings[] = {
> /* ABI-related definitions. */
> const struct loongarch_isa
> abi_minimal_isa[N_ABI_BASE_TYPES][N_ABI_EXT_TYPES] = {
> + [ABI_BASE_ILP32D] = {
> + [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_FPU64},
> + },
> + [ABI_BASE_ILP32F] = {
> + [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_FPU32},
> + },
> + [ABI_BASE_ILP32S] = {
> + [ABI_EXT_BASE] = {.base = ISA_BASE_LA32V100, .fpu = ISA_EXT_NOFPU},
> + },
> [ABI_BASE_LP64D] = {
> [ABI_EXT_BASE] = {.base = ISA_BASE_LA64V100, .fpu = ISA_EXT_FPU64},
> },
> diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
> index fb8bb88eb52..6c4b9fa3385 100644
> --- a/gcc/config/loongarch/loongarch-def.h
> +++ b/gcc/config/loongarch/loongarch-def.h
> @@ -54,8 +54,9 @@ extern "C" {
>
> /* enum isa_base */
> extern const char* loongarch_isa_base_strings[];
> -#define ISA_BASE_LA64V100 0
> -#define N_ISA_BASE_TYPES 1
> +#define ISA_BASE_LA32V100 0
> +#define ISA_BASE_LA64V100 1
> +#define N_ISA_BASE_TYPES 2
>
> /* enum isa_ext_* */
> extern const char* loongarch_isa_ext_strings[];
> @@ -67,10 +68,13 @@ extern const char* loongarch_isa_ext_strings[];
>
> /* enum abi_base */
> extern const char* loongarch_abi_base_strings[];
> -#define ABI_BASE_LP64D 0
> -#define ABI_BASE_LP64F 1
> -#define ABI_BASE_LP64S 2
> -#define N_ABI_BASE_TYPES 3
> +#define ABI_BASE_ILP32D 0
> +#define ABI_BASE_ILP32F 1
> +#define ABI_BASE_ILP32S 2
> +#define ABI_BASE_LP64D 3
> +#define ABI_BASE_LP64F 4
> +#define ABI_BASE_LP64S 5
> +#define N_ABI_BASE_TYPES 6
>
> /* enum abi_ext */
> extern const char* loongarch_abi_ext_strings[];
> @@ -132,10 +136,11 @@ struct loongarch_target
> /* CPU properties. */
> /* index */
> #define CPU_NATIVE 0
> -#define CPU_LOONGARCH64 1
> -#define CPU_LA464 2
> -#define N_ARCH_TYPES 3
> -#define N_TUNE_TYPES 3
> +#define CPU_LOONGARCH32 1
> +#define CPU_LOONGARCH64 2
> +#define CPU_LA464 3
> +#define N_ARCH_TYPES 4
> +#define N_TUNE_TYPES 4
>
> /* parallel tables. */
> extern const char* loongarch_cpu_strings[];
> diff --git a/gcc/config/loongarch/loongarch-driver.h b/gcc/config/loongarch/loongarch-driver.h
> index ba8817a4621..0a22acab803 100644
> --- a/gcc/config/loongarch/loongarch-driver.h
> +++ b/gcc/config/loongarch/loongarch-driver.h
> @@ -58,9 +58,13 @@ driver_get_normalized_m_opts (int argc, const char **argv);
>
> /* ABI spec strings. */
> #define ABI_GRLEN_SPEC \
> + "%{mabi=ilp32*:32}" \
> "%{mabi=lp64*:64}" \
>
> #define ABI_SPEC \
> + "%{mabi=ilp32d:ilp32d}" \
> + "%{mabi=ilp32f:ilp32f}" \
> + "%{mabi=ilp32s:ilp32s}" \
> "%{mabi=lp64d:lp64d}" \
> "%{mabi=lp64f:lp64f}" \
> "%{mabi=lp64s:lp64s}" \
> diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
> index a52e25236ea..9fc0bbbcb6e 100644
> --- a/gcc/config/loongarch/loongarch-opts.cc
> +++ b/gcc/config/loongarch/loongarch-opts.cc
> @@ -36,6 +36,9 @@ struct loongarch_target la_target;
> #define ABI_COUNT (sizeof(abi_priority_list)/sizeof(struct loongarch_abi))
> static const struct loongarch_abi
> abi_priority_list[] = {
> + {ABI_BASE_ILP32D, ABI_EXT_BASE},
> + {ABI_BASE_ILP32F, ABI_EXT_BASE},
> + {ABI_BASE_ILP32S, ABI_EXT_BASE},
> {ABI_BASE_LP64D, ABI_EXT_BASE},
> {ABI_BASE_LP64F, ABI_EXT_BASE},
> {ABI_BASE_LP64S, ABI_EXT_BASE},
> @@ -410,17 +413,23 @@ isa_default_abi (const struct loongarch_isa *isa)
> switch (isa->fpu)
> {
> case ISA_EXT_FPU64:
> - if (isa->base == ISA_BASE_LA64V100)
> + if (isa->base == ISA_BASE_LA32V100)
> + abi.base = ABI_BASE_ILP32D;
> + else if (isa->base == ISA_BASE_LA64V100)
> abi.base = ABI_BASE_LP64D;
> break;
>
> case ISA_EXT_FPU32:
> - if (isa->base == ISA_BASE_LA64V100)
> + if (isa->base == ISA_BASE_LA32V100)
> + abi.base = ABI_BASE_ILP32F;
> + else if (isa->base == ISA_BASE_LA64V100)
> abi.base = ABI_BASE_LP64F;
> break;
>
> case ISA_EXT_NOFPU:
> - if (isa->base == ISA_BASE_LA64V100)
> + if (isa->base == ISA_BASE_LA32V100)
> + abi.base = ABI_BASE_ILP32S;
> + else if (isa->base == ISA_BASE_LA64V100)
> abi.base = ABI_BASE_LP64S;
> break;
>
> @@ -439,6 +448,8 @@ isa_base_compat_p (const struct loongarch_isa *set1,
> {
> switch (set2->base)
> {
> + case ISA_BASE_LA32V100:
> + return (set1->base == ISA_BASE_LA32V100);
> case ISA_BASE_LA64V100:
> return (set1->base == ISA_BASE_LA64V100);
>
> @@ -487,6 +498,11 @@ abi_default_cpu_arch (struct loongarch_abi abi)
> {
> switch (abi.base)
> {
> + case ABI_BASE_ILP32D:
> + case ABI_BASE_ILP32F:
> + case ABI_BASE_ILP32S:
> + if (abi.ext == ABI_EXT_BASE)
> + return CPU_LOONGARCH32;
> case ABI_BASE_LP64D:
> case ABI_BASE_LP64F:
> case ABI_BASE_LP64S:
> diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
> index b1ff54426e4..c8794dff0ad 100644
> --- a/gcc/config/loongarch/loongarch-opts.h
> +++ b/gcc/config/loongarch/loongarch-opts.h
> @@ -51,15 +51,25 @@ loongarch_config_target (struct loongarch_target *target,
> #define TARGET_CMODEL_EXTREME (la_target.cmodel == CMODEL_EXTREME)
>
> #define TARGET_HARD_FLOAT (la_target.isa.fpu != ISA_EXT_NOFPU)
> -#define TARGET_HARD_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D \
> +#define TARGET_HARD_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32D \
> + || la_target.abi.base == ABI_BASE_ILP32F \
> + || la_target.abi.base == ABI_BASE_LP64D \
> || la_target.abi.base == ABI_BASE_LP64F)
>
> #define TARGET_SOFT_FLOAT (la_target.isa.fpu == ISA_EXT_NOFPU)
> -#define TARGET_SOFT_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64S)
> +#define TARGET_SOFT_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32S \
> + || la_target.abi.base == ABI_BASE_LP64S)
> #define TARGET_SINGLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU32)
> -#define TARGET_SINGLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64F)
> +#define TARGET_SINGLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32F \
> + || la_target.abi.base == ABI_BASE_LP64F)
> #define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64)
> -#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D)
> +#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_ILP32D \
> + || la_target.abi.base == ABI_BASE_LP64D)
> +
> +#define TARGET_32BIT (la_target.isa.base == ISA_BASE_LA32V100)
> +#define TARGET_ABI_ILP32 (la_target.abi.base == ABI_BASE_ILP32D \
> + || la_target.abi.base == ABI_BASE_ILP32F \
> + || la_target.abi.base == ABI_BASE_ILP32S)
>
> #define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100)
> #define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \
> @@ -78,9 +88,11 @@ loongarch_config_target (struct loongarch_target *target,
> ? (la_target.cpu_native) : (CPU_NATIVE)) \
> : (la_target.cpu_tune))
>
> +#define TARGET_ARCH_LOONGARCH32 (LARCH_ACTUAL_ARCH == CPU_LOONGARCH32)
> #define TARGET_ARCH_LOONGARCH64 (LARCH_ACTUAL_ARCH == CPU_LOONGARCH64)
> #define TARGET_ARCH_LA464 (LARCH_ACTUAL_ARCH == CPU_LA464)
>
> +#define TARGET_TUNE_LOONGARCH32 (LARCH_ACTUAL_TUNE == CPU_LOONGARCH32)
> #define TARGET_TUNE_LOONGARCH64 (LARCH_ACTUAL_TUNE == CPU_LOONGARCH64)
> #define TARGET_TUNE_LA464 (LARCH_ACTUAL_TUNE == CPU_LA464)
>
> diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
> index af2e82a321f..60588da45e2 100644
> --- a/gcc/config/loongarch/loongarch-str.h
> +++ b/gcc/config/loongarch/loongarch-str.h
> @@ -27,9 +27,11 @@ along with GCC; see the file COPYING3. If not see
> #define OPTSTR_TUNE "tune"
>
> #define STR_CPU_NATIVE "native"
> +#define STR_CPU_LOONGARCH32 "loongarch32"
> #define STR_CPU_LOONGARCH64 "loongarch64"
> #define STR_CPU_LA464 "la464"
>
> +#define STR_ISA_BASE_LA32V100 "la32"
> #define STR_ISA_BASE_LA64V100 "la64"
>
> #define OPTSTR_ISA_EXT_FPU "fpu"
> @@ -43,6 +45,9 @@ along with GCC; see the file COPYING3. If not see
> #define OPTSTR_DOUBLE_FLOAT "double-float"
>
> #define OPTSTR_ABI_BASE "abi"
> +#define STR_ABI_BASE_ILP32D "ilp32d"
> +#define STR_ABI_BASE_ILP32F "ilp32f"
> +#define STR_ABI_BASE_ILP32S "ilp32s"
> #define STR_ABI_BASE_LP64D "lp64d"
> #define STR_ABI_BASE_LP64F "lp64f"
> #define STR_ABI_BASE_LP64S "lp64s"
> diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
> index 5b8b93eb24b..ff7904d49d5 100644
> --- a/gcc/config/loongarch/loongarch.cc
> +++ b/gcc/config/loongarch/loongarch.cc
> @@ -6208,7 +6208,7 @@ loongarch_option_override_internal (struct gcc_options *opts)
> la_opt_cpu_arch, la_opt_cpu_tune, la_opt_fpu,
> la_opt_abi_base, la_opt_abi_ext, la_opt_cmodel, 0);
>
> - if (TARGET_ABI_LP64)
> + if (TARGET_ABI_LP64 || TARGET_ABI_ILP32)
> flag_pcc_struct_return = 0;
>
> /* Decide which rtx_costs structure to use. */
> diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
> index 68018ade73f..2cd36c5e8fa 100644
> --- a/gcc/config/loongarch/loongarch.opt
> +++ b/gcc/config/loongarch/loongarch.opt
> @@ -92,6 +92,9 @@ LoongArch CPU types:
> EnumValue
> Enum(cpu_type) String(native) Value(CPU_NATIVE)
>
> +EnumValue
> +Enum(cpu_type) String(loongarch32) Value(CPU_LOONGARCH32)
> +
> EnumValue
> Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
>
> @@ -115,6 +118,15 @@ Enum
> Name(abi_base) Type(int)
> Base ABI types for LoongArch:
>
> +EnumValue
> +Enum(abi_base) String(ilp32d) Value(ABI_BASE_ILP32D)
> +
> +EnumValue
> +Enum(abi_base) String(ilp32f) Value(ABI_BASE_ILP32F)
> +
> +EnumValue
> +Enum(abi_base) String(ilp32s) Value(ABI_BASE_ILP32S)
> +
> EnumValue
> Enum(abi_base) String(lp64d) Value(ABI_BASE_LP64D)
>
> diff --git a/gcc/config/loongarch/t-linux b/gcc/config/loongarch/t-linux
> index e40da179203..1718c3e11a2 100644
> --- a/gcc/config/loongarch/t-linux
> +++ b/gcc/config/loongarch/t-linux
> @@ -17,8 +17,8 @@
> # <http://www.gnu.org/licenses/>.
>
> # Multilib
> -MULTILIB_OPTIONS = mabi=lp64d/mabi=lp64f/mabi=lp64s
> -MULTILIB_DIRNAMES = base/lp64d base/lp64f base/lp64s
> +MULTILIB_OPTIONS = mabi=ilp32d/mabi=ilp32f/mabi=ilp32s/mabi=lp64d/mabi=lp64f/mabi=lp64s
> +MULTILIB_DIRNAMES = base/ilp32d base/ilp32f base/ilp32s base/lp64d base/lp64f base/lp64s
>
> # The GCC driver always gets all abi-related options on the command line.
> # (see loongarch-driver.c:driver_get_normalized_m_opts)
> @@ -38,6 +38,18 @@ endif
> # Don't define MULTILIB_OSDIRNAMES if multilib is disabled.
> ifeq ($(filter LA_DISABLE_MULTILIB,$(tm_defines)),)
>
> + MULTILIB_OSDIRNAMES = \
> + mabi.ilp32d=../lib32$\
> + $(call if_multiarch,:loongarch32-linux-gnu)
> +
> + MULTILIB_OSDIRNAMES += \
> + mabi.ilp32f=../lib32/f32$\
> + $(call if_multiarch,:loongarch32-linux-gnuf32)
> +
> + MULTILIB_OSDIRNAMES += \
> + mabi.ilp32s=../lib32/sf$\
> + $(call if_multiarch,:loongarch32-linux-gnusf)
> +
> MULTILIB_OSDIRNAMES = \
> mabi.lp64d=../lib64$\
> $(call if_multiarch,:loongarch64-linux-gnu)
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/9] LoongArch: Fix default ISA setting
2023-08-06 12:49 ` [PATCH 2/9] LoongArch: Fix default ISA setting Jiajie Chen
@ 2023-08-09 3:38 ` Xi Ruoyao
0 siblings, 0 replies; 11+ messages in thread
From: Xi Ruoyao @ 2023-08-09 3:38 UTC (permalink / raw)
To: Jiajie Chen, gcc-patches
On Sun, 2023-08-06 at 20:49 +0800, Jiajie Chen via Gcc-patches wrote:
> When loongarch_arch_target is called, la_target has not been
> initialized, thus the macro LARCH_ACTUAL_ARCH always equals to zero.
>
> This commit fixes by expanding the macro and reading the latest value.
> It permits -march=loongarch64 when the default target is loongarch32 and
> vice versa.
>
> gcc/ChangeLog:
>
> * config/loongarch/loongarch-opts.cc (loongarch_config_target):
> Fix -march detection.
Nit: the first letter 'F' of the second line should align with '*' of
the first line, not 'c'.
/* snip */
> diff --git a/gcc/testsuite/gcc.target/loongarch/arch-3.c b/gcc/testsuite/gcc.target/loongarch/arch-3.c
> new file mode 100644
> index 00000000000..543b93883bd
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/loongarch/arch-3.c
> @@ -0,0 +1,6 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=loongarch64 -mabi=ilp32d" } */
> +int foo()
> +{
> +}
> +/* { dg-error "unable to implement ABI 'ilp32d' with instruction set 'la64/fpu64'" "" { target *-*-* } 0 } */
This is just wrong. It's absolutely possible to implement ilp32d with
la64/fpu64. LoongArch *.w instructions are always 32-bit operations, no
matter on LA32 or LA64. They are different from RISC-V where many
instructions operate on 32-bit integers on RV32 but 64-bit integers on
RV64.
If you don't want to spend your time to implement it you should use
`sorry ("%<-mabi=ilp32d%> is not implemented for la64");` instead.
Yes, I know there is some (mis)uses of TARGET_64BIT in the
config/loongarch code where TARGET_ABI_LP64 should be actually used
instead. They are bugs preventing us from implementing -mabi=ilp32d -
march=loongarch64 and they should be fixed. They are not our excuse to
blindly "simulate" what RISC-V has.
--
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-08-09 3:38 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-06 12:49 [PATCH 1/9] LoongArch: Introduce loongarch32 target Jiajie Chen
2023-08-06 12:49 ` [PATCH 2/9] LoongArch: Fix default ISA setting Jiajie Chen
2023-08-09 3:38 ` Xi Ruoyao
2023-08-06 12:50 ` [PATCH 3/9] LoongArch: Fix SI division for loongarch32 target Jiajie Chen
2023-08-06 12:50 ` [PATCH 4/9] LoongArch: Fix movgr2frh.w operand order Jiajie Chen
2023-08-06 12:50 ` [PATCH 5/9] LoongArch: Fix 64-bit move for loongarch32 target Jiajie Chen
2023-08-06 12:50 ` [PATCH 6/9] LoongArch: Fix 64-bit immediate " Jiajie Chen
2023-08-06 12:50 ` [PATCH 7/9] LoongArch: Fix signed 32-bit overflow " Jiajie Chen
2023-08-06 12:50 ` [PATCH 8/9] LoongArch: Do not emit SF/DF <-> DI conversion in loongarch32 Jiajie Chen
2023-08-06 12:50 ` [PATCH 9/9] LoongArch: Add: Add -march=loongarch64 to tests with -mabi=lp64d Jiajie Chen
2023-08-09 2:50 ` [PATCH 1/9] LoongArch: Introduce loongarch32 target Chenghua Xu
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