* [PATCH] RISC-V: Support VLS basic operation auto-vectorization
@ 2023-08-07 9:27 Juzhe-Zhong
2023-08-07 19:46 ` Robin Dapp
0 siblings, 1 reply; 4+ messages in thread
From: Juzhe-Zhong @ 2023-08-07 9:27 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, kito.cheng, jeffreyalaw, rdapp.gcc, Juzhe-Zhong
This patch support VLS modes auto-vectorization to enhance VLA auto-vectorization
when niters is known.
Consider this following case:
#include <stdint.h>
#define DEF_OP_VV(PREFIX, NUM, TYPE, OP) \
void __attribute__ ((noinline, noclone)) \
PREFIX##_##TYPE##NUM (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c) \
{ \
for (int i = 0; i < NUM; ++i) \
a[i] = b[i] OP c[i]; \
}
DEF_OP_VV (plus, 16, int8_t, +)
Before this patch:
plus_int8_t16(signed char*, signed char*, signed char*):
li a5,16
csrr a4,vlenb
bleu a5,a4,.L2
mv a5,a4
.L2:
vsetvli zero,a5,e8,m1,ta,ma
vle8.v v2,0(a1)
vle8.v v1,0(a2)
vsetvli a4,zero,e8,m1,ta,ma
vadd.vv v1,v1,v2
vsetvli zero,a5,e8,m1,ta,ma
vse8.v v1,0(a0)
ret
After this patch:
plus_int8_t16:
vsetivli zero,16,e8,m1,ta,ma
vle8.v v1,0(a2)
vle8.v v2,0(a1)
vadd.vv v1,v1,v2
vse8.v v1,0(a0)
ret
gcc/ChangeLog:
* config/riscv/autovec-vls.md (<optab><mode>3): Add VLS modes.
* config/riscv/vector-iterators.md: Ditto.
* config/riscv/vector.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Add basic operations.
* gcc.target/riscv/rvv/autovec/vls/and-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/and-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/and-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/div-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/ior-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/ior-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/ior-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/max-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/min-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/minus-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/minus-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/minus-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mod-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/mult-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/plus-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/plus-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/plus-3.c: New test.
---
gcc/config/riscv/autovec-vls.md | 23 +++
gcc/config/riscv/vector-iterators.md | 93 ++++++++++
gcc/config/riscv/vector.md | 166 +++++++++---------
.../gcc.target/riscv/rvv/autovec/vls/and-1.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/and-2.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/and-3.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/def.h | 48 +++++
.../gcc.target/riscv/rvv/autovec/vls/div-1.c | 58 ++++++
.../gcc.target/riscv/rvv/autovec/vls/ior-1.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/ior-2.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/ior-3.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/max-1.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/min-1.c | 57 ++++++
.../riscv/rvv/autovec/vls/minus-1.c | 57 ++++++
.../riscv/rvv/autovec/vls/minus-2.c | 57 ++++++
.../riscv/rvv/autovec/vls/minus-3.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/mod-1.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/mult-1.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/plus-1.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/plus-2.c | 57 ++++++
.../gcc.target/riscv/rvv/autovec/vls/plus-3.c | 57 ++++++
21 files changed, 1217 insertions(+), 83 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
index 1a64dfdd91e..4a9f8c8d0bc 100644
--- a/gcc/config/riscv/autovec-vls.md
+++ b/gcc/config/riscv/autovec-vls.md
@@ -158,3 +158,26 @@
DONE;
}
)
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] Binary operations
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vadd.vv/vsub.vv/...
+;; - vadd.vi/vsub.vi/...
+;; -------------------------------------------------------------------------
+
+(define_insn_and_split "<optab><mode>3"
+ [(set (match_operand:VLSI 0 "register_operand")
+ (any_int_binop_no_shift:VLSI
+ (match_operand:VLSI 1 "<binop_rhs1_predicate>")
+ (match_operand:VLSI 2 "<binop_rhs2_predicate>")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
+ riscv_vector::RVV_BINOP, operands);
+ DONE;
+})
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 6a2cfa5bf37..14829989e09 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -543,6 +543,51 @@
RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
])
+(define_mode_iterator V_VLSI_QHS [
+ RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
+
+ RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
+
+ RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
+
+ (V1QI "TARGET_VECTOR_VLS")
+ (V2QI "TARGET_VECTOR_VLS")
+ (V4QI "TARGET_VECTOR_VLS")
+ (V8QI "TARGET_VECTOR_VLS")
+ (V16QI "TARGET_VECTOR_VLS")
+ (V32QI "TARGET_VECTOR_VLS")
+ (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1HI "TARGET_VECTOR_VLS")
+ (V2HI "TARGET_VECTOR_VLS")
+ (V4HI "TARGET_VECTOR_VLS")
+ (V8HI "TARGET_VECTOR_VLS")
+ (V16HI "TARGET_VECTOR_VLS")
+ (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1SI "TARGET_VECTOR_VLS")
+ (V2SI "TARGET_VECTOR_VLS")
+ (V4SI "TARGET_VECTOR_VLS")
+ (V8SI "TARGET_VECTOR_VLS")
+ (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+])
+
(define_mode_iterator VI_D [
(RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
(RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
@@ -2292,3 +2337,51 @@
(V128DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
(V256DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
(V512DF "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")])
+
+(define_mode_iterator VLSI [
+ (V1QI "TARGET_VECTOR_VLS")
+ (V2QI "TARGET_VECTOR_VLS")
+ (V4QI "TARGET_VECTOR_VLS")
+ (V8QI "TARGET_VECTOR_VLS")
+ (V16QI "TARGET_VECTOR_VLS")
+ (V32QI "TARGET_VECTOR_VLS")
+ (V64QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V128QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V256QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V512QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V1024QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V2048QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V4096QI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1HI "TARGET_VECTOR_VLS")
+ (V2HI "TARGET_VECTOR_VLS")
+ (V4HI "TARGET_VECTOR_VLS")
+ (V8HI "TARGET_VECTOR_VLS")
+ (V16HI "TARGET_VECTOR_VLS")
+ (V32HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V64HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V128HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V256HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V512HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V1024HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V2048HI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1SI "TARGET_VECTOR_VLS")
+ (V2SI "TARGET_VECTOR_VLS")
+ (V4SI "TARGET_VECTOR_VLS")
+ (V8SI "TARGET_VECTOR_VLS")
+ (V16SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 64")
+ (V32SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 128")
+ (V64SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 256")
+ (V128SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 512")
+ (V256SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 1024")
+ (V512SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 2048")
+ (V1024SI "TARGET_VECTOR_VLS && TARGET_MIN_VLEN >= 4096")
+ (V1DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
+ (V2DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
+ (V4DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64")
+ (V8DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
+ (V16DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
+ (V32DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
+ (V64DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
+ (V128DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
+ (V256DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
+ (V512DI "TARGET_VECTOR_VLS && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")])
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 3674074b95e..9b51e0089d7 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -2228,8 +2228,8 @@
;; -------------------------------------------------------------------------------
(define_insn "@pred_<optab><mode>"
- [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
@@ -2238,10 +2238,10 @@
(match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_int_binop:VI
- (match_operand:VI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
- (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
- (match_operand:VI 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
+ (any_int_binop:V_VLSI
+ (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
+ (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
+ (match_operand:V_VLSI 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
"TARGET_VECTOR"
"@
v<insn>.vv\t%0,%3,%4%p1
@@ -2264,8 +2264,8 @@
;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the
;; scalar mode is inner mode of the RVV mode for other vx patterns.
(define_insn "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI 0 "register_operand" "=vd,vd, vr, vr,vd,vd, vr, vr")
- (if_then_else:VI
+ [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr,vd,vd, vr, vr")
+ (if_then_else:V_VLSI
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK,rK,rK, rK, rK")
@@ -2274,10 +2274,10 @@
(match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_shift:VI
- (match_operand:VI 3 "register_operand" "vr,vr, vr, vr,vr,vr, vr, vr")
+ (any_shift:V_VLSI
+ (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr,vr,vr, vr, vr")
(match_operand 4 "pmode_reg_or_uimm5_operand" " r, r, r, r, K, K, K, K"))
- (match_operand:VI 2 "vector_merge_operand" "vu, 0, vu, 0,vu, 0, vu, 0")))]
+ (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0,vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.v%o4\t%0,%3,%4%p1"
[(set_attr "type" "vshift")
@@ -2285,8 +2285,8 @@
;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
(define_insn "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_QHS
+ [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2295,19 +2295,19 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_commutative_binop:VI_QHS
- (vec_duplicate:VI_QHS
+ (any_commutative_binop:V_VLSI_QHS
+ (vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
- (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr"))
- (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
+ (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_QHS
+ [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2316,19 +2316,19 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_non_commutative_binop:VI_QHS
- (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr")
- (vec_duplicate:VI_QHS
+ (any_non_commutative_binop:V_VLSI_QHS
+ (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr")
+ (vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
- (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
(define_insn "@pred_sub<mode>_reverse_scalar"
- [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_QHS
+ [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_QHS
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2337,11 +2337,11 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI_QHS
- (vec_duplicate:VI_QHS
+ (minus:V_VLSI_QHS
+ (vec_duplicate:V_VLSI_QHS
(match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
- (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr"))
- (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
+ (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vrsub.vx\t%0,%3,%z4%p1"
[(set_attr "type" "vialu")
@@ -2350,8 +2350,8 @@
;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
;; we need to deal with SEW = 64 in RV32 system.
(define_expand "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 5 "vector_length_operand")
@@ -2360,11 +2360,11 @@
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_commutative_binop:VI_D
- (vec_duplicate:VI_D
+ (any_commutative_binop:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "reg_or_int_operand"))
- (match_operand:VI_D 3 "register_operand"))
- (match_operand:VI_D 2 "vector_merge_operand")))]
+ (match_operand:V_VLSI_D 3 "register_operand"))
+ (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
"TARGET_VECTOR"
{
if (riscv_vector::sew64_scalar_helper (
@@ -2382,8 +2382,8 @@
})
(define_insn "*pred_<optab><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2392,19 +2392,19 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_commutative_binop:VI_D
- (vec_duplicate:VI_D
+ (any_commutative_binop:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
- (match_operand:VI_D 3 "register_operand" "vr,vr, vr, vr"))
- (match_operand:VI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
(define_insn "*pred_<optab><mode>_extended_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2413,20 +2413,20 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_commutative_binop:VI_D
- (vec_duplicate:VI_D
+ (any_commutative_binop:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
- (match_operand:VI_D 3 "register_operand" "vr,vr, vr, vr"))
- (match_operand:VI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
(define_expand "@pred_<optab><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 5 "vector_length_operand")
@@ -2435,11 +2435,11 @@
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_non_commutative_binop:VI_D
- (match_operand:VI_D 3 "register_operand")
- (vec_duplicate:VI_D
+ (any_non_commutative_binop:V_VLSI_D
+ (match_operand:V_VLSI_D 3 "register_operand")
+ (vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "reg_or_int_operand")))
- (match_operand:VI_D 2 "vector_merge_operand")))]
+ (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
"TARGET_VECTOR"
{
if (riscv_vector::sew64_scalar_helper (
@@ -2457,8 +2457,8 @@
})
(define_insn "*pred_<optab><mode>_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2467,19 +2467,19 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_non_commutative_binop:VI_D
- (match_operand:VI_D 3 "register_operand" "vr,vr, vr, vr")
- (vec_duplicate:VI_D
+ (any_non_commutative_binop:V_VLSI_D
+ (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
+ (vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
- (match_operand:VI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
(define_insn "*pred_<optab><mode>_extended_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2488,20 +2488,20 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (any_non_commutative_binop:VI_D
- (match_operand:VI_D 3 "register_operand" "vr,vr, vr, vr")
- (vec_duplicate:VI_D
+ (any_non_commutative_binop:V_VLSI_D
+ (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
+ (vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
- (match_operand:VI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"v<insn>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "<int_binop_insn_type>")
(set_attr "mode" "<MODE>")])
(define_expand "@pred_sub<mode>_reverse_scalar"
- [(set (match_operand:VI_D 0 "register_operand")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand")
(match_operand 5 "vector_length_operand")
@@ -2510,11 +2510,11 @@
(match_operand 8 "const_int_operand")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI_D
- (vec_duplicate:VI_D
+ (minus:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "reg_or_int_operand"))
- (match_operand:VI_D 3 "register_operand"))
- (match_operand:VI_D 2 "vector_merge_operand")))]
+ (match_operand:V_VLSI_D 3 "register_operand"))
+ (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
"TARGET_VECTOR"
{
if (riscv_vector::sew64_scalar_helper (
@@ -2532,8 +2532,8 @@
})
(define_insn "*pred_sub<mode>_reverse_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2542,19 +2542,19 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI_D
- (vec_duplicate:VI_D
+ (minus:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
- (match_operand:VI_D 3 "register_operand" "vr,vr, vr, vr"))
- (match_operand:VI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vrsub.vx\t%0,%3,%z4%p1"
[(set_attr "type" "vialu")
(set_attr "mode" "<MODE>")])
(define_insn "*pred_sub<mode>_extended_reverse_scalar"
- [(set (match_operand:VI_D 0 "register_operand" "=vd,vd, vr, vr")
- (if_then_else:VI_D
+ [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
+ (if_then_else:V_VLSI_D
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
@@ -2563,12 +2563,12 @@
(match_operand 8 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
- (minus:VI_D
- (vec_duplicate:VI_D
+ (minus:V_VLSI_D
+ (vec_duplicate:V_VLSI_D
(sign_extend:<VEL>
(match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
- (match_operand:VI_D 3 "register_operand" "vr,vr, vr, vr"))
- (match_operand:VI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
+ (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
+ (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vrsub.vx\t%0,%3,%z4%p1"
[(set_attr "type" "vialu")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
new file mode 100644
index 00000000000..15ffdf68de7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VV (and, 1, int8_t, &)
+DEF_OP_VV (and, 2, int8_t, &)
+DEF_OP_VV (and, 4, int8_t, &)
+DEF_OP_VV (and, 8, int8_t, &)
+DEF_OP_VV (and, 16, int8_t, &)
+DEF_OP_VV (and, 32, int8_t, &)
+DEF_OP_VV (and, 64, int8_t, &)
+DEF_OP_VV (and, 128, int8_t, &)
+DEF_OP_VV (and, 256, int8_t, &)
+DEF_OP_VV (and, 512, int8_t, &)
+DEF_OP_VV (and, 1024, int8_t, &)
+DEF_OP_VV (and, 2048, int8_t, &)
+DEF_OP_VV (and, 4096, int8_t, &)
+
+DEF_OP_VV (and, 1, int16_t, &)
+DEF_OP_VV (and, 2, int16_t, &)
+DEF_OP_VV (and, 4, int16_t, &)
+DEF_OP_VV (and, 8, int16_t, &)
+DEF_OP_VV (and, 16, int16_t, &)
+DEF_OP_VV (and, 32, int16_t, &)
+DEF_OP_VV (and, 64, int16_t, &)
+DEF_OP_VV (and, 128, int16_t, &)
+DEF_OP_VV (and, 256, int16_t, &)
+DEF_OP_VV (and, 512, int16_t, &)
+DEF_OP_VV (and, 1024, int16_t, &)
+DEF_OP_VV (and, 2048, int16_t, &)
+
+DEF_OP_VV (and, 1, int32_t, &)
+DEF_OP_VV (and, 2, int32_t, &)
+DEF_OP_VV (and, 4, int32_t, &)
+DEF_OP_VV (and, 8, int32_t, &)
+DEF_OP_VV (and, 16, int32_t, &)
+DEF_OP_VV (and, 32, int32_t, &)
+DEF_OP_VV (and, 64, int32_t, &)
+DEF_OP_VV (and, 128, int32_t, &)
+DEF_OP_VV (and, 256, int32_t, &)
+DEF_OP_VV (and, 512, int32_t, &)
+DEF_OP_VV (and, 1024, int32_t, &)
+
+DEF_OP_VV (and, 1, int64_t, &)
+DEF_OP_VV (and, 2, int64_t, &)
+DEF_OP_VV (and, 4, int64_t, &)
+DEF_OP_VV (and, 8, int64_t, &)
+DEF_OP_VV (and, 16, int64_t, &)
+DEF_OP_VV (and, 32, int64_t, &)
+DEF_OP_VV (and, 64, int64_t, &)
+DEF_OP_VV (and, 128, int64_t, &)
+DEF_OP_VV (and, 256, int64_t, &)
+DEF_OP_VV (and, 512, int64_t, &)
+
+/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
new file mode 100644
index 00000000000..d0e68b1b47c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-2.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VI_M16 (and, 1, int8_t, &)
+DEF_OP_VI_M16 (and, 2, int8_t, &)
+DEF_OP_VI_M16 (and, 4, int8_t, &)
+DEF_OP_VI_M16 (and, 8, int8_t, &)
+DEF_OP_VI_M16 (and, 16, int8_t, &)
+DEF_OP_VI_M16 (and, 32, int8_t, &)
+DEF_OP_VI_M16 (and, 64, int8_t, &)
+DEF_OP_VI_M16 (and, 128, int8_t, &)
+DEF_OP_VI_M16 (and, 256, int8_t, &)
+DEF_OP_VI_M16 (and, 512, int8_t, &)
+DEF_OP_VI_M16 (and, 1024, int8_t, &)
+DEF_OP_VI_M16 (and, 2048, int8_t, &)
+DEF_OP_VI_M16 (and, 4096, int8_t, &)
+
+DEF_OP_VI_M16 (and, 1, int16_t, &)
+DEF_OP_VI_M16 (and, 2, int16_t, &)
+DEF_OP_VI_M16 (and, 4, int16_t, &)
+DEF_OP_VI_M16 (and, 8, int16_t, &)
+DEF_OP_VI_M16 (and, 16, int16_t, &)
+DEF_OP_VI_M16 (and, 32, int16_t, &)
+DEF_OP_VI_M16 (and, 64, int16_t, &)
+DEF_OP_VI_M16 (and, 128, int16_t, &)
+DEF_OP_VI_M16 (and, 256, int16_t, &)
+DEF_OP_VI_M16 (and, 512, int16_t, &)
+DEF_OP_VI_M16 (and, 1024, int16_t, &)
+DEF_OP_VI_M16 (and, 2048, int16_t, &)
+
+DEF_OP_VI_M16 (and, 1, int32_t, &)
+DEF_OP_VI_M16 (and, 2, int32_t, &)
+DEF_OP_VI_M16 (and, 4, int32_t, &)
+DEF_OP_VI_M16 (and, 8, int32_t, &)
+DEF_OP_VI_M16 (and, 16, int32_t, &)
+DEF_OP_VI_M16 (and, 32, int32_t, &)
+DEF_OP_VI_M16 (and, 64, int32_t, &)
+DEF_OP_VI_M16 (and, 128, int32_t, &)
+DEF_OP_VI_M16 (and, 256, int32_t, &)
+DEF_OP_VI_M16 (and, 512, int32_t, &)
+DEF_OP_VI_M16 (and, 1024, int32_t, &)
+
+DEF_OP_VI_M16 (and, 1, int64_t, &)
+DEF_OP_VI_M16 (and, 2, int64_t, &)
+DEF_OP_VI_M16 (and, 4, int64_t, &)
+DEF_OP_VI_M16 (and, 8, int64_t, &)
+DEF_OP_VI_M16 (and, 16, int64_t, &)
+DEF_OP_VI_M16 (and, 32, int64_t, &)
+DEF_OP_VI_M16 (and, 64, int64_t, &)
+DEF_OP_VI_M16 (and, 128, int64_t, &)
+DEF_OP_VI_M16 (and, 256, int64_t, &)
+DEF_OP_VI_M16 (and, 512, int64_t, &)
+
+/* { dg-final { scan-assembler-times {vand\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
new file mode 100644
index 00000000000..5b697dd8818
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/and-3.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VI_15 (and, 1, int8_t, &)
+DEF_OP_VI_15 (and, 2, int8_t, &)
+DEF_OP_VI_15 (and, 4, int8_t, &)
+DEF_OP_VI_15 (and, 8, int8_t, &)
+DEF_OP_VI_15 (and, 16, int8_t, &)
+DEF_OP_VI_15 (and, 32, int8_t, &)
+DEF_OP_VI_15 (and, 64, int8_t, &)
+DEF_OP_VI_15 (and, 128, int8_t, &)
+DEF_OP_VI_15 (and, 256, int8_t, &)
+DEF_OP_VI_15 (and, 512, int8_t, &)
+DEF_OP_VI_15 (and, 1024, int8_t, &)
+DEF_OP_VI_15 (and, 2048, int8_t, &)
+DEF_OP_VI_15 (and, 4096, int8_t, &)
+
+DEF_OP_VI_15 (and, 1, int16_t, &)
+DEF_OP_VI_15 (and, 2, int16_t, &)
+DEF_OP_VI_15 (and, 4, int16_t, &)
+DEF_OP_VI_15 (and, 8, int16_t, &)
+DEF_OP_VI_15 (and, 16, int16_t, &)
+DEF_OP_VI_15 (and, 32, int16_t, &)
+DEF_OP_VI_15 (and, 64, int16_t, &)
+DEF_OP_VI_15 (and, 128, int16_t, &)
+DEF_OP_VI_15 (and, 256, int16_t, &)
+DEF_OP_VI_15 (and, 512, int16_t, &)
+DEF_OP_VI_15 (and, 1024, int16_t, &)
+DEF_OP_VI_15 (and, 2048, int16_t, &)
+
+DEF_OP_VI_15 (and, 1, int32_t, &)
+DEF_OP_VI_15 (and, 2, int32_t, &)
+DEF_OP_VI_15 (and, 4, int32_t, &)
+DEF_OP_VI_15 (and, 8, int32_t, &)
+DEF_OP_VI_15 (and, 16, int32_t, &)
+DEF_OP_VI_15 (and, 32, int32_t, &)
+DEF_OP_VI_15 (and, 64, int32_t, &)
+DEF_OP_VI_15 (and, 128, int32_t, &)
+DEF_OP_VI_15 (and, 256, int32_t, &)
+DEF_OP_VI_15 (and, 512, int32_t, &)
+DEF_OP_VI_15 (and, 1024, int32_t, &)
+
+DEF_OP_VI_15 (and, 1, int64_t, &)
+DEF_OP_VI_15 (and, 2, int64_t, &)
+DEF_OP_VI_15 (and, 4, int64_t, &)
+DEF_OP_VI_15 (and, 8, int64_t, &)
+DEF_OP_VI_15 (and, 16, int64_t, &)
+DEF_OP_VI_15 (and, 32, int64_t, &)
+DEF_OP_VI_15 (and, 64, int64_t, &)
+DEF_OP_VI_15 (and, 128, int64_t, &)
+DEF_OP_VI_15 (and, 256, int64_t, &)
+DEF_OP_VI_15 (and, 512, int64_t, &)
+
+/* { dg-final { scan-assembler-times {vand\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
index d03108ad771..2ef84be3b63 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h
@@ -86,3 +86,51 @@ typedef double v512df __attribute__ ((vector_size (4096)));
"v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", \
"v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25", \
"v26", "v27", "v28", "v29", "v30", "v31");
+
+#define DEF_OP_VV(PREFIX, NUM, TYPE, OP) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = b[i] OP c[i]; \
+ }
+
+#define DEF_OP_VI_M16(PREFIX, NUM, TYPE, OP) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = b[i] OP -16; \
+ }
+
+#define DEF_OP_VI_15(PREFIX, NUM, TYPE, OP) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = b[i] OP 15; \
+ }
+
+#define DEF_OP_IV_M16(PREFIX, NUM, TYPE, OP) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = -16 OP b[i]; \
+ }
+
+#define DEF_OP_IV_15(PREFIX, NUM, TYPE, OP) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = 15 OP b[i]; \
+ }
+
+#define DEF_MINMAX_VV(PREFIX, NUM, TYPE, OP) \
+ void __attribute__ ((noinline, noclone)) \
+ PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE *restrict c) \
+ { \
+ for (int i = 0; i < NUM; ++i) \
+ a[i] = b[i] OP c[i] ? b[i] : c[i]; \
+ }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
new file mode 100644
index 00000000000..f3388a86e38
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c
@@ -0,0 +1,58 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VV (div, 1, int8_t, /)
+DEF_OP_VV (div, 2, int8_t, /)
+DEF_OP_VV (div, 4, int8_t, /)
+DEF_OP_VV (div, 8, int8_t, /)
+DEF_OP_VV (div, 16, int8_t, /)
+DEF_OP_VV (div, 32, int8_t, /)
+DEF_OP_VV (div, 64, int8_t, /)
+DEF_OP_VV (div, 128, int8_t, /)
+DEF_OP_VV (div, 256, int8_t, /)
+DEF_OP_VV (div, 512, int8_t, /)
+DEF_OP_VV (div, 1024, int8_t, /)
+DEF_OP_VV (div, 2048, int8_t, /)
+DEF_OP_VV (div, 4096, int8_t, /)
+
+DEF_OP_VV (div, 1, int16_t, /)
+DEF_OP_VV (div, 2, int16_t, /)
+DEF_OP_VV (div, 4, int16_t, /)
+DEF_OP_VV (div, 8, int16_t, /)
+DEF_OP_VV (div, 16, int16_t, /)
+DEF_OP_VV (div, 32, int16_t, /)
+DEF_OP_VV (div, 64, int16_t, /)
+DEF_OP_VV (div, 128, int16_t, /)
+DEF_OP_VV (div, 256, int16_t, /)
+DEF_OP_VV (div, 512, int16_t, /)
+DEF_OP_VV (div, 1024, int16_t, /)
+DEF_OP_VV (div, 2048, int16_t, /)
+
+DEF_OP_VV (div, 1, int32_t, /)
+DEF_OP_VV (div, 2, int32_t, /)
+DEF_OP_VV (div, 4, int32_t, /)
+DEF_OP_VV (div, 8, int32_t, /)
+DEF_OP_VV (div, 16, int32_t, /)
+DEF_OP_VV (div, 32, int32_t, /)
+DEF_OP_VV (div, 64, int32_t, /)
+DEF_OP_VV (div, 128, int32_t, /)
+DEF_OP_VV (div, 256, int32_t, /)
+DEF_OP_VV (div, 512, int32_t, /)
+DEF_OP_VV (div, 1024, int32_t, /)
+
+DEF_OP_VV (div, 1, int64_t, /)
+DEF_OP_VV (div, 2, int64_t, /)
+DEF_OP_VV (div, 4, int64_t, /)
+DEF_OP_VV (div, 8, int64_t, /)
+DEF_OP_VV (div, 16, int64_t, /)
+DEF_OP_VV (div, 32, int64_t, /)
+DEF_OP_VV (div, 64, int64_t, /)
+DEF_OP_VV (div, 128, int64_t, /)
+DEF_OP_VV (div, 256, int64_t, /)
+DEF_OP_VV (div, 512, int64_t, /)
+
+/* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */
+/* { dg-final { scan-assembler-times {csrr} 19 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
new file mode 100644
index 00000000000..dcee81a9bc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VV (ior, 1, int8_t, |)
+DEF_OP_VV (ior, 2, int8_t, |)
+DEF_OP_VV (ior, 4, int8_t, |)
+DEF_OP_VV (ior, 8, int8_t, |)
+DEF_OP_VV (ior, 16, int8_t, |)
+DEF_OP_VV (ior, 32, int8_t, |)
+DEF_OP_VV (ior, 64, int8_t, |)
+DEF_OP_VV (ior, 128, int8_t, |)
+DEF_OP_VV (ior, 256, int8_t, |)
+DEF_OP_VV (ior, 512, int8_t, |)
+DEF_OP_VV (ior, 1024, int8_t, |)
+DEF_OP_VV (ior, 2048, int8_t, |)
+DEF_OP_VV (ior, 4096, int8_t, |)
+
+DEF_OP_VV (ior, 1, int16_t, |)
+DEF_OP_VV (ior, 2, int16_t, |)
+DEF_OP_VV (ior, 4, int16_t, |)
+DEF_OP_VV (ior, 8, int16_t, |)
+DEF_OP_VV (ior, 16, int16_t, |)
+DEF_OP_VV (ior, 32, int16_t, |)
+DEF_OP_VV (ior, 64, int16_t, |)
+DEF_OP_VV (ior, 128, int16_t, |)
+DEF_OP_VV (ior, 256, int16_t, |)
+DEF_OP_VV (ior, 512, int16_t, |)
+DEF_OP_VV (ior, 1024, int16_t, |)
+DEF_OP_VV (ior, 2048, int16_t, |)
+
+DEF_OP_VV (ior, 1, int32_t, |)
+DEF_OP_VV (ior, 2, int32_t, |)
+DEF_OP_VV (ior, 4, int32_t, |)
+DEF_OP_VV (ior, 8, int32_t, |)
+DEF_OP_VV (ior, 16, int32_t, |)
+DEF_OP_VV (ior, 32, int32_t, |)
+DEF_OP_VV (ior, 64, int32_t, |)
+DEF_OP_VV (ior, 128, int32_t, |)
+DEF_OP_VV (ior, 256, int32_t, |)
+DEF_OP_VV (ior, 512, int32_t, |)
+DEF_OP_VV (ior, 1024, int32_t, |)
+
+DEF_OP_VV (ior, 1, int64_t, |)
+DEF_OP_VV (ior, 2, int64_t, |)
+DEF_OP_VV (ior, 4, int64_t, |)
+DEF_OP_VV (ior, 8, int64_t, |)
+DEF_OP_VV (ior, 16, int64_t, |)
+DEF_OP_VV (ior, 32, int64_t, |)
+DEF_OP_VV (ior, 64, int64_t, |)
+DEF_OP_VV (ior, 128, int64_t, |)
+DEF_OP_VV (ior, 256, int64_t, |)
+DEF_OP_VV (ior, 512, int64_t, |)
+
+/* { dg-final { scan-assembler-times {vor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
new file mode 100644
index 00000000000..adcba29197a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-2.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VI_M16 (ior, 1, int8_t, |)
+DEF_OP_VI_M16 (ior, 2, int8_t, |)
+DEF_OP_VI_M16 (ior, 4, int8_t, |)
+DEF_OP_VI_M16 (ior, 8, int8_t, |)
+DEF_OP_VI_M16 (ior, 16, int8_t, |)
+DEF_OP_VI_M16 (ior, 32, int8_t, |)
+DEF_OP_VI_M16 (ior, 64, int8_t, |)
+DEF_OP_VI_M16 (ior, 128, int8_t, |)
+DEF_OP_VI_M16 (ior, 256, int8_t, |)
+DEF_OP_VI_M16 (ior, 512, int8_t, |)
+DEF_OP_VI_M16 (ior, 1024, int8_t, |)
+DEF_OP_VI_M16 (ior, 2048, int8_t, |)
+DEF_OP_VI_M16 (ior, 4096, int8_t, |)
+
+DEF_OP_VI_M16 (ior, 1, int16_t, |)
+DEF_OP_VI_M16 (ior, 2, int16_t, |)
+DEF_OP_VI_M16 (ior, 4, int16_t, |)
+DEF_OP_VI_M16 (ior, 8, int16_t, |)
+DEF_OP_VI_M16 (ior, 16, int16_t, |)
+DEF_OP_VI_M16 (ior, 32, int16_t, |)
+DEF_OP_VI_M16 (ior, 64, int16_t, |)
+DEF_OP_VI_M16 (ior, 128, int16_t, |)
+DEF_OP_VI_M16 (ior, 256, int16_t, |)
+DEF_OP_VI_M16 (ior, 512, int16_t, |)
+DEF_OP_VI_M16 (ior, 1024, int16_t, |)
+DEF_OP_VI_M16 (ior, 2048, int16_t, |)
+
+DEF_OP_VI_M16 (ior, 1, int32_t, |)
+DEF_OP_VI_M16 (ior, 2, int32_t, |)
+DEF_OP_VI_M16 (ior, 4, int32_t, |)
+DEF_OP_VI_M16 (ior, 8, int32_t, |)
+DEF_OP_VI_M16 (ior, 16, int32_t, |)
+DEF_OP_VI_M16 (ior, 32, int32_t, |)
+DEF_OP_VI_M16 (ior, 64, int32_t, |)
+DEF_OP_VI_M16 (ior, 128, int32_t, |)
+DEF_OP_VI_M16 (ior, 256, int32_t, |)
+DEF_OP_VI_M16 (ior, 512, int32_t, |)
+DEF_OP_VI_M16 (ior, 1024, int32_t, |)
+
+DEF_OP_VI_M16 (ior, 1, int64_t, |)
+DEF_OP_VI_M16 (ior, 2, int64_t, |)
+DEF_OP_VI_M16 (ior, 4, int64_t, |)
+DEF_OP_VI_M16 (ior, 8, int64_t, |)
+DEF_OP_VI_M16 (ior, 16, int64_t, |)
+DEF_OP_VI_M16 (ior, 32, int64_t, |)
+DEF_OP_VI_M16 (ior, 64, int64_t, |)
+DEF_OP_VI_M16 (ior, 128, int64_t, |)
+DEF_OP_VI_M16 (ior, 256, int64_t, |)
+DEF_OP_VI_M16 (ior, 512, int64_t, |)
+
+/* { dg-final { scan-assembler-times {vor\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
new file mode 100644
index 00000000000..ed142d58489
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/ior-3.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VI_15 (ior, 1, int8_t, |)
+DEF_OP_VI_15 (ior, 2, int8_t, |)
+DEF_OP_VI_15 (ior, 4, int8_t, |)
+DEF_OP_VI_15 (ior, 8, int8_t, |)
+DEF_OP_VI_15 (ior, 16, int8_t, |)
+DEF_OP_VI_15 (ior, 32, int8_t, |)
+DEF_OP_VI_15 (ior, 64, int8_t, |)
+DEF_OP_VI_15 (ior, 128, int8_t, |)
+DEF_OP_VI_15 (ior, 256, int8_t, |)
+DEF_OP_VI_15 (ior, 512, int8_t, |)
+DEF_OP_VI_15 (ior, 1024, int8_t, |)
+DEF_OP_VI_15 (ior, 2048, int8_t, |)
+DEF_OP_VI_15 (ior, 4096, int8_t, |)
+
+DEF_OP_VI_15 (ior, 1, int16_t, |)
+DEF_OP_VI_15 (ior, 2, int16_t, |)
+DEF_OP_VI_15 (ior, 4, int16_t, |)
+DEF_OP_VI_15 (ior, 8, int16_t, |)
+DEF_OP_VI_15 (ior, 16, int16_t, |)
+DEF_OP_VI_15 (ior, 32, int16_t, |)
+DEF_OP_VI_15 (ior, 64, int16_t, |)
+DEF_OP_VI_15 (ior, 128, int16_t, |)
+DEF_OP_VI_15 (ior, 256, int16_t, |)
+DEF_OP_VI_15 (ior, 512, int16_t, |)
+DEF_OP_VI_15 (ior, 1024, int16_t, |)
+DEF_OP_VI_15 (ior, 2048, int16_t, |)
+
+DEF_OP_VI_15 (ior, 1, int32_t, |)
+DEF_OP_VI_15 (ior, 2, int32_t, |)
+DEF_OP_VI_15 (ior, 4, int32_t, |)
+DEF_OP_VI_15 (ior, 8, int32_t, |)
+DEF_OP_VI_15 (ior, 16, int32_t, |)
+DEF_OP_VI_15 (ior, 32, int32_t, |)
+DEF_OP_VI_15 (ior, 64, int32_t, |)
+DEF_OP_VI_15 (ior, 128, int32_t, |)
+DEF_OP_VI_15 (ior, 256, int32_t, |)
+DEF_OP_VI_15 (ior, 512, int32_t, |)
+DEF_OP_VI_15 (ior, 1024, int32_t, |)
+
+DEF_OP_VI_15 (ior, 1, int64_t, |)
+DEF_OP_VI_15 (ior, 2, int64_t, |)
+DEF_OP_VI_15 (ior, 4, int64_t, |)
+DEF_OP_VI_15 (ior, 8, int64_t, |)
+DEF_OP_VI_15 (ior, 16, int64_t, |)
+DEF_OP_VI_15 (ior, 32, int64_t, |)
+DEF_OP_VI_15 (ior, 64, int64_t, |)
+DEF_OP_VI_15 (ior, 128, int64_t, |)
+DEF_OP_VI_15 (ior, 256, int64_t, |)
+DEF_OP_VI_15 (ior, 512, int64_t, |)
+
+/* { dg-final { scan-assembler-times {vor\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
new file mode 100644
index 00000000000..e4400c20733
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/max-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_MINMAX_VV (max, 1, int8_t, >)
+DEF_MINMAX_VV (max, 2, int8_t, >)
+DEF_MINMAX_VV (max, 4, int8_t, >)
+DEF_MINMAX_VV (max, 8, int8_t, >)
+DEF_MINMAX_VV (max, 16, int8_t, >)
+DEF_MINMAX_VV (max, 32, int8_t, >)
+DEF_MINMAX_VV (max, 64, int8_t, >)
+DEF_MINMAX_VV (max, 128, int8_t, >)
+DEF_MINMAX_VV (max, 256, int8_t, >)
+DEF_MINMAX_VV (max, 512, int8_t, >)
+DEF_MINMAX_VV (max, 1024, int8_t, >)
+DEF_MINMAX_VV (max, 2048, int8_t, >)
+DEF_MINMAX_VV (max, 4096, int8_t, >)
+
+DEF_MINMAX_VV (max, 1, int16_t, >)
+DEF_MINMAX_VV (max, 2, int16_t, >)
+DEF_MINMAX_VV (max, 4, int16_t, >)
+DEF_MINMAX_VV (max, 8, int16_t, >)
+DEF_MINMAX_VV (max, 16, int16_t, >)
+DEF_MINMAX_VV (max, 32, int16_t, >)
+DEF_MINMAX_VV (max, 64, int16_t, >)
+DEF_MINMAX_VV (max, 128, int16_t, >)
+DEF_MINMAX_VV (max, 256, int16_t, >)
+DEF_MINMAX_VV (max, 512, int16_t, >)
+DEF_MINMAX_VV (max, 1024, int16_t, >)
+DEF_MINMAX_VV (max, 2048, int16_t, >)
+
+DEF_MINMAX_VV (max, 1, int32_t, >)
+DEF_MINMAX_VV (max, 2, int32_t, >)
+DEF_MINMAX_VV (max, 4, int32_t, >)
+DEF_MINMAX_VV (max, 8, int32_t, >)
+DEF_MINMAX_VV (max, 16, int32_t, >)
+DEF_MINMAX_VV (max, 32, int32_t, >)
+DEF_MINMAX_VV (max, 64, int32_t, >)
+DEF_MINMAX_VV (max, 128, int32_t, >)
+DEF_MINMAX_VV (max, 256, int32_t, >)
+DEF_MINMAX_VV (max, 512, int32_t, >)
+DEF_MINMAX_VV (max, 1024, int32_t, >)
+
+DEF_MINMAX_VV (max, 1, int64_t, >)
+DEF_MINMAX_VV (max, 2, int64_t, >)
+DEF_MINMAX_VV (max, 4, int64_t, >)
+DEF_MINMAX_VV (max, 8, int64_t, >)
+DEF_MINMAX_VV (max, 16, int64_t, >)
+DEF_MINMAX_VV (max, 32, int64_t, >)
+DEF_MINMAX_VV (max, 64, int64_t, >)
+DEF_MINMAX_VV (max, 128, int64_t, >)
+DEF_MINMAX_VV (max, 256, int64_t, >)
+DEF_MINMAX_VV (max, 512, int64_t, >)
+
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
new file mode 100644
index 00000000000..41e2d26e158
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/min-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_MINMAX_VV (min, 1, int8_t, <)
+DEF_MINMAX_VV (min, 2, int8_t, <)
+DEF_MINMAX_VV (min, 4, int8_t, <)
+DEF_MINMAX_VV (min, 8, int8_t, <)
+DEF_MINMAX_VV (min, 16, int8_t, <)
+DEF_MINMAX_VV (min, 32, int8_t, <)
+DEF_MINMAX_VV (min, 64, int8_t, <)
+DEF_MINMAX_VV (min, 128, int8_t, <)
+DEF_MINMAX_VV (min, 256, int8_t, <)
+DEF_MINMAX_VV (min, 512, int8_t, <)
+DEF_MINMAX_VV (min, 1024, int8_t, <)
+DEF_MINMAX_VV (min, 2048, int8_t, <)
+DEF_MINMAX_VV (min, 4096, int8_t, <)
+
+DEF_MINMAX_VV (min, 1, int16_t, <)
+DEF_MINMAX_VV (min, 2, int16_t, <)
+DEF_MINMAX_VV (min, 4, int16_t, <)
+DEF_MINMAX_VV (min, 8, int16_t, <)
+DEF_MINMAX_VV (min, 16, int16_t, <)
+DEF_MINMAX_VV (min, 32, int16_t, <)
+DEF_MINMAX_VV (min, 64, int16_t, <)
+DEF_MINMAX_VV (min, 128, int16_t, <)
+DEF_MINMAX_VV (min, 256, int16_t, <)
+DEF_MINMAX_VV (min, 512, int16_t, <)
+DEF_MINMAX_VV (min, 1024, int16_t, <)
+DEF_MINMAX_VV (min, 2048, int16_t, <)
+
+DEF_MINMAX_VV (min, 1, int32_t, <)
+DEF_MINMAX_VV (min, 2, int32_t, <)
+DEF_MINMAX_VV (min, 4, int32_t, <)
+DEF_MINMAX_VV (min, 8, int32_t, <)
+DEF_MINMAX_VV (min, 16, int32_t, <)
+DEF_MINMAX_VV (min, 32, int32_t, <)
+DEF_MINMAX_VV (min, 64, int32_t, <)
+DEF_MINMAX_VV (min, 128, int32_t, <)
+DEF_MINMAX_VV (min, 256, int32_t, <)
+DEF_MINMAX_VV (min, 512, int32_t, <)
+DEF_MINMAX_VV (min, 1024, int32_t, <)
+
+DEF_MINMAX_VV (min, 1, int64_t, <)
+DEF_MINMAX_VV (min, 2, int64_t, <)
+DEF_MINMAX_VV (min, 4, int64_t, <)
+DEF_MINMAX_VV (min, 8, int64_t, <)
+DEF_MINMAX_VV (min, 16, int64_t, <)
+DEF_MINMAX_VV (min, 32, int64_t, <)
+DEF_MINMAX_VV (min, 64, int64_t, <)
+DEF_MINMAX_VV (min, 128, int64_t, <)
+DEF_MINMAX_VV (min, 256, int64_t, <)
+DEF_MINMAX_VV (min, 512, int64_t, <)
+
+/* { dg-final { scan-assembler-times {vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
new file mode 100644
index 00000000000..4d698ba3c89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VV (minus, 1, int8_t, -)
+DEF_OP_VV (minus, 2, int8_t, -)
+DEF_OP_VV (minus, 4, int8_t, -)
+DEF_OP_VV (minus, 8, int8_t, -)
+DEF_OP_VV (minus, 16, int8_t, -)
+DEF_OP_VV (minus, 32, int8_t, -)
+DEF_OP_VV (minus, 64, int8_t, -)
+DEF_OP_VV (minus, 128, int8_t, -)
+DEF_OP_VV (minus, 256, int8_t, -)
+DEF_OP_VV (minus, 512, int8_t, -)
+DEF_OP_VV (minus, 1024, int8_t, -)
+DEF_OP_VV (minus, 2048, int8_t, -)
+DEF_OP_VV (minus, 4096, int8_t, -)
+
+DEF_OP_VV (minus, 1, int16_t, -)
+DEF_OP_VV (minus, 2, int16_t, -)
+DEF_OP_VV (minus, 4, int16_t, -)
+DEF_OP_VV (minus, 8, int16_t, -)
+DEF_OP_VV (minus, 16, int16_t, -)
+DEF_OP_VV (minus, 32, int16_t, -)
+DEF_OP_VV (minus, 64, int16_t, -)
+DEF_OP_VV (minus, 128, int16_t, -)
+DEF_OP_VV (minus, 256, int16_t, -)
+DEF_OP_VV (minus, 512, int16_t, -)
+DEF_OP_VV (minus, 1024, int16_t, -)
+DEF_OP_VV (minus, 2048, int16_t, -)
+
+DEF_OP_VV (minus, 1, int32_t, -)
+DEF_OP_VV (minus, 2, int32_t, -)
+DEF_OP_VV (minus, 4, int32_t, -)
+DEF_OP_VV (minus, 8, int32_t, -)
+DEF_OP_VV (minus, 16, int32_t, -)
+DEF_OP_VV (minus, 32, int32_t, -)
+DEF_OP_VV (minus, 64, int32_t, -)
+DEF_OP_VV (minus, 128, int32_t, -)
+DEF_OP_VV (minus, 256, int32_t, -)
+DEF_OP_VV (minus, 512, int32_t, -)
+DEF_OP_VV (minus, 1024, int32_t, -)
+
+DEF_OP_VV (minus, 1, int64_t, -)
+DEF_OP_VV (minus, 2, int64_t, -)
+DEF_OP_VV (minus, 4, int64_t, -)
+DEF_OP_VV (minus, 8, int64_t, -)
+DEF_OP_VV (minus, 16, int64_t, -)
+DEF_OP_VV (minus, 32, int64_t, -)
+DEF_OP_VV (minus, 64, int64_t, -)
+DEF_OP_VV (minus, 128, int64_t, -)
+DEF_OP_VV (minus, 256, int64_t, -)
+DEF_OP_VV (minus, 512, int64_t, -)
+
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
new file mode 100644
index 00000000000..2d9dd6290f5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-2.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_IV_M16 (minus, 1, int8_t, -)
+DEF_OP_IV_M16 (minus, 2, int8_t, -)
+DEF_OP_IV_M16 (minus, 4, int8_t, -)
+DEF_OP_IV_M16 (minus, 8, int8_t, -)
+DEF_OP_IV_M16 (minus, 16, int8_t, -)
+DEF_OP_IV_M16 (minus, 32, int8_t, -)
+DEF_OP_IV_M16 (minus, 64, int8_t, -)
+DEF_OP_IV_M16 (minus, 128, int8_t, -)
+DEF_OP_IV_M16 (minus, 256, int8_t, -)
+DEF_OP_IV_M16 (minus, 512, int8_t, -)
+DEF_OP_IV_M16 (minus, 1024, int8_t, -)
+DEF_OP_IV_M16 (minus, 2048, int8_t, -)
+DEF_OP_IV_M16 (minus, 4096, int8_t, -)
+
+DEF_OP_IV_M16 (minus, 1, int16_t, -)
+DEF_OP_IV_M16 (minus, 2, int16_t, -)
+DEF_OP_IV_M16 (minus, 4, int16_t, -)
+DEF_OP_IV_M16 (minus, 8, int16_t, -)
+DEF_OP_IV_M16 (minus, 16, int16_t, -)
+DEF_OP_IV_M16 (minus, 32, int16_t, -)
+DEF_OP_IV_M16 (minus, 64, int16_t, -)
+DEF_OP_IV_M16 (minus, 128, int16_t, -)
+DEF_OP_IV_M16 (minus, 256, int16_t, -)
+DEF_OP_IV_M16 (minus, 512, int16_t, -)
+DEF_OP_IV_M16 (minus, 1024, int16_t, -)
+DEF_OP_IV_M16 (minus, 2048, int16_t, -)
+
+DEF_OP_IV_M16 (minus, 1, int32_t, -)
+DEF_OP_IV_M16 (minus, 2, int32_t, -)
+DEF_OP_IV_M16 (minus, 4, int32_t, -)
+DEF_OP_IV_M16 (minus, 8, int32_t, -)
+DEF_OP_IV_M16 (minus, 16, int32_t, -)
+DEF_OP_IV_M16 (minus, 32, int32_t, -)
+DEF_OP_IV_M16 (minus, 64, int32_t, -)
+DEF_OP_IV_M16 (minus, 128, int32_t, -)
+DEF_OP_IV_M16 (minus, 256, int32_t, -)
+DEF_OP_IV_M16 (minus, 512, int32_t, -)
+DEF_OP_IV_M16 (minus, 1024, int32_t, -)
+
+DEF_OP_IV_M16 (minus, 1, int64_t, -)
+DEF_OP_IV_M16 (minus, 2, int64_t, -)
+DEF_OP_IV_M16 (minus, 4, int64_t, -)
+DEF_OP_IV_M16 (minus, 8, int64_t, -)
+DEF_OP_IV_M16 (minus, 16, int64_t, -)
+DEF_OP_IV_M16 (minus, 32, int64_t, -)
+DEF_OP_IV_M16 (minus, 64, int64_t, -)
+DEF_OP_IV_M16 (minus, 128, int64_t, -)
+DEF_OP_IV_M16 (minus, 256, int64_t, -)
+DEF_OP_IV_M16 (minus, 512, int64_t, -)
+
+/* { dg-final { scan-assembler-times {vrsub\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
new file mode 100644
index 00000000000..2625c164e41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/minus-3.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_IV_15 (minus, 1, int8_t, -)
+DEF_OP_IV_15 (minus, 2, int8_t, -)
+DEF_OP_IV_15 (minus, 4, int8_t, -)
+DEF_OP_IV_15 (minus, 8, int8_t, -)
+DEF_OP_IV_15 (minus, 16, int8_t, -)
+DEF_OP_IV_15 (minus, 32, int8_t, -)
+DEF_OP_IV_15 (minus, 64, int8_t, -)
+DEF_OP_IV_15 (minus, 128, int8_t, -)
+DEF_OP_IV_15 (minus, 256, int8_t, -)
+DEF_OP_IV_15 (minus, 512, int8_t, -)
+DEF_OP_IV_15 (minus, 1024, int8_t, -)
+DEF_OP_IV_15 (minus, 2048, int8_t, -)
+DEF_OP_IV_15 (minus, 4096, int8_t, -)
+
+DEF_OP_IV_15 (minus, 1, int16_t, -)
+DEF_OP_IV_15 (minus, 2, int16_t, -)
+DEF_OP_IV_15 (minus, 4, int16_t, -)
+DEF_OP_IV_15 (minus, 8, int16_t, -)
+DEF_OP_IV_15 (minus, 16, int16_t, -)
+DEF_OP_IV_15 (minus, 32, int16_t, -)
+DEF_OP_IV_15 (minus, 64, int16_t, -)
+DEF_OP_IV_15 (minus, 128, int16_t, -)
+DEF_OP_IV_15 (minus, 256, int16_t, -)
+DEF_OP_IV_15 (minus, 512, int16_t, -)
+DEF_OP_IV_15 (minus, 1024, int16_t, -)
+DEF_OP_IV_15 (minus, 2048, int16_t, -)
+
+DEF_OP_IV_15 (minus, 1, int32_t, -)
+DEF_OP_IV_15 (minus, 2, int32_t, -)
+DEF_OP_IV_15 (minus, 4, int32_t, -)
+DEF_OP_IV_15 (minus, 8, int32_t, -)
+DEF_OP_IV_15 (minus, 16, int32_t, -)
+DEF_OP_IV_15 (minus, 32, int32_t, -)
+DEF_OP_IV_15 (minus, 64, int32_t, -)
+DEF_OP_IV_15 (minus, 128, int32_t, -)
+DEF_OP_IV_15 (minus, 256, int32_t, -)
+DEF_OP_IV_15 (minus, 512, int32_t, -)
+DEF_OP_IV_15 (minus, 1024, int32_t, -)
+
+DEF_OP_IV_15 (minus, 1, int64_t, -)
+DEF_OP_IV_15 (minus, 2, int64_t, -)
+DEF_OP_IV_15 (minus, 4, int64_t, -)
+DEF_OP_IV_15 (minus, 8, int64_t, -)
+DEF_OP_IV_15 (minus, 16, int64_t, -)
+DEF_OP_IV_15 (minus, 32, int64_t, -)
+DEF_OP_IV_15 (minus, 64, int64_t, -)
+DEF_OP_IV_15 (minus, 128, int64_t, -)
+DEF_OP_IV_15 (minus, 256, int64_t, -)
+DEF_OP_IV_15 (minus, 512, int64_t, -)
+
+/* { dg-final { scan-assembler-times {vrsub\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
new file mode 100644
index 00000000000..c8caf353553
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VV (mod, 1, int8_t, %)
+DEF_OP_VV (mod, 2, int8_t, %)
+DEF_OP_VV (mod, 4, int8_t, %)
+DEF_OP_VV (mod, 8, int8_t, %)
+DEF_OP_VV (mod, 16, int8_t, %)
+DEF_OP_VV (mod, 32, int8_t, %)
+DEF_OP_VV (mod, 64, int8_t, %)
+DEF_OP_VV (mod, 128, int8_t, %)
+DEF_OP_VV (mod, 256, int8_t, %)
+DEF_OP_VV (mod, 512, int8_t, %)
+DEF_OP_VV (mod, 1024, int8_t, %)
+DEF_OP_VV (mod, 2048, int8_t, %)
+DEF_OP_VV (mod, 4096, int8_t, %)
+
+DEF_OP_VV (mod, 1, int16_t, %)
+DEF_OP_VV (mod, 2, int16_t, %)
+DEF_OP_VV (mod, 4, int16_t, %)
+DEF_OP_VV (mod, 8, int16_t, %)
+DEF_OP_VV (mod, 16, int16_t, %)
+DEF_OP_VV (mod, 32, int16_t, %)
+DEF_OP_VV (mod, 64, int16_t, %)
+DEF_OP_VV (mod, 128, int16_t, %)
+DEF_OP_VV (mod, 256, int16_t, %)
+DEF_OP_VV (mod, 512, int16_t, %)
+DEF_OP_VV (mod, 1024, int16_t, %)
+DEF_OP_VV (mod, 2048, int16_t, %)
+
+DEF_OP_VV (mod, 1, int32_t, %)
+DEF_OP_VV (mod, 2, int32_t, %)
+DEF_OP_VV (mod, 4, int32_t, %)
+DEF_OP_VV (mod, 8, int32_t, %)
+DEF_OP_VV (mod, 16, int32_t, %)
+DEF_OP_VV (mod, 32, int32_t, %)
+DEF_OP_VV (mod, 64, int32_t, %)
+DEF_OP_VV (mod, 128, int32_t, %)
+DEF_OP_VV (mod, 256, int32_t, %)
+DEF_OP_VV (mod, 512, int32_t, %)
+DEF_OP_VV (mod, 1024, int32_t, %)
+
+DEF_OP_VV (mod, 1, int64_t, %)
+DEF_OP_VV (mod, 2, int64_t, %)
+DEF_OP_VV (mod, 4, int64_t, %)
+DEF_OP_VV (mod, 8, int64_t, %)
+DEF_OP_VV (mod, 16, int64_t, %)
+DEF_OP_VV (mod, 32, int64_t, %)
+DEF_OP_VV (mod, 64, int64_t, %)
+DEF_OP_VV (mod, 128, int64_t, %)
+DEF_OP_VV (mod, 256, int64_t, %)
+DEF_OP_VV (mod, 512, int64_t, %)
+
+/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
new file mode 100644
index 00000000000..0d1b5a45e9c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mult-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VV (mult, 1, int8_t, *)
+DEF_OP_VV (mult, 2, int8_t, *)
+DEF_OP_VV (mult, 4, int8_t, *)
+DEF_OP_VV (mult, 8, int8_t, *)
+DEF_OP_VV (mult, 16, int8_t, *)
+DEF_OP_VV (mult, 32, int8_t, *)
+DEF_OP_VV (mult, 64, int8_t, *)
+DEF_OP_VV (mult, 128, int8_t, *)
+DEF_OP_VV (mult, 256, int8_t, *)
+DEF_OP_VV (mult, 512, int8_t, *)
+DEF_OP_VV (mult, 1024, int8_t, *)
+DEF_OP_VV (mult, 2048, int8_t, *)
+DEF_OP_VV (mult, 4096, int8_t, *)
+
+DEF_OP_VV (mult, 1, int16_t, *)
+DEF_OP_VV (mult, 2, int16_t, *)
+DEF_OP_VV (mult, 4, int16_t, *)
+DEF_OP_VV (mult, 8, int16_t, *)
+DEF_OP_VV (mult, 16, int16_t, *)
+DEF_OP_VV (mult, 32, int16_t, *)
+DEF_OP_VV (mult, 64, int16_t, *)
+DEF_OP_VV (mult, 128, int16_t, *)
+DEF_OP_VV (mult, 256, int16_t, *)
+DEF_OP_VV (mult, 512, int16_t, *)
+DEF_OP_VV (mult, 1024, int16_t, *)
+DEF_OP_VV (mult, 2048, int16_t, *)
+
+DEF_OP_VV (mult, 1, int32_t, *)
+DEF_OP_VV (mult, 2, int32_t, *)
+DEF_OP_VV (mult, 4, int32_t, *)
+DEF_OP_VV (mult, 8, int32_t, *)
+DEF_OP_VV (mult, 16, int32_t, *)
+DEF_OP_VV (mult, 32, int32_t, *)
+DEF_OP_VV (mult, 64, int32_t, *)
+DEF_OP_VV (mult, 128, int32_t, *)
+DEF_OP_VV (mult, 256, int32_t, *)
+DEF_OP_VV (mult, 512, int32_t, *)
+DEF_OP_VV (mult, 1024, int32_t, *)
+
+DEF_OP_VV (mult, 1, int64_t, *)
+DEF_OP_VV (mult, 2, int64_t, *)
+DEF_OP_VV (mult, 4, int64_t, *)
+DEF_OP_VV (mult, 8, int64_t, *)
+DEF_OP_VV (mult, 16, int64_t, *)
+DEF_OP_VV (mult, 32, int64_t, *)
+DEF_OP_VV (mult, 64, int64_t, *)
+DEF_OP_VV (mult, 128, int64_t, *)
+DEF_OP_VV (mult, 256, int64_t, *)
+DEF_OP_VV (mult, 512, int64_t, *)
+
+/* { dg-final { scan-assembler-times {vmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
new file mode 100644
index 00000000000..146b4dd2cac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-1.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VV (plus, 1, int8_t, +)
+DEF_OP_VV (plus, 2, int8_t, +)
+DEF_OP_VV (plus, 4, int8_t, +)
+DEF_OP_VV (plus, 8, int8_t, +)
+DEF_OP_VV (plus, 16, int8_t, +)
+DEF_OP_VV (plus, 32, int8_t, +)
+DEF_OP_VV (plus, 64, int8_t, +)
+DEF_OP_VV (plus, 128, int8_t, +)
+DEF_OP_VV (plus, 256, int8_t, +)
+DEF_OP_VV (plus, 512, int8_t, +)
+DEF_OP_VV (plus, 1024, int8_t, +)
+DEF_OP_VV (plus, 2048, int8_t, +)
+DEF_OP_VV (plus, 4096, int8_t, +)
+
+DEF_OP_VV (plus, 1, int16_t, +)
+DEF_OP_VV (plus, 2, int16_t, +)
+DEF_OP_VV (plus, 4, int16_t, +)
+DEF_OP_VV (plus, 8, int16_t, +)
+DEF_OP_VV (plus, 16, int16_t, +)
+DEF_OP_VV (plus, 32, int16_t, +)
+DEF_OP_VV (plus, 64, int16_t, +)
+DEF_OP_VV (plus, 128, int16_t, +)
+DEF_OP_VV (plus, 256, int16_t, +)
+DEF_OP_VV (plus, 512, int16_t, +)
+DEF_OP_VV (plus, 1024, int16_t, +)
+DEF_OP_VV (plus, 2048, int16_t, +)
+
+DEF_OP_VV (plus, 1, int32_t, +)
+DEF_OP_VV (plus, 2, int32_t, +)
+DEF_OP_VV (plus, 4, int32_t, +)
+DEF_OP_VV (plus, 8, int32_t, +)
+DEF_OP_VV (plus, 16, int32_t, +)
+DEF_OP_VV (plus, 32, int32_t, +)
+DEF_OP_VV (plus, 64, int32_t, +)
+DEF_OP_VV (plus, 128, int32_t, +)
+DEF_OP_VV (plus, 256, int32_t, +)
+DEF_OP_VV (plus, 512, int32_t, +)
+DEF_OP_VV (plus, 1024, int32_t, +)
+
+DEF_OP_VV (plus, 1, int64_t, +)
+DEF_OP_VV (plus, 2, int64_t, +)
+DEF_OP_VV (plus, 4, int64_t, +)
+DEF_OP_VV (plus, 8, int64_t, +)
+DEF_OP_VV (plus, 16, int64_t, +)
+DEF_OP_VV (plus, 32, int64_t, +)
+DEF_OP_VV (plus, 64, int64_t, +)
+DEF_OP_VV (plus, 128, int64_t, +)
+DEF_OP_VV (plus, 256, int64_t, +)
+DEF_OP_VV (plus, 512, int64_t, +)
+
+/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
new file mode 100644
index 00000000000..6ce07194d14
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-2.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VI_M16 (plus, 1, int8_t, +)
+DEF_OP_VI_M16 (plus, 2, int8_t, +)
+DEF_OP_VI_M16 (plus, 4, int8_t, +)
+DEF_OP_VI_M16 (plus, 8, int8_t, +)
+DEF_OP_VI_M16 (plus, 16, int8_t, +)
+DEF_OP_VI_M16 (plus, 32, int8_t, +)
+DEF_OP_VI_M16 (plus, 64, int8_t, +)
+DEF_OP_VI_M16 (plus, 128, int8_t, +)
+DEF_OP_VI_M16 (plus, 256, int8_t, +)
+DEF_OP_VI_M16 (plus, 512, int8_t, +)
+DEF_OP_VI_M16 (plus, 1024, int8_t, +)
+DEF_OP_VI_M16 (plus, 2048, int8_t, +)
+DEF_OP_VI_M16 (plus, 4096, int8_t, +)
+
+DEF_OP_VI_M16 (plus, 1, int16_t, +)
+DEF_OP_VI_M16 (plus, 2, int16_t, +)
+DEF_OP_VI_M16 (plus, 4, int16_t, +)
+DEF_OP_VI_M16 (plus, 8, int16_t, +)
+DEF_OP_VI_M16 (plus, 16, int16_t, +)
+DEF_OP_VI_M16 (plus, 32, int16_t, +)
+DEF_OP_VI_M16 (plus, 64, int16_t, +)
+DEF_OP_VI_M16 (plus, 128, int16_t, +)
+DEF_OP_VI_M16 (plus, 256, int16_t, +)
+DEF_OP_VI_M16 (plus, 512, int16_t, +)
+DEF_OP_VI_M16 (plus, 1024, int16_t, +)
+DEF_OP_VI_M16 (plus, 2048, int16_t, +)
+
+DEF_OP_VI_M16 (plus, 1, int32_t, +)
+DEF_OP_VI_M16 (plus, 2, int32_t, +)
+DEF_OP_VI_M16 (plus, 4, int32_t, +)
+DEF_OP_VI_M16 (plus, 8, int32_t, +)
+DEF_OP_VI_M16 (plus, 16, int32_t, +)
+DEF_OP_VI_M16 (plus, 32, int32_t, +)
+DEF_OP_VI_M16 (plus, 64, int32_t, +)
+DEF_OP_VI_M16 (plus, 128, int32_t, +)
+DEF_OP_VI_M16 (plus, 256, int32_t, +)
+DEF_OP_VI_M16 (plus, 512, int32_t, +)
+DEF_OP_VI_M16 (plus, 1024, int32_t, +)
+
+DEF_OP_VI_M16 (plus, 1, int64_t, +)
+DEF_OP_VI_M16 (plus, 2, int64_t, +)
+DEF_OP_VI_M16 (plus, 4, int64_t, +)
+DEF_OP_VI_M16 (plus, 8, int64_t, +)
+DEF_OP_VI_M16 (plus, 16, int64_t, +)
+DEF_OP_VI_M16 (plus, 32, int64_t, +)
+DEF_OP_VI_M16 (plus, 64, int64_t, +)
+DEF_OP_VI_M16 (plus, 128, int64_t, +)
+DEF_OP_VI_M16 (plus, 256, int64_t, +)
+DEF_OP_VI_M16 (plus, 512, int64_t, +)
+
+/* { dg-final { scan-assembler-times {vadd\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
new file mode 100644
index 00000000000..c68b2bc7755
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/plus-3.c
@@ -0,0 +1,57 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8" } */
+
+#include "def.h"
+
+DEF_OP_VI_15 (plus, 1, int8_t, +)
+DEF_OP_VI_15 (plus, 2, int8_t, +)
+DEF_OP_VI_15 (plus, 4, int8_t, +)
+DEF_OP_VI_15 (plus, 8, int8_t, +)
+DEF_OP_VI_15 (plus, 16, int8_t, +)
+DEF_OP_VI_15 (plus, 32, int8_t, +)
+DEF_OP_VI_15 (plus, 64, int8_t, +)
+DEF_OP_VI_15 (plus, 128, int8_t, +)
+DEF_OP_VI_15 (plus, 256, int8_t, +)
+DEF_OP_VI_15 (plus, 512, int8_t, +)
+DEF_OP_VI_15 (plus, 1024, int8_t, +)
+DEF_OP_VI_15 (plus, 2048, int8_t, +)
+DEF_OP_VI_15 (plus, 4096, int8_t, +)
+
+DEF_OP_VI_15 (plus, 1, int16_t, +)
+DEF_OP_VI_15 (plus, 2, int16_t, +)
+DEF_OP_VI_15 (plus, 4, int16_t, +)
+DEF_OP_VI_15 (plus, 8, int16_t, +)
+DEF_OP_VI_15 (plus, 16, int16_t, +)
+DEF_OP_VI_15 (plus, 32, int16_t, +)
+DEF_OP_VI_15 (plus, 64, int16_t, +)
+DEF_OP_VI_15 (plus, 128, int16_t, +)
+DEF_OP_VI_15 (plus, 256, int16_t, +)
+DEF_OP_VI_15 (plus, 512, int16_t, +)
+DEF_OP_VI_15 (plus, 1024, int16_t, +)
+DEF_OP_VI_15 (plus, 2048, int16_t, +)
+
+DEF_OP_VI_15 (plus, 1, int32_t, +)
+DEF_OP_VI_15 (plus, 2, int32_t, +)
+DEF_OP_VI_15 (plus, 4, int32_t, +)
+DEF_OP_VI_15 (plus, 8, int32_t, +)
+DEF_OP_VI_15 (plus, 16, int32_t, +)
+DEF_OP_VI_15 (plus, 32, int32_t, +)
+DEF_OP_VI_15 (plus, 64, int32_t, +)
+DEF_OP_VI_15 (plus, 128, int32_t, +)
+DEF_OP_VI_15 (plus, 256, int32_t, +)
+DEF_OP_VI_15 (plus, 512, int32_t, +)
+DEF_OP_VI_15 (plus, 1024, int32_t, +)
+
+DEF_OP_VI_15 (plus, 1, int64_t, +)
+DEF_OP_VI_15 (plus, 2, int64_t, +)
+DEF_OP_VI_15 (plus, 4, int64_t, +)
+DEF_OP_VI_15 (plus, 8, int64_t, +)
+DEF_OP_VI_15 (plus, 16, int64_t, +)
+DEF_OP_VI_15 (plus, 32, int64_t, +)
+DEF_OP_VI_15 (plus, 64, int64_t, +)
+DEF_OP_VI_15 (plus, 128, int64_t, +)
+DEF_OP_VI_15 (plus, 256, int64_t, +)
+DEF_OP_VI_15 (plus, 512, int64_t, +)
+
+/* { dg-final { scan-assembler-times {vadd\.vi\s+v[0-9]+,\s*v[0-9]+,\s*15} 42 } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
--
2.36.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
2023-08-07 9:27 [PATCH] RISC-V: Support VLS basic operation auto-vectorization Juzhe-Zhong
@ 2023-08-07 19:46 ` Robin Dapp
2023-08-07 21:14 ` 钟居哲
0 siblings, 1 reply; 4+ messages in thread
From: Robin Dapp @ 2023-08-07 19:46 UTC (permalink / raw)
To: Juzhe-Zhong, gcc-patches; +Cc: rdapp.gcc, kito.cheng, kito.cheng, jeffreyalaw
Hi Juzhe,
thanks, looks good from my side.
> +/* { dg-final { scan-assembler-times {vand\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 42 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
I was actually looking for a scan-assembler-not vsetvli... but the
csrr will do as well.
Regards
Robin
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
2023-08-07 19:46 ` Robin Dapp
@ 2023-08-07 21:14 ` 钟居哲
2023-08-07 23:07 ` Li, Pan2
0 siblings, 1 reply; 4+ messages in thread
From: 钟居哲 @ 2023-08-07 21:14 UTC (permalink / raw)
To: rdapp.gcc, gcc-patches; +Cc: rdapp.gcc, kito.cheng, kito.cheng, Jeff Law
[-- Attachment #1: Type: text/plain, Size: 720 bytes --]
Thanks Robin.
Yes, we should not allow vsetvli rd,rs1 which is generated by SELECT_VL for partial vector auto-vectorzation.
But I believe scan-assembler-not csrr is enough.
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2023-08-08 03:46
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
Hi Juzhe,
thanks, looks good from my side.
> +/* { dg-final { scan-assembler-times {vand\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 42 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
I was actually looking for a scan-assembler-not vsetvli... but the
csrr will do as well.
Regards
Robin
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
2023-08-07 21:14 ` 钟居哲
@ 2023-08-07 23:07 ` Li, Pan2
0 siblings, 0 replies; 4+ messages in thread
From: Li, Pan2 @ 2023-08-07 23:07 UTC (permalink / raw)
To: 钟居哲, rdapp.gcc, gcc-patches
Cc: rdapp.gcc, kito.cheng, kito.cheng, Jeff Law
Committed, thanks Robin.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of ???
Sent: Tuesday, August 8, 2023 5:15 AM
To: rdapp.gcc <rdapp.gcc@gmail.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: rdapp.gcc <rdapp.gcc@gmail.com>; kito.cheng <kito.cheng@gmail.com>; kito.cheng <kito.cheng@sifive.com>; Jeff Law <jeffreyalaw@gmail.com>
Subject: Re: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
Thanks Robin.
Yes, we should not allow vsetvli rd,rs1 which is generated by SELECT_VL for partial vector auto-vectorzation.
But I believe scan-assembler-not csrr is enough.
juzhe.zhong@rivai.ai
From: Robin Dapp
Date: 2023-08-08 03:46
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
Hi Juzhe,
thanks, looks good from my side.
> +/* { dg-final { scan-assembler-times {vand\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16} 42 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
I was actually looking for a scan-assembler-not vsetvli... but the
csrr will do as well.
Regards
Robin
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-08-07 23:07 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2023-08-07 9:27 [PATCH] RISC-V: Support VLS basic operation auto-vectorization Juzhe-Zhong
2023-08-07 19:46 ` Robin Dapp
2023-08-07 21:14 ` 钟居哲
2023-08-07 23:07 ` Li, Pan2
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