From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
To: gcc-patches@gcc.gnu.org
Cc: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Subject: [Committed] RISC-V: Fix VSETVL VL check condition bug
Date: Wed, 8 Nov 2023 19:33:06 +0800 [thread overview]
Message-ID: <20231108113306.1820431-1-juzhe.zhong@rivai.ai> (raw)
When fixing the induction variable vectorization bug, notice there is a ICE bug
in VSETVL PASS:
0x178015b rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int, char const*)
../../../../gcc/gcc/rtl.cc:770
0x1079cdd rhs_regno(rtx_def const*)
../../../../gcc/gcc/rtl.h:1934
0x1dab360 vsetvl_info::parse_insn(rtl_ssa::insn_info*)
../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:1070
0x1daa272 vsetvl_info::vsetvl_info(rtl_ssa::insn_info*)
../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:746
0x1da5d98 pre_vsetvl::fuse_local_vsetvl_info()
../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:2708
0x1da94d9 pass_vsetvl::lazy_vsetvl()
../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3444
0x1da977c pass_vsetvl::execute(function*)
../../../../gcc/gcc/config/riscv/riscv-vsetvl.cc:3504
Committed as it is obvious.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc: Fix ICE.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vl-use-ice.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 2 +-
gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c | 11 +++++++++++
2 files changed, 12 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 77dbf159d41..3fa25a6404d 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1067,7 +1067,7 @@ public:
break;
}
rtx avl = ::get_avl (rinsn);
- if (!avl || REGNO (get_vl ()) != REGNO (avl))
+ if (!avl || !REG_P (avl) || REGNO (get_vl ()) != REGNO (avl))
{
m_vl_used_by_non_rvv_insn = true;
break;
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c
new file mode 100644
index 00000000000..715c7e0cad2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vl-use-ice.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d" } */
+
+#include "riscv_vector.h"
+
+void foo(void *in1, void *out, size_t avl) {
+
+ size_t vl = __riscv_vsetvl_e32m1(avl);
+ vint32m1_t v = __riscv_vmv_v_x_i32m1 (vl, 16);
+ __riscv_vse32_v_i32m1 (out, v, 16);
+}
--
2.36.3
reply other threads:[~2023-11-08 11:33 UTC|newest]
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