* [PATCH v2 1/2] LoongArch: Switch loongarch-def from C to C++ to make it possible.
2023-12-05 2:30 [PATCH v2 0/2] Delete ISA_BASE_LA64V110 related definitions Lulu Cheng
@ 2023-12-05 2:30 ` Lulu Cheng
2023-12-05 2:30 ` [PATCH v2 2/2] LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code Lulu Cheng
2023-12-08 7:39 ` [pushed][PATCH v2 0/2] Delete ISA_BASE_LA64V110 related definitions chenglulu
2 siblings, 0 replies; 4+ messages in thread
From: Lulu Cheng @ 2023-12-05 2:30 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu
From: Xi Ruoyao <xry111@xry111.site>
We'll use HOST_WIDE_INT in LoongArch static properties in following patches.
To keep the same readability as C99 designated initializers, create a
std::array like data structure with position setter function, and add
field setter functions for structs used in loongarch-def.cc.
Remove unneeded guards #if
!defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
in loongarch-def.h and loongarch-opts.h.
gcc/ChangeLog:
* config/loongarch/loongarch-def.h: Remove extern "C".
(loongarch_isa_base_strings): Declare as loongarch_def_array
instead of plain array.
(loongarch_isa_ext_strings): Likewise.
(loongarch_abi_base_strings): Likewise.
(loongarch_abi_ext_strings): Likewise.
(loongarch_cmodel_strings): Likewise.
(loongarch_cpu_strings): Likewise.
(loongarch_cpu_default_isa): Likewise.
(loongarch_cpu_issue_rate): Likewise.
(loongarch_cpu_multipass_dfa_lookahead): Likewise.
(loongarch_cpu_cache): Likewise.
(loongarch_cpu_align): Likewise.
(loongarch_cpu_rtx_cost_data): Likewise.
(loongarch_isa): Add a constructor and field setter functions.
* config/loongarch/loongarch-opts.h (loongarch-defs.h): Do not
include for target libraries.
* config/loongarch/loongarch-tune.h (LOONGARCH_TUNE_H): Likewise.
(struct loongarch_rtx_cost_data): Likewise.
(struct loongarch_cache): Likewise.
(struct loongarch_align): Likewise.
* config/loongarch/t-loongarch: Compile loongarch-def.cc with the
C++ compiler.
* config/loongarch/loongarch-def-array.h: New file for a
std:array like data structure with position setter function.
* config/loongarch/loongarch-def.c: Rename to ...
* config/loongarch/loongarch-def.cc: ... here.
(loongarch_cpu_strings): Define as loongarch_def_array instead
of plain array.
(loongarch_cpu_default_isa): Likewise.
(loongarch_cpu_cache): Likewise.
(loongarch_cpu_align): Likewise.
(loongarch_cpu_rtx_cost_data): Likewise.
(loongarch_cpu_issue_rate): Likewise.
(loongarch_cpu_multipass_dfa_lookahead): Likewise.
(loongarch_isa_base_strings): Likewise.
(loongarch_isa_ext_strings): Likewise.
(loongarch_abi_base_strings): Likewise.
(loongarch_abi_ext_strings): Likewise.
(loongarch_cmodel_strings): Likewise.
(abi_minimal_isa): Likewise.
(loongarch_rtx_cost_optimize_size): Use field setter functions
instead of designated initializers.
(loongarch_rtx_cost_data): Implement default constructor.
---
gcc/config/loongarch/loongarch-def-array.h | 40 ++++
gcc/config/loongarch/loongarch-def.c | 227 ---------------------
gcc/config/loongarch/loongarch-def.cc | 187 +++++++++++++++++
gcc/config/loongarch/loongarch-def.h | 55 ++---
gcc/config/loongarch/loongarch-opts.cc | 7 +
gcc/config/loongarch/loongarch-opts.h | 5 +-
gcc/config/loongarch/loongarch-tune.h | 123 ++++++++++-
gcc/config/loongarch/t-loongarch | 4 +-
8 files changed, 390 insertions(+), 258 deletions(-)
create mode 100644 gcc/config/loongarch/loongarch-def-array.h
delete mode 100644 gcc/config/loongarch/loongarch-def.c
create mode 100644 gcc/config/loongarch/loongarch-def.cc
diff --git a/gcc/config/loongarch/loongarch-def-array.h b/gcc/config/loongarch/loongarch-def-array.h
new file mode 100644
index 00000000000..bdb3e9c6a2b
--- /dev/null
+++ b/gcc/config/loongarch/loongarch-def-array.h
@@ -0,0 +1,40 @@
+/* A std::array like data structure for LoongArch static properties.
+ Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef _LOONGARCH_DEF_ARRAY_H
+#define _LOONGARCH_DEF_ARRAY_H 1
+
+template <class T, int N>
+class loongarch_def_array {
+private:
+ T arr[N];
+public:
+ loongarch_def_array () : arr{} {}
+
+ T &operator[] (int n) { return arr[n]; }
+ const T &operator[] (int n) const { return arr[n]; }
+
+ loongarch_def_array set (int idx, T &&value)
+ {
+ (*this)[idx] = value;
+ return *this;
+ }
+};
+
+#endif
diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
deleted file mode 100644
index f22d488acb2..00000000000
--- a/gcc/config/loongarch/loongarch-def.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* LoongArch static properties.
- Copyright (C) 2021-2023 Free Software Foundation, Inc.
- Contributed by Loongson Ltd.
-
-This file is part of GCC.
-
-GCC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 3, or (at your option)
-any later version.
-
-GCC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GCC; see the file COPYING3. If not see
-<http://www.gnu.org/licenses/>. */
-
-#include "loongarch-def.h"
-#include "loongarch-str.h"
-
-/* CPU property tables. */
-const char*
-loongarch_cpu_strings[N_TUNE_TYPES] = {
- [CPU_NATIVE] = STR_CPU_NATIVE,
- [CPU_ABI_DEFAULT] = STR_CPU_ABI_DEFAULT,
- [CPU_LOONGARCH64] = STR_CPU_LOONGARCH64,
- [CPU_LA464] = STR_CPU_LA464,
- [CPU_LA664] = STR_CPU_LA664,
-};
-
-struct loongarch_isa
-loongarch_cpu_default_isa[N_ARCH_TYPES] = {
- [CPU_LOONGARCH64] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_FPU64,
- .simd = 0,
- },
- [CPU_LA464] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_FPU64,
- .simd = ISA_EXT_SIMD_LASX,
- },
- [CPU_LA664] = {
- .base = ISA_BASE_LA64V110,
- .fpu = ISA_EXT_FPU64,
- .simd = ISA_EXT_SIMD_LASX,
- },
-};
-
-struct loongarch_cache
-loongarch_cpu_cache[N_TUNE_TYPES] = {
- [CPU_LOONGARCH64] = {
- .l1d_line_size = 64,
- .l1d_size = 64,
- .l2d_size = 256,
- .simultaneous_prefetches = 4,
- },
- [CPU_LA464] = {
- .l1d_line_size = 64,
- .l1d_size = 64,
- .l2d_size = 256,
- .simultaneous_prefetches = 4,
- },
- [CPU_LA664] = {
- .l1d_line_size = 64,
- .l1d_size = 64,
- .l2d_size = 256,
- .simultaneous_prefetches = 4,
- },
-};
-
-struct loongarch_align
-loongarch_cpu_align[N_TUNE_TYPES] = {
- [CPU_LOONGARCH64] = {
- .function = "32",
- .label = "16",
- },
- [CPU_LA464] = {
- .function = "32",
- .label = "16",
- },
- [CPU_LA664] = {
- .function = "32",
- .label = "16",
- },
-};
-
-
-/* Default RTX cost initializer. */
-#define COSTS_N_INSNS(N) ((N) * 4)
-#define DEFAULT_COSTS \
- .fp_add = COSTS_N_INSNS (1), \
- .fp_mult_sf = COSTS_N_INSNS (2), \
- .fp_mult_df = COSTS_N_INSNS (4), \
- .fp_div_sf = COSTS_N_INSNS (6), \
- .fp_div_df = COSTS_N_INSNS (8), \
- .int_mult_si = COSTS_N_INSNS (1), \
- .int_mult_di = COSTS_N_INSNS (1), \
- .int_div_si = COSTS_N_INSNS (4), \
- .int_div_di = COSTS_N_INSNS (6), \
- .branch_cost = 6, \
- .memory_latency = 4
-
-/* The following properties cannot be looked up directly using "cpucfg".
- So it is necessary to provide a default value for "unknown native"
- tune targets (i.e. -mtune=native while PRID does not correspond to
- any known "-mtune" type). */
-
-struct loongarch_rtx_cost_data
-loongarch_cpu_rtx_cost_data[N_TUNE_TYPES] = {
- [CPU_NATIVE] = {
- DEFAULT_COSTS
- },
- [CPU_LOONGARCH64] = {
- DEFAULT_COSTS
- },
- [CPU_LA464] = {
- DEFAULT_COSTS
- },
- [CPU_LA664] = {
- DEFAULT_COSTS
- },
-};
-
-/* RTX costs to use when optimizing for size. */
-const struct loongarch_rtx_cost_data
-loongarch_rtx_cost_optimize_size = {
- .fp_add = 4,
- .fp_mult_sf = 4,
- .fp_mult_df = 4,
- .fp_div_sf = 4,
- .fp_div_df = 4,
- .int_mult_si = 4,
- .int_mult_di = 4,
- .int_div_si = 4,
- .int_div_di = 4,
- .branch_cost = 6,
- .memory_latency = 4,
-};
-
-int
-loongarch_cpu_issue_rate[N_TUNE_TYPES] = {
- [CPU_NATIVE] = 4,
- [CPU_LOONGARCH64] = 4,
- [CPU_LA464] = 4,
- [CPU_LA664] = 6,
-};
-
-int
-loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
- [CPU_NATIVE] = 4,
- [CPU_LOONGARCH64] = 4,
- [CPU_LA464] = 4,
- [CPU_LA664] = 6,
-};
-
-/* Wiring string definitions from loongarch-str.h to global arrays
- with standard index values from loongarch-opts.h, so we can
- print config-related messages and do ABI self-spec filtering
- from the driver in a self-consistent manner. */
-
-const char*
-loongarch_isa_base_strings[N_ISA_BASE_TYPES] = {
- [ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100,
- [ISA_BASE_LA64V110] = STR_ISA_BASE_LA64V110,
-};
-
-const char*
-loongarch_isa_ext_strings[N_ISA_EXT_TYPES] = {
- [ISA_EXT_NONE] = STR_NONE,
- [ISA_EXT_FPU32] = STR_ISA_EXT_FPU32,
- [ISA_EXT_FPU64] = STR_ISA_EXT_FPU64,
- [ISA_EXT_SIMD_LSX] = STR_ISA_EXT_LSX,
- [ISA_EXT_SIMD_LASX] = STR_ISA_EXT_LASX,
-};
-
-const char*
-loongarch_abi_base_strings[N_ABI_BASE_TYPES] = {
- [ABI_BASE_LP64D] = STR_ABI_BASE_LP64D,
- [ABI_BASE_LP64F] = STR_ABI_BASE_LP64F,
- [ABI_BASE_LP64S] = STR_ABI_BASE_LP64S,
-};
-
-const char*
-loongarch_abi_ext_strings[N_ABI_EXT_TYPES] = {
- [ABI_EXT_BASE] = STR_ABI_EXT_BASE,
-};
-
-const char*
-loongarch_cmodel_strings[] = {
- [CMODEL_NORMAL] = STR_CMODEL_NORMAL,
- [CMODEL_TINY] = STR_CMODEL_TINY,
- [CMODEL_TINY_STATIC] = STR_CMODEL_TS,
- [CMODEL_MEDIUM] = STR_CMODEL_MEDIUM,
- [CMODEL_LARGE] = STR_CMODEL_LARGE,
- [CMODEL_EXTREME] = STR_CMODEL_EXTREME,
-};
-
-
-/* ABI-related definitions. */
-const struct loongarch_isa
-abi_minimal_isa[N_ABI_BASE_TYPES][N_ABI_EXT_TYPES] = {
- [ABI_BASE_LP64D] = {
- [ABI_EXT_BASE] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_FPU64,
- .simd = 0
- },
- },
- [ABI_BASE_LP64F] = {
- [ABI_EXT_BASE] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_FPU32,
- .simd = 0
- },
- },
- [ABI_BASE_LP64S] = {
- [ABI_EXT_BASE] = {
- .base = ISA_BASE_LA64V100,
- .fpu = ISA_EXT_NONE,
- .simd = 0
- },
- },
-};
diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc
new file mode 100644
index 00000000000..6990c86c2c4
--- /dev/null
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -0,0 +1,187 @@
+/* LoongArch static properties.
+ Copyright (C) 2021-2023 Free Software Foundation, Inc.
+ Contributed by Loongson Ltd.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#include "loongarch-def.h"
+#include "loongarch-str.h"
+
+template <class T, int N>
+using array = loongarch_def_array<T, N>;
+
+template <class T>
+using array_tune = array<T, N_TUNE_TYPES>;
+
+template <class T>
+using array_arch = array<T, N_ARCH_TYPES>;
+
+/* CPU property tables. */
+array_tune<const char *> loongarch_cpu_strings = array_tune<const char *> ()
+ .set (CPU_NATIVE, STR_CPU_NATIVE)
+ .set (CPU_ABI_DEFAULT, STR_CPU_ABI_DEFAULT)
+ .set (CPU_LOONGARCH64, STR_CPU_LOONGARCH64)
+ .set (CPU_LA464, STR_CPU_LA464)
+ .set (CPU_LA664, STR_CPU_LA664);
+
+array_arch<loongarch_isa> loongarch_cpu_default_isa =
+ array_arch<loongarch_isa> ()
+ .set (CPU_LOONGARCH64,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU64))
+ .set (CPU_LA464,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU64)
+ .simd_ (ISA_EXT_SIMD_LASX))
+ .set (CPU_LA664,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V110)
+ .fpu_ (ISA_EXT_FPU64)
+ .simd_ (ISA_EXT_SIMD_LASX));
+
+static inline loongarch_cache la464_cache ()
+{
+ return loongarch_cache ()
+ .l1d_line_size_ (64)
+ .l1d_size_ (64)
+ .l2d_size_ (256)
+ .simultaneous_prefetches_ (4);
+}
+
+array_tune<loongarch_cache> loongarch_cpu_cache =
+ array_tune<loongarch_cache> ()
+ .set (CPU_LOONGARCH64, la464_cache ())
+ .set (CPU_LA464, la464_cache ())
+ .set (CPU_LA664, la464_cache ());
+
+static inline loongarch_align la464_align ()
+{
+ return loongarch_align ().function_ ("32").label_ ("16");
+}
+
+array_tune<loongarch_align> loongarch_cpu_align =
+ array_tune<loongarch_align> ()
+ .set (CPU_LOONGARCH64, la464_align ())
+ .set (CPU_LA464, la464_align ())
+ .set (CPU_LA664, la464_align ());
+
+#define COSTS_N_INSNS(N) ((N) * 4)
+
+/* Default RTX cost initializer. */
+loongarch_rtx_cost_data::loongarch_rtx_cost_data ()
+ : fp_add (COSTS_N_INSNS (1)),
+ fp_mult_sf (COSTS_N_INSNS (2)),
+ fp_mult_df (COSTS_N_INSNS (4)),
+ fp_div_sf (COSTS_N_INSNS (6)),
+ fp_div_df (COSTS_N_INSNS (8)),
+ int_mult_si (COSTS_N_INSNS (1)),
+ int_mult_di (COSTS_N_INSNS (1)),
+ int_div_si (COSTS_N_INSNS (4)),
+ int_div_di (COSTS_N_INSNS (6)),
+ branch_cost (6),
+ memory_latency (4) {}
+
+/* The following properties cannot be looked up directly using "cpucfg".
+ So it is necessary to provide a default value for "unknown native"
+ tune targets (i.e. -mtune=native while PRID does not correspond to
+ any known "-mtune" type). Currently all numbers are default. */
+array_tune<loongarch_rtx_cost_data> loongarch_cpu_rtx_cost_data =
+ array_tune<loongarch_rtx_cost_data> ();
+
+/* RTX costs to use when optimizing for size. */
+const loongarch_rtx_cost_data loongarch_rtx_cost_optimize_size =
+ loongarch_rtx_cost_data ()
+ .fp_add_ (4)
+ .fp_mult_sf_ (4)
+ .fp_mult_df_ (4)
+ .fp_div_sf_ (4)
+ .fp_div_df_ (4)
+ .int_mult_si_ (4)
+ .int_mult_di_ (4)
+ .int_div_si_ (4)
+ .int_div_di_ (4);
+
+array_tune<int> loongarch_cpu_issue_rate = array_tune<int> ()
+ .set (CPU_NATIVE, 4)
+ .set (CPU_LOONGARCH64, 4)
+ .set (CPU_LA464, 4)
+ .set (CPU_LA664, 6);
+
+array_tune<int> loongarch_cpu_multipass_dfa_lookahead = array_tune<int> ()
+ .set (CPU_NATIVE, 4)
+ .set (CPU_LOONGARCH64, 4)
+ .set (CPU_LA464, 4)
+ .set (CPU_LA664, 6);
+
+/* Wiring string definitions from loongarch-str.h to global arrays
+ with standard index values from loongarch-opts.h, so we can
+ print config-related messages and do ABI self-spec filtering
+ from the driver in a self-consistent manner. */
+
+array<const char *, N_ISA_BASE_TYPES> loongarch_isa_base_strings =
+ array<const char *, N_ISA_BASE_TYPES> ()
+ .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100)
+ .set (ISA_BASE_LA64V110, STR_ISA_BASE_LA64V110);
+
+array<const char *, N_ISA_EXT_TYPES> loongarch_isa_ext_strings =
+ array<const char *, N_ISA_EXT_TYPES> ()
+ .set (ISA_EXT_NONE, STR_NONE)
+ .set (ISA_EXT_FPU32, STR_ISA_EXT_FPU32)
+ .set (ISA_EXT_FPU64, STR_ISA_EXT_FPU64)
+ .set (ISA_EXT_SIMD_LSX, STR_ISA_EXT_LSX)
+ .set (ISA_EXT_SIMD_LASX, STR_ISA_EXT_LASX);
+
+array<const char *, N_ABI_BASE_TYPES> loongarch_abi_base_strings =
+ array<const char *, N_ABI_BASE_TYPES> ()
+ .set (ABI_BASE_LP64D, STR_ABI_BASE_LP64D)
+ .set (ABI_BASE_LP64F, STR_ABI_BASE_LP64F)
+ .set (ABI_BASE_LP64S, STR_ABI_BASE_LP64S);
+
+array<const char *, N_ABI_EXT_TYPES> loongarch_abi_ext_strings =
+ array<const char *, N_ABI_EXT_TYPES> ()
+ .set (ABI_EXT_BASE, STR_ABI_EXT_BASE);
+
+array<const char *, N_CMODEL_TYPES> loongarch_cmodel_strings =
+ array<const char *, N_CMODEL_TYPES> ()
+ .set (CMODEL_NORMAL, STR_CMODEL_NORMAL)
+ .set (CMODEL_TINY, STR_CMODEL_TINY)
+ .set (CMODEL_TINY_STATIC, STR_CMODEL_TS)
+ .set (CMODEL_MEDIUM, STR_CMODEL_MEDIUM)
+ .set (CMODEL_LARGE, STR_CMODEL_LARGE)
+ .set (CMODEL_EXTREME, STR_CMODEL_EXTREME);
+
+array<array<loongarch_isa, N_ABI_EXT_TYPES>, N_ABI_BASE_TYPES>
+ abi_minimal_isa = array<array<loongarch_isa, N_ABI_EXT_TYPES>,
+ N_ABI_BASE_TYPES> ()
+ .set (ABI_BASE_LP64D,
+ array<loongarch_isa, N_ABI_EXT_TYPES> ()
+ .set (ABI_EXT_BASE,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU64)))
+ .set (ABI_BASE_LP64F,
+ array<loongarch_isa, N_ABI_EXT_TYPES> ()
+ .set (ABI_EXT_BASE,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU32)))
+ .set (ABI_BASE_LP64S,
+ array<loongarch_isa, N_ABI_EXT_TYPES> ()
+ .set (ABI_EXT_BASE,
+ loongarch_isa ().base_ (ISA_BASE_LA64V100)));
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 851ff864eb2..68a9a461e54 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -50,20 +50,18 @@ along with GCC; see the file COPYING3. If not see
#include <stdint.h>
#endif
+#include "loongarch-def-array.h"
#include "loongarch-tune.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
/* enum isa_base */
-extern const char* loongarch_isa_base_strings[];
/* LoongArch V1.00. */
#define ISA_BASE_LA64V100 0
/* LoongArch V1.10. */
#define ISA_BASE_LA64V110 1
#define N_ISA_BASE_TYPES 2
+extern loongarch_def_array<const char *, N_ISA_BASE_TYPES>
+ loongarch_isa_base_strings;
#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is
@@ -72,7 +70,6 @@ extern int64_t loongarch_isa_base_features[];
#endif
/* enum isa_ext_* */
-extern const char* loongarch_isa_ext_strings[];
#define ISA_EXT_NONE 0
#define ISA_EXT_FPU32 1
#define ISA_EXT_FPU64 2
@@ -80,13 +77,16 @@ extern const char* loongarch_isa_ext_strings[];
#define ISA_EXT_SIMD_LSX 3
#define ISA_EXT_SIMD_LASX 4
#define N_ISA_EXT_TYPES 5
+extern loongarch_def_array<const char *, N_ISA_EXT_TYPES>
+ loongarch_isa_ext_strings;
/* enum abi_base */
-extern const char* loongarch_abi_base_strings[];
#define ABI_BASE_LP64D 0
#define ABI_BASE_LP64F 1
#define ABI_BASE_LP64S 2
#define N_ABI_BASE_TYPES 3
+extern loongarch_def_array<const char *, N_ABI_BASE_TYPES>
+ loongarch_abi_base_strings;
#define TO_LP64_ABI_BASE(C) (C)
@@ -99,12 +99,12 @@ extern const char* loongarch_abi_base_strings[];
/* enum abi_ext */
-extern const char* loongarch_abi_ext_strings[];
#define ABI_EXT_BASE 0
#define N_ABI_EXT_TYPES 1
+extern loongarch_def_array<const char *, N_ABI_EXT_TYPES>
+ loongarch_abi_ext_strings;
/* enum cmodel */
-extern const char* loongarch_cmodel_strings[];
#define CMODEL_NORMAL 0
#define CMODEL_TINY 1
#define CMODEL_TINY_STATIC 2
@@ -112,6 +112,8 @@ extern const char* loongarch_cmodel_strings[];
#define CMODEL_LARGE 4
#define CMODEL_EXTREME 5
#define N_CMODEL_TYPES 6
+extern loongarch_def_array<const char *, N_CMODEL_TYPES>
+ loongarch_cmodel_strings;
/* enum explicit_relocs */
#define EXPLICIT_RELOCS_AUTO 0
@@ -126,7 +128,6 @@ extern const char* loongarch_cmodel_strings[];
#define M_OPT_ABSENT(opt_enum) ((opt_enum) == M_OPT_UNSET)
-#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
/* Internal representation of the target. */
struct loongarch_isa
{
@@ -139,6 +140,13 @@ struct loongarch_isa
Using int64_t instead of HOST_WIDE_INT for C compatibility. */
int64_t evolution;
+
+ loongarch_isa () : base (0), fpu (0), simd (0), evolution (0) {}
+ loongarch_isa base_ (int _base) { base = _base; return *this; }
+ loongarch_isa fpu_ (int _fpu) { fpu = _fpu; return *this; }
+ loongarch_isa simd_ (int _simd) { simd = _simd; return *this; }
+ loongarch_isa evolution_ (int64_t _evolution)
+ { evolution = _evolution; return *this; }
};
struct loongarch_abi
@@ -156,9 +164,6 @@ struct loongarch_target
int cmodel; /* CMODEL_ */
};
-extern struct loongarch_isa loongarch_cpu_default_isa[];
-#endif
-
/* CPU properties. */
/* index */
#define CPU_NATIVE 0
@@ -170,15 +175,19 @@ extern struct loongarch_isa loongarch_cpu_default_isa[];
#define N_TUNE_TYPES 5
/* parallel tables. */
-extern const char* loongarch_cpu_strings[];
-extern int loongarch_cpu_issue_rate[];
-extern int loongarch_cpu_multipass_dfa_lookahead[];
+extern loongarch_def_array<const char *, N_ARCH_TYPES>
+ loongarch_cpu_strings;
+extern loongarch_def_array<loongarch_isa, N_ARCH_TYPES>
+ loongarch_cpu_default_isa;
+extern loongarch_def_array<int, N_TUNE_TYPES>
+ loongarch_cpu_issue_rate;
+extern loongarch_def_array<int, N_TUNE_TYPES>
+ loongarch_cpu_multipass_dfa_lookahead;
+extern loongarch_def_array<loongarch_cache, N_TUNE_TYPES>
+ loongarch_cpu_cache;
+extern loongarch_def_array<loongarch_align, N_TUNE_TYPES>
+ loongarch_cpu_align;
+extern loongarch_def_array<loongarch_rtx_cost_data, N_TUNE_TYPES>
+ loongarch_cpu_rtx_cost_data;
-extern struct loongarch_cache loongarch_cpu_cache[];
-extern struct loongarch_align loongarch_cpu_align[];
-extern struct loongarch_rtx_cost_data loongarch_cpu_rtx_cost_data[];
-
-#ifdef __cplusplus
-}
-#endif
#endif /* LOONGARCH_DEF_H */
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index b5836f198c0..7b63ef57a2a 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -163,6 +163,7 @@ loongarch_config_target (struct loongarch_target *target,
int follow_multilib_list_p)
{
struct loongarch_target t;
+
if (!target)
return;
@@ -657,12 +658,18 @@ abi_str (struct loongarch_abi abi)
strlen (loongarch_abi_base_strings[abi.base]));
else
{
+ /* This situation has not yet occurred, so in order to avoid the
+ -Warray-bounds warning during C++ syntax checking, this part
+ of the code is commented first. */
+ /*
APPEND_STRING (loongarch_abi_base_strings[abi.base])
APPEND1 ('/')
APPEND_STRING (loongarch_abi_ext_strings[abi.ext])
APPEND1 ('\0')
return XOBFINISH (&msg_obstack, const char *);
+ */
+ gcc_unreachable ();
}
}
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index fa3773223bc..e1ec702335d 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -21,7 +21,10 @@ along with GCC; see the file COPYING3. If not see
#ifndef LOONGARCH_OPTS_H
#define LOONGARCH_OPTS_H
+/* This is a C++ header and it shouldn't be used by target libraries. */
+#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
#include "loongarch-def.h"
+#endif
/* Target configuration */
extern struct loongarch_target la_target;
@@ -33,7 +36,6 @@ struct loongarch_flags {
int sx[2];
};
-#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
/* Initialize loongarch_target from separate option variables. */
void
@@ -54,7 +56,6 @@ void
loongarch_update_gcc_opt_status (struct loongarch_target *target,
struct gcc_options *opts,
struct gcc_options *opts_set);
-#endif
/* Macros for common conditional expressions used in loongarch.{c,h,md} */
diff --git a/gcc/config/loongarch/loongarch-tune.h b/gcc/config/loongarch/loongarch-tune.h
index 5c03262daff..4aa01c54c08 100644
--- a/gcc/config/loongarch/loongarch-tune.h
+++ b/gcc/config/loongarch/loongarch-tune.h
@@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see
#ifndef LOONGARCH_TUNE_H
#define LOONGARCH_TUNE_H
+#include "loongarch-def-array.h"
+
/* RTX costs of various operations on the different architectures. */
struct loongarch_rtx_cost_data
{
@@ -35,6 +37,76 @@ struct loongarch_rtx_cost_data
unsigned short int_div_di;
unsigned short branch_cost;
unsigned short memory_latency;
+
+ /* Default RTX cost initializer, implemented in loongarch-def.cc. */
+ loongarch_rtx_cost_data ();
+
+ loongarch_rtx_cost_data fp_add_ (unsigned short _fp_add)
+ {
+ fp_add = _fp_add;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data fp_mult_sf_ (unsigned short _fp_mult_sf)
+ {
+ fp_mult_sf = _fp_mult_sf;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data fp_mult_df_ (unsigned short _fp_mult_df)
+ {
+ fp_mult_df = _fp_mult_df;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data fp_div_sf_ (unsigned short _fp_div_sf)
+ {
+ fp_div_sf = _fp_div_sf;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data fp_div_df_ (unsigned short _fp_div_df)
+ {
+ fp_div_df = _fp_div_df;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data int_mult_si_ (unsigned short _int_mult_si)
+ {
+ int_mult_si = _int_mult_si;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data int_mult_di_ (unsigned short _int_mult_di)
+ {
+ int_mult_di = _int_mult_di;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data int_div_si_ (unsigned short _int_div_si)
+ {
+ int_div_si = _int_div_si;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data int_div_di_ (unsigned short _int_div_di)
+ {
+ int_div_di = _int_div_di;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data branch_cost_ (unsigned short _branch_cost)
+ {
+ branch_cost = _branch_cost;
+ return *this;
+ }
+
+ loongarch_rtx_cost_data memory_latency_ (unsigned short _memory_latency)
+ {
+ memory_latency = _memory_latency;
+ return *this;
+ }
+
};
/* Costs to use when optimizing for size. */
@@ -42,10 +114,39 @@ extern const struct loongarch_rtx_cost_data loongarch_rtx_cost_optimize_size;
/* Cache size record of known processor models. */
struct loongarch_cache {
- int l1d_line_size; /* bytes */
- int l1d_size; /* KiB */
- int l2d_size; /* kiB */
- int simultaneous_prefetches; /* number of parallel prefetch */
+ int l1d_line_size; /* bytes */
+ int l1d_size; /* KiB */
+ int l2d_size; /* kiB */
+ int simultaneous_prefetches; /* number of parallel prefetch */
+
+ loongarch_cache () : l1d_line_size (0),
+ l1d_size (0),
+ l2d_size (0),
+ simultaneous_prefetches (0) {}
+
+ loongarch_cache l1d_line_size_ (int _l1d_line_size)
+ {
+ l1d_line_size = _l1d_line_size;
+ return *this;
+ }
+
+ loongarch_cache l1d_size_ (int _l1d_size)
+ {
+ l1d_size = _l1d_size;
+ return *this;
+ }
+
+ loongarch_cache l2d_size_ (int _l2d_size)
+ {
+ l2d_size = _l2d_size;
+ return *this;
+ }
+
+ loongarch_cache simultaneous_prefetches_ (int _simultaneous_prefetches)
+ {
+ simultaneous_prefetches = _simultaneous_prefetches;
+ return *this;
+ }
};
/* Alignment for functions and labels for best performance. For new uarchs
@@ -54,6 +155,20 @@ struct loongarch_cache {
struct loongarch_align {
const char *function; /* default value for -falign-functions */
const char *label; /* default value for -falign-labels */
+
+ loongarch_align () : function (nullptr), label (nullptr) {}
+
+ loongarch_align function_ (const char *_function)
+ {
+ function = _function;
+ return *this;
+ }
+
+ loongarch_align label_ (const char *_label)
+ {
+ label = _label;
+ return *this;
+ }
};
#endif /* LOONGARCH_TUNE_H */
diff --git a/gcc/config/loongarch/t-loongarch b/gcc/config/loongarch/t-loongarch
index 7e65bb6e2a8..10a984f3cb1 100644
--- a/gcc/config/loongarch/t-loongarch
+++ b/gcc/config/loongarch/t-loongarch
@@ -64,8 +64,8 @@ loongarch-cpu.o: $(srcdir)/config/loongarch/loongarch-cpu.cc $(LA_STR_H) \
$(srcdir)/config/loongarch/loongarch-cpucfg-map.h
$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
-loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.c $(LA_STR_H)
- $(CC) -c $(ALL_CFLAGS) $(INCLUDES) $<
+loongarch-def.o: $(srcdir)/config/loongarch/loongarch-def.cc $(LA_STR_H)
+ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
$(srcdir)/config/loongarch/loongarch.opt: s-loongarch-opt ; @true
s-loongarch-opt: $(srcdir)/config/loongarch/genopts/genstr.sh \
--
2.31.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v2 2/2] LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code.
2023-12-05 2:30 [PATCH v2 0/2] Delete ISA_BASE_LA64V110 related definitions Lulu Cheng
2023-12-05 2:30 ` [PATCH v2 1/2] LoongArch: Switch loongarch-def from C to C++ to make it possible Lulu Cheng
@ 2023-12-05 2:30 ` Lulu Cheng
2023-12-08 7:39 ` [pushed][PATCH v2 0/2] Delete ISA_BASE_LA64V110 related definitions chenglulu
2 siblings, 0 replies; 4+ messages in thread
From: Lulu Cheng @ 2023-12-05 2:30 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, i, xuchenghua, chenglulu
The instructions defined in LoongArch Reference Manual v1.1 are not the instruction
set v1.1 version. The CPU defined later may only support some instructions in
LoongArch Reference Manual v1.1. Therefore, the macro ISA_BASE_LA64V110 and
related definitions are removed here.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Delete STR_ISA_BASE_LA64V110.
* config/loongarch/genopts/loongarch.opt.in: Likewise.
* config/loongarch/loongarch-cpu.cc (ISA_BASE_LA64V110_FEATURES): Delete macro.
(fill_native_cpu_config): Define a new variable hw_isa_evolution record the
extended instruction set support read from cpucfg.
* config/loongarch/loongarch-def.cc: Set evolution at initialization.
* config/loongarch/loongarch-def.h (ISA_BASE_LA64V100): Delete.
(ISA_BASE_LA64V110): Likewise.
(N_ISA_BASE_TYPES): Likewise.
(defined): Likewise.
* config/loongarch/loongarch-opts.cc: Likewise.
* config/loongarch/loongarch-opts.h (TARGET_64BIT): Likewise.
(ISA_BASE_IS_LA64V110): Likewise.
* config/loongarch/loongarch-str.h (STR_ISA_BASE_LA64V110): Likewise.
* config/loongarch/loongarch.opt: Regenerate.
---
.../loongarch/genopts/loongarch-strings | 1 -
gcc/config/loongarch/genopts/loongarch.opt.in | 3 ---
gcc/config/loongarch/loongarch-cpu.cc | 23 +++++--------------
gcc/config/loongarch/loongarch-def.cc | 14 +++++++----
gcc/config/loongarch/loongarch-def.h | 12 ++--------
gcc/config/loongarch/loongarch-opts.cc | 3 ---
gcc/config/loongarch/loongarch-opts.h | 4 +---
gcc/config/loongarch/loongarch-str.h | 1 -
gcc/config/loongarch/loongarch.opt | 3 ---
9 files changed, 19 insertions(+), 45 deletions(-)
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index b2070c83ed0..7bc4824007e 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -30,7 +30,6 @@ STR_CPU_LA664 la664
# Base architecture
STR_ISA_BASE_LA64V100 la64
-STR_ISA_BASE_LA64V110 la64v1.1
# -mfpu
OPTSTR_ISA_EXT_FPU fpu
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 8af6cc6f532..483b185b059 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -32,9 +32,6 @@ Basic ISAs of LoongArch:
EnumValue
Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100)
-EnumValue
-Enum(isa_base) String(@@STR_ISA_BASE_LA64V110@@) Value(ISA_BASE_LA64V110)
-
;; ISA extensions / adjustments
Enum
Name(isa_ext_fpu) Type(int)
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index 622df47916f..4033320d0e1 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -23,7 +23,6 @@ along with GCC; see the file COPYING3. If not see
#include "config.h"
#include "system.h"
#include "coretypes.h"
-#include "tm.h"
#include "diagnostic-core.h"
#include "loongarch-def.h"
@@ -32,19 +31,6 @@ along with GCC; see the file COPYING3. If not see
#include "loongarch-cpucfg-map.h"
#include "loongarch-str.h"
-/* loongarch_isa_base_features defined here instead of loongarch-def.c
- because we need to use options.h. Pay attention on the order of elements
- in the initializer becaue ISO C++ does not allow C99 designated
- initializers! */
-
-#define ISA_BASE_LA64V110_FEATURES \
- (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA \
- | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS)
-
-int64_t loongarch_isa_base_features[N_ISA_BASE_TYPES] = {
- /* [ISA_BASE_LA64V100] = */ 0,
- /* [ISA_BASE_LA64V110] = */ ISA_BASE_LA64V110_FEATURES,
-};
/* Native CPU detection with "cpucfg" */
static uint32_t cpucfg_cache[N_CPUCFG_WORDS] = { 0 };
@@ -235,18 +221,20 @@ fill_native_cpu_config (struct loongarch_target *tgt)
/* Use the native value anyways. */
preset.simd = tmp;
+
+ int64_t hw_isa_evolution = 0;
+
/* Features added during ISA evolution. */
for (const auto &entry: cpucfg_map)
if (cpucfg_cache[entry.cpucfg_word] & entry.cpucfg_bit)
- preset.evolution |= entry.isa_evolution_bit;
+ hw_isa_evolution |= entry.isa_evolution_bit;
if (native_cpu_type != CPU_NATIVE)
{
/* Check if the local CPU really supports the features of the base
ISA of probed native_cpu_type. If any feature is not detected,
either GCC or the hardware is buggy. */
- auto base_isa_feature = loongarch_isa_base_features[preset.base];
- if ((preset.evolution & base_isa_feature) != base_isa_feature)
+ if ((preset.evolution & hw_isa_evolution) != hw_isa_evolution)
warning (0,
"detected base architecture %qs, but some of its "
"features are not detected; the detected base "
@@ -254,6 +242,7 @@ fill_native_cpu_config (struct loongarch_target *tgt)
"features will be enabled",
loongarch_isa_base_strings[preset.base]);
}
+ preset.evolution = hw_isa_evolution;
}
if (tune_native_p)
diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc
index 6990c86c2c4..bc6997e45b5 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -18,6 +18,11 @@ You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+
#include "loongarch-def.h"
#include "loongarch-str.h"
@@ -51,9 +56,11 @@ array_arch<loongarch_isa> loongarch_cpu_default_isa =
.simd_ (ISA_EXT_SIMD_LASX))
.set (CPU_LA664,
loongarch_isa ()
- .base_ (ISA_BASE_LA64V110)
+ .base_ (ISA_BASE_LA64V100)
.fpu_ (ISA_EXT_FPU64)
- .simd_ (ISA_EXT_SIMD_LASX));
+ .simd_ (ISA_EXT_SIMD_LASX)
+ .evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA
+ | OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS));
static inline loongarch_cache la464_cache ()
{
@@ -136,8 +143,7 @@ array_tune<int> loongarch_cpu_multipass_dfa_lookahead = array_tune<int> ()
array<const char *, N_ISA_BASE_TYPES> loongarch_isa_base_strings =
array<const char *, N_ISA_BASE_TYPES> ()
- .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100)
- .set (ISA_BASE_LA64V110, STR_ISA_BASE_LA64V110);
+ .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100);
array<const char *, N_ISA_EXT_TYPES> loongarch_isa_ext_strings =
array<const char *, N_ISA_EXT_TYPES> ()
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 68a9a461e54..a2c86df5bd9 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -56,19 +56,11 @@ along with GCC; see the file COPYING3. If not see
/* enum isa_base */
/* LoongArch V1.00. */
-#define ISA_BASE_LA64V100 0
-/* LoongArch V1.10. */
-#define ISA_BASE_LA64V110 1
-#define N_ISA_BASE_TYPES 2
+#define ISA_BASE_LA64V100 0
+#define N_ISA_BASE_TYPES 1
extern loongarch_def_array<const char *, N_ISA_BASE_TYPES>
loongarch_isa_base_strings;
-#if !defined(IN_LIBGCC2) && !defined(IN_TARGET_LIBS) && !defined(IN_RTS)
-/* Unlike other arrays, this is defined in loongarch-cpu.cc. The problem is
- we cannot use the C++ header options.h in loongarch-def.c. */
-extern int64_t loongarch_isa_base_features[];
-#endif
-
/* enum isa_ext_* */
#define ISA_EXT_NONE 0
#define ISA_EXT_FPU32 1
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index 7b63ef57a2a..8689f2dab05 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -285,9 +285,6 @@ config_target_isa:
/* Get default ISA from "-march" or its default value. */
t.isa = loongarch_cpu_default_isa[t.cpu_arch];
- if (t.cpu_arch != CPU_NATIVE)
- t.isa.evolution |= loongarch_isa_base_features[t.isa.base];
-
/* Apply incremental changes. */
/* "-march=native" overrides the default FPU type. */
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index e1ec702335d..651c1c18ca8 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -77,8 +77,7 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
#define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64)
#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D)
-#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100 \
- || la_target.isa.base == ISA_BASE_LA64V110)
+#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100)
#define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \
|| la_target.abi.base == ABI_BASE_LP64F \
|| la_target.abi.base == ABI_BASE_LP64S)
@@ -90,7 +89,6 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
/* TARGET_ macros for use in *.md template conditionals */
#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464)
#define TARGET_uARCH_LA664 (la_target.cpu_tune == CPU_LA664)
-#define ISA_BASE_IS_LA64V110 (la_target.isa.base == ISA_BASE_LA64V110)
/* Note: optimize_size may vary across functions,
while -m[no]-memcpy imposes a global constraint. */
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 0384493765c..7c78d1443d5 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -33,7 +33,6 @@ along with GCC; see the file COPYING3. If not see
#define STR_CPU_LA664 "la664"
#define STR_ISA_BASE_LA64V100 "la64"
-#define STR_ISA_BASE_LA64V110 "la64v1.1"
#define OPTSTR_ISA_EXT_FPU "fpu"
#define STR_NONE "none"
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index 4d36e3ec4de..41e6424e861 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -40,9 +40,6 @@ Basic ISAs of LoongArch:
EnumValue
Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100)
-EnumValue
-Enum(isa_base) String(la64v1.1) Value(ISA_BASE_LA64V110)
-
;; ISA extensions / adjustments
Enum
Name(isa_ext_fpu) Type(int)
--
2.31.1
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