[gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for x86_64 backend

[gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for x86_64 backend

[Haochen Jiang]

Hi all,

This patch will mention the following changes in wwwdocs for x86_64 backend:

  - AVX10.1 support
  - APX EGPR, PUSH2POP2, PPX and NDD support
  - Xeon Phi ISAs deprecated

Also I adjust the words in x86_64 part for GCC 13. Ok for gcc-wwwdocs?

Thx,
Haochen

Mention AVX10.1 support, APX support and Xeon Phi deprecate in GCC 14.
Also adjust documentation in GCC 13.
---
 htdocs/gcc-13/changes.html | 14 ++++++++------
 htdocs/gcc-14/changes.html | 18 ++++++++++++++++++
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 8ef3d639..e29ca72e 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -579,13 +579,13 @@ You may also want to check out our
   </li>
   <li>GCC now supports the Intel CPU named Sierra Forest through
     <code>-march=sierraforest</code>.
-    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-    ENQCMD and UINTR ISA extensions.
+    Based on ISA extensions enabled on Alder Lake, the switch further enables
+    the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, ENQCMD and UINTR
+    ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Grand Ridge through
     <code>-march=grandridge</code>.
-    The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
-    ENQCMD, UINTR and RAO-INT ISA extensions.
+    Based on Sierra Forest, the switch further enables RAO-INT ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Emerald Rapids through
     <code>-march=emeraldrapids</code>.
@@ -593,11 +593,13 @@ You may also want to check out our
   </li>
   <li>GCC now supports the Intel CPU named Granite Rapids through
     <code>-march=graniterapids</code>.
-    The switch enables the AMX-FP16, PREFETCHI ISA extensions.
+    Based on Sapphire Rapids, the switch further enables the AMX-FP16 and
+    PREFETCHI ISA extensions.
   </li>
   <li>GCC now supports the Intel CPU named Granite Rapids D through
     <code>-march=graniterapids-d</code>.
-    The switch enables the AMX-FP16, PREFETCHI and AMX-COMPLEX ISA extensions.
+    Based on Granite Rapids, the switch further enables the AMX-COMPLEX ISA
+    extensions.
   </li>
   <li>GCC now supports AMD CPUs based on the <code>znver4</code> core
     via <code>-march=znver4</code>.  The switch makes GCC consider
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 6d7138f8..8590f735 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -296,6 +296,16 @@ a work-in-progress.</p>
       USER_MSR intrinsics are available via the <code>-muser_msr</code>
       compiler switch.
   </li>
+  <li>New ISA extension support for Intel AVX10.1 was added.
+      AVX10.1 intrinsics are available via the <code>-mavx10.1</code> or
+      <code>-mavx10.1-256</code> compiler switch with 256 bit vector size
+      support. 512 bit vector size support for AVX10.1 intrinsics are
+      available via the <code>-mavx10.1-512</code> compiler switch.
+  </li>
+  <li>Part of new feature support for Intel APX was added, including EGPR,
+      PUSH2POP2, PPX and NDD. APX features are available via the
+      <code>-mapxf</code> compiler switch.
+  </li>
   <li>GCC now supports the Intel CPU named Clearwater Forest through
     <code>-march=clearwaterforest</code>.
     Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
@@ -321,6 +331,14 @@ a work-in-progress.</p>
     Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
     extensions.
   </li>
+  <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked
+    as deprecated. GCC will emit a warning when using the
+    <code>-mavx5124fmaps</code>, <code>-mavx5124vnniw</code>,
+    <code>-mavx512er</code>, <code>-mavx512pf</code>,
+    <code>-mprefetchwt1</code>, <code>-march=knl</code>,
+    <code>-march=knm</code>, <code>-mtune=knl</code> and <code>-mtune=knm</code>
+    compiler switch. The support will be removed in GCC 15.
+  </li>
 </ul>
 
 <!-- <h3 id="mips">MIPS</h3> -->
-- 
2.31.1

Re: [gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for x86_64 backend

[Gerald Pfeifer]

On Fri, 8 Dec 2023, Haochen Jiang wrote:
> +++ b/htdocs/gcc-13/changes.html

> +    Based on ISA extensions enabled on Alder Lake, the switch further enables
> +    the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, ENQCMD and UINTR
> +    ISA extensions.

Personally I would alphabetically sort all the options, like you have 
mostly done already. Just AVX-VNNI-INT8 and AVX-NE-CONVERT are not.

(Maybe you have a reason, and in any case this should not block this 
patch.)


> +++ b/htdocs/gcc-14/changes.html
> +  <li>New ISA extension support for Intel AVX10.1 was added.
> +      AVX10.1 intrinsics are available via the <code>-mavx10.1</code> or
> +      <code>-mavx10.1-256</code> compiler switch with 256 bit vector size
> +      support. 512 bit vector size support for AVX10.1 intrinsics are

We usually write 256-bit and 512-bit as adjectives, cf. 
gcc.gnu.org/codingconventions.html .

> +  <li>Part of new feature support for Intel APX was added, including EGPR,
> +      PUSH2POP2, PPX and NDD. 

Alphabetically?

>     APX features are available via the
> +      <code>-mapxf</code> compiler switch.

Could we say "APX is enabled via..." or "APX support is available via..."?

> +  <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are marked
> +    as deprecated. GCC will emit a warning when using the
> +    <code>-mavx5124fmaps</code>, <code>-mavx5124vnniw</code>,
> +    <code>-mavx512er</code>, <code>-mavx512pf</code>,
> +    <code>-mprefetchwt1</code>, <code>-march=knl</code>,
> +    <code>-march=knm</code>, <code>-mtune=knl</code> and <code>-mtune=knm</code>
> +    compiler switch. The support will be removed in GCC 15.
> +  </li>

I believe "or" instead of "and" will be clearer.

And "compiler switches" (plural).

And just "Support" in the last sentence.


Thanks for submitting these! No need for further review before committing
(a minor variation).

Gerald

RE: [gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for x86_64 backend

[Jiang, Haochen]

> -----Original Message-----
> From: Gerald Pfeifer <gerald@pfeifer.com>
> Sent: Wednesday, December 13, 2023 2:20 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: gcc-patches@gcc.gnu.org; Liu, Hongtao <hongtao.liu@intel.com>;
> ubizjak@gmail.com
> Subject: Re: [gcc-wwwdocs PATCH] gcc-13/14: Mention recent update for
> x86_64 backend
> 
> On Fri, 8 Dec 2023, Haochen Jiang wrote:
> > +++ b/htdocs/gcc-13/changes.html
> 
> > +    Based on ISA extensions enabled on Alder Lake, the switch further
> enables
> > +    the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
> ENQCMD and UINTR
> > +    ISA extensions.
> 
> Personally I would alphabetically sort all the options, like you have mostly
> done already. Just AVX-VNNI-INT8 and AVX-NE-CONVERT are not.
> 
> (Maybe you have a reason, and in any case this should not block this
> patch.)
> 
> 
> > +++ b/htdocs/gcc-14/changes.html
> > +  <li>New ISA extension support for Intel AVX10.1 was added.
> > +      AVX10.1 intrinsics are available via the <code>-mavx10.1</code> or
> > +      <code>-mavx10.1-256</code> compiler switch with 256 bit vector size
> > +      support. 512 bit vector size support for AVX10.1 intrinsics are
> 
> We usually write 256-bit and 512-bit as adjectives, cf.
> gcc.gnu.org/codingconventions.html .
> 
> > +  <li>Part of new feature support for Intel APX was added, including EGPR,
> > +      PUSH2POP2, PPX and NDD.
> 
> Alphabetically?
> 
> >     APX features are available via the
> > +      <code>-mapxf</code> compiler switch.
> 
> Could we say "APX is enabled via..." or "APX support is available via..."?
> 
> > +  <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) are
> marked
> > +    as deprecated. GCC will emit a warning when using the
> > +    <code>-mavx5124fmaps</code>, <code>-mavx5124vnniw</code>,
> > +    <code>-mavx512er</code>, <code>-mavx512pf</code>,
> > +    <code>-mprefetchwt1</code>, <code>-march=knl</code>,
> > +    <code>-march=knm</code>, <code>-mtune=knl</code> and <code>-
> mtune=knm</code>
> > +    compiler switch. The support will be removed in GCC 15.
> > +  </li>
> 
> I believe "or" instead of "and" will be clearer.
> 
> And "compiler switches" (plural).
> 
> And just "Support" in the last sentence.
> 
> 
> Thanks for submitting these! No need for further review before committing
> (a minor variation).

Thanks for your review. I will fix them and also other alphabetic issue in GCC13/14
doc. Since there will be a Grand Ridge ISA change coming soon in GCC13 (I have
not sent out the patch but will happen within one week), I will commit the whole
patch after that landed.

Thx,
Haochen

> 
> Gerald