* [Committed] RISC-V: Refine some codes of expand_const_vector [NFC]
@ 2023-12-19 10:56 Juzhe-Zhong
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From: Juzhe-Zhong @ 2023-12-19 10:56 UTC (permalink / raw)
To: gcc-patches; +Cc: Juzhe-Zhong
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_const_vector): Use builder.inner_mode ().
---
gcc/config/riscv/riscv-v.cc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index d1eb7a0a9a5..486f5deb296 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1380,15 +1380,15 @@ expand_const_vector (rtx target, rtx src)
rtx base1 = builder.elt (1);
rtx base2 = builder.elt (2);
- scalar_mode elem_mode = GET_MODE_INNER (mode);
- rtx step = simplify_binary_operation (MINUS, elem_mode, base2, base1);
+ rtx step = simplify_binary_operation (MINUS, builder.inner_mode (),
+ base2, base1);
/* Step 1 - { base1, base1 + step, base1 + step * 2, ... } */
rtx tmp = gen_reg_rtx (mode);
expand_vec_series (tmp, base1, step);
/* Step 2 - { base0, base1, base1 + step, base1 + step * 2, ... } */
if (!rtx_equal_p (base0, const0_rtx))
- base0 = force_reg (elem_mode, base0);
+ base0 = force_reg (builder.inner_mode (), base0);
insn_code icode = optab_handler (vec_shl_insert_optab, mode);
gcc_assert (icode != CODE_FOR_nothing);
--
2.36.3
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2023-12-19 10:56 [Committed] RISC-V: Refine some codes of expand_const_vector [NFC] Juzhe-Zhong
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