* [PATCH v2 0/4] Adjust option handling code
@ 2024-01-08 1:14 Yang Yujie
2024-01-08 1:14 ` [PATCH v2 1/4] LoongArch: Handle ISA evolution switches along with other options Yang Yujie
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Yang Yujie @ 2024-01-08 1:14 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, chenglulu, xuchenghua, Yang Yujie
This patchset performs some code cleanup, and is bootstrapped and regtested
on loongarch64-linux-gnu.
Changes from v1 -> v2:
* Replaced all TARGET_<evolution> macros from .opt.
* Fixed definition of ISA_HAS_LAMCAS.
Yang Yujie (4):
LoongArch: Handle ISA evolution switches along with other options
LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64
LoongArch: Use enums for constants
LoongArch: Simplify -mexplicit-reloc definitions
gcc/config/loongarch/genopts/genstr.sh | 2 +-
.../loongarch/genopts/loongarch-strings | 8 +-
gcc/config/loongarch/genopts/loongarch.opt.in | 16 +--
gcc/config/loongarch/lasx.md | 4 +-
gcc/config/loongarch/loongarch-builtins.cc | 6 +-
gcc/config/loongarch/loongarch-c.cc | 2 +-
gcc/config/loongarch/loongarch-cpu.cc | 2 +-
gcc/config/loongarch/loongarch-def.cc | 14 +-
gcc/config/loongarch/loongarch-def.h | 120 +++++++++++-------
gcc/config/loongarch/loongarch-driver.cc | 5 +-
gcc/config/loongarch/loongarch-opts.cc | 27 +++-
gcc/config/loongarch/loongarch-opts.h | 26 +++-
gcc/config/loongarch/loongarch-str.h | 7 +-
gcc/config/loongarch/loongarch.cc | 36 ++----
gcc/config/loongarch/loongarch.md | 12 +-
gcc/config/loongarch/loongarch.opt | 20 +--
gcc/config/loongarch/lsx.md | 4 +-
gcc/config/loongarch/sync.md | 22 ++--
18 files changed, 180 insertions(+), 153 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/4] LoongArch: Handle ISA evolution switches along with other options
2024-01-08 1:14 [PATCH v2 0/4] Adjust option handling code Yang Yujie
@ 2024-01-08 1:14 ` Yang Yujie
2024-01-08 1:14 ` [PATCH v2 2/4] LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64 Yang Yujie
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Yang Yujie @ 2024-01-08 1:14 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, chenglulu, xuchenghua, Yang Yujie
gcc/ChangeLog:
* config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
variable with the common la_ prefix.
* config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
flags as saved using TargetVariable.
* config/loongarch/loongarch.opt: Same.
* config/loongarch/loongarch-def.h: Define evolution_set to
mark changes to the -march default.
* config/loongarch/loongarch-driver.cc: Same.
* config/loongarch/loongarch-opts.cc: Same.
* config/loongarch/loongarch-opts.h: Define and use ISA evolution
conditions around the la_target structure.
* config/loongarch/loongarch.cc: Same.
* config/loongarch/loongarch.md: Same.
* config/loongarch/loongarch-builtins.cc: Same.
* config/loongarch/loongarch-c.cc: Same.
* config/loongarch/lasx.md: Same.
* config/loongarch/lsx.md: Same.
* config/loongarch/sync.md: Same.
---
gcc/config/loongarch/genopts/genstr.sh | 2 +-
gcc/config/loongarch/genopts/loongarch.opt.in | 6 ++---
gcc/config/loongarch/lasx.md | 4 ++--
gcc/config/loongarch/loongarch-builtins.cc | 6 ++---
gcc/config/loongarch/loongarch-c.cc | 2 +-
gcc/config/loongarch/loongarch-def.h | 5 +++-
gcc/config/loongarch/loongarch-driver.cc | 5 ++--
gcc/config/loongarch/loongarch-opts.cc | 17 ++++++++++++-
gcc/config/loongarch/loongarch-opts.h | 24 +++++++++++++++----
gcc/config/loongarch/loongarch.cc | 24 ++++++++-----------
gcc/config/loongarch/loongarch.md | 12 +++++-----
gcc/config/loongarch/loongarch.opt | 16 ++++++-------
gcc/config/loongarch/lsx.md | 4 ++--
gcc/config/loongarch/sync.md | 22 ++++++++---------
14 files changed, 90 insertions(+), 59 deletions(-)
diff --git a/gcc/config/loongarch/genopts/genstr.sh b/gcc/config/loongarch/genopts/genstr.sh
index 5865b87d516..724c9aaedac 100755
--- a/gcc/config/loongarch/genopts/genstr.sh
+++ b/gcc/config/loongarch/genopts/genstr.sh
@@ -107,7 +107,7 @@ EOF
print("")
print("m"$3)
gsub(/-/, "_", $3)
- print("Target Mask(ISA_"toupper($3)") Var(isa_evolution)")
+ print("Target Mask(ISA_"toupper($3)") Var(la_isa_evolution)")
$1=""; $2=""; $3=""
sub(/^ */, "", $0)
print($0)
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index f2e7ea2ef2f..e643deacd21 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -259,6 +259,6 @@ default value is 4.
; Features added during ISA evolution. This concept is different from ISA
; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
; explanation. These features may be implemented and enumerated with
-; CPUCFG independantly, so we use bit flags to specify them.
-Variable
-HOST_WIDE_INT isa_evolution = 0
+; CPUCFG independently, so we use bit flags to specify them.
+TargetVariable
+HOST_WIDE_INT la_isa_evolution = 0
diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 027021b45d5..429c59504b9 100644
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -1539,7 +1539,7 @@ (define_insn "lasx_xvfrecipe_<flasxfmt>"
[(set (match_operand:FLASX 0 "register_operand" "=f")
(unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")]
UNSPEC_LASX_XVFRECIPE))]
- "ISA_HAS_LASX && TARGET_FRECIPE"
+ "ISA_HAS_LASX && ISA_HAS_FRECIPE"
"xvfrecipe.<flasxfmt>\t%u0,%u1"
[(set_attr "type" "simd_fdiv")
(set_attr "mode" "<MODE>")])
@@ -1572,7 +1572,7 @@ (define_insn "lasx_xvfrsqrte_<flasxfmt>"
[(set (match_operand:FLASX 0 "register_operand" "=f")
(unspec:FLASX [(match_operand:FLASX 1 "register_operand" "f")]
UNSPEC_LASX_XVFRSQRTE))]
- "ISA_HAS_LASX && TARGET_FRECIPE"
+ "ISA_HAS_LASX && ISA_HAS_FRECIPE"
"xvfrsqrte.<flasxfmt>\t%u0,%u1"
[(set_attr "type" "simd_fdiv")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc
index 45ec6aca030..efe7e5e5ebc 100644
--- a/gcc/config/loongarch/loongarch-builtins.cc
+++ b/gcc/config/loongarch/loongarch-builtins.cc
@@ -120,9 +120,9 @@ struct loongarch_builtin_description
AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
AVAIL_ALL (lsx, ISA_HAS_LSX)
AVAIL_ALL (lasx, ISA_HAS_LASX)
-AVAIL_ALL (frecipe, TARGET_FRECIPE && TARGET_HARD_FLOAT_ABI)
-AVAIL_ALL (lsx_frecipe, ISA_HAS_LSX && TARGET_FRECIPE)
-AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && TARGET_FRECIPE)
+AVAIL_ALL (frecipe, ISA_HAS_FRECIPE && TARGET_HARD_FLOAT_ABI)
+AVAIL_ALL (lsx_frecipe, ISA_HAS_LSX && ISA_HAS_FRECIPE)
+AVAIL_ALL (lasx_frecipe, ISA_HAS_LASX && ISA_HAS_FRECIPE)
/* Construct a loongarch_builtin_description from the given arguments.
diff --git a/gcc/config/loongarch/loongarch-c.cc b/gcc/config/loongarch/loongarch-c.cc
index 118b1512e1e..4d88c1729ff 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -102,7 +102,7 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
else
builtin_define ("__loongarch_frlen=0");
- if (TARGET_HARD_FLOAT && TARGET_FRECIPE)
+ if (TARGET_HARD_FLOAT && ISA_HAS_FRECIPE)
builtin_define ("__loongarch_frecipe");
if (ISA_HAS_LSX)
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 403b024812d..1fab4f4d315 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -132,8 +132,11 @@ struct loongarch_isa
Using int64_t instead of HOST_WIDE_INT for C compatibility. */
int64_t evolution;
+ int64_t evolution_set;
- loongarch_isa () : base (0), fpu (0), simd (0), evolution (0) {}
+ loongarch_isa () :
+ base (0), fpu (0), simd (0), evolution (0), evolution_set (0)
+ {}
loongarch_isa base_ (int _base) { base = _base; return *this; }
loongarch_isa fpu_ (int _fpu) { fpu = _fpu; return *this; }
loongarch_isa simd_ (int _simd) { simd = _simd; return *this; }
diff --git a/gcc/config/loongarch/loongarch-driver.cc b/gcc/config/loongarch/loongarch-driver.cc
index ef1db3104e7..62658f531ad 100644
--- a/gcc/config/loongarch/loongarch-driver.cc
+++ b/gcc/config/loongarch/loongarch-driver.cc
@@ -42,9 +42,10 @@ extern struct obstack opts_obstack;
const char*
la_driver_init (int argc ATTRIBUTE_UNUSED, const char **argv ATTRIBUTE_UNUSED)
{
- /* Initialize all fields of la_target to -1 */
+ /* Initialize all fields of la_target. */
loongarch_init_target (&la_target, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET,
- M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET);
+ M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET, M_OPT_UNSET,
+ 0, 0);
return "";
}
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index d28b4363c7b..9483060ab62 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -140,7 +140,9 @@ static int with_default_simd = 0;
void
loongarch_init_target (struct loongarch_target *target,
int cpu_arch, int cpu_tune, int fpu, int simd,
- int abi_base, int abi_ext, int cmodel)
+ int abi_base, int abi_ext, int cmodel,
+ HOST_WIDE_INT isa_evolution,
+ HOST_WIDE_INT isa_evolution_set)
{
if (!target)
return;
@@ -148,6 +150,8 @@ loongarch_init_target (struct loongarch_target *target,
target->cpu_tune = cpu_tune;
target->isa.fpu = fpu;
target->isa.simd = simd;
+ target->isa.evolution = isa_evolution;
+ target->isa.evolution_set = isa_evolution_set;
target->abi.base = abi_base;
target->abi.ext = abi_ext;
target->cmodel = cmodel;
@@ -184,6 +188,9 @@ loongarch_config_target (struct loongarch_target *target,
M_OPT_ABSENT (target->abi.base) ? 0 : 1,
};
+ int64_t isa_evolution = target->isa.evolution;
+ int64_t isa_evolution_set = target->isa.evolution_set;
+
/* 1. Target ABI */
if (constrained.abi_base)
t.abi.base = target->abi.base;
@@ -394,6 +401,13 @@ config_target_isa:
}
}
+ /* Apply the ISA evolution feature switches from the user. */
+ HOST_WIDE_INT isa_evolution_orig = t.isa.evolution;
+ t.isa.evolution &= ~(~isa_evolution & isa_evolution_set);
+ t.isa.evolution |= isa_evolution & isa_evolution_set;
+
+ /* evolution_set means "what's different from the -march default". */
+ t.isa.evolution_set = isa_evolution_orig ^ t.isa.evolution;
/* 4. ABI-ISA compatibility */
/* Note:
@@ -774,4 +788,5 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
/* status of -mfpu */
opts->x_la_opt_fpu = target->isa.fpu;
opts->x_la_opt_simd = target->isa.simd;
+ opts->x_la_isa_evolution = target->isa.evolution;
}
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index b28dcbfb791..aa0dd32f411 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -34,7 +34,9 @@ extern struct loongarch_target la_target;
void
loongarch_init_target (struct loongarch_target *target,
int cpu_arch, int cpu_tune, int fpu, int simd,
- int abi_base, int abi_ext, int cmodel);
+ int abi_base, int abi_ext, int cmodel,
+ HOST_WIDE_INT isa_evolutions,
+ HOST_WIDE_INT isa_evolutions_set);
/* Handler for "-m" option combinations,
@@ -82,9 +84,23 @@ struct loongarch_flags {
|| la_target.abi.base == ABI_BASE_LP64F \
|| la_target.abi.base == ABI_BASE_LP64S)
-#define ISA_HAS_LSX (la_target.isa.simd == ISA_EXT_SIMD_LSX \
- || la_target.isa.simd == ISA_EXT_SIMD_LASX)
-#define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX)
+#define ISA_HAS_LSX \
+ (la_target.isa.simd == ISA_EXT_SIMD_LSX \
+ || la_target.isa.simd == ISA_EXT_SIMD_LASX)
+
+#define ISA_HAS_LASX \
+ (la_target.isa.simd == ISA_EXT_SIMD_LASX)
+
+#define ISA_HAS_FRECIPE \
+ (la_target.isa.evolution & OPTION_MASK_ISA_FRECIPE)
+#define ISA_HAS_DIV32 \
+ (la_target.isa.evolution & OPTION_MASK_ISA_DIV32)
+#define ISA_HAS_LAM_BH \
+ (la_target.isa.evolution & OPTION_MASK_ISA_LAM_BH)
+#define ISA_HAS_LAMCAS \
+ (la_target.isa.evolution & OPTION_MASK_ISA_LAMCAS)
+#define ISA_HAS_LD_SEQ_SA \
+ (la_target.isa.evolution & OPTION_MASK_ISA_LD_SEQ_SA)
/* TARGET_ macros for use in *.md template conditionals */
#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464)
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 91e6bb3e95a..95517ec61da 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -3874,7 +3874,7 @@ loongarch_rtx_costs (rtx x, machine_mode mode, int outer_code,
else
{
*total = loongarch_cost->int_div_si;
- if (TARGET_64BIT && !TARGET_DIV32)
+ if (TARGET_64BIT && !ISA_HAS_DIV32)
*total += COSTS_N_INSNS (2);
}
@@ -6122,7 +6122,7 @@ loongarch_print_operand (FILE *file, rtx op, int letter)
if (loongarch_cas_failure_memorder_needs_acquire (
memmodel_from_int (INTVAL (op))))
fputs ("dbar\t0b10100", file);
- else if (!TARGET_LD_SEQ_SA)
+ else if (!ISA_HAS_LD_SEQ_SA)
fputs ("dbar\t0x700", file);
break;
@@ -7524,7 +7524,8 @@ loongarch_option_override_internal (struct gcc_options *opts,
loongarch_init_target (&la_target,
la_opt_cpu_arch, la_opt_cpu_tune, la_opt_fpu,
la_opt_simd, la_opt_abi_base, la_opt_abi_ext,
- la_opt_cmodel);
+ la_opt_cmodel, opts->x_la_isa_evolution,
+ opts_set->x_la_isa_evolution);
/* Handle target-specific options: compute defaults/conflicts etc. */
loongarch_config_target (&la_target, NULL, 0);
@@ -7565,11 +7566,6 @@ loongarch_option_override_internal (struct gcc_options *opts,
if (loongarch_branch_cost == 0)
loongarch_branch_cost = loongarch_cost->branch_cost;
- /* If the user hasn't disabled a feature added during ISA evolution,
- use the processor's default. */
- isa_evolution |= (la_target.isa.evolution &
- ~global_options_set.x_isa_evolution);
-
/* Enable sw prefetching at -O3 and higher. */
if (opts->x_flag_prefetch_loop_arrays < 0
&& (opts->x_optimize >= 3 || opts->x_flag_profile_use)
@@ -7700,7 +7696,7 @@ loongarch_option_override_internal (struct gcc_options *opts,
}
if (loongarch_recip)
recip_mask |= RECIP_MASK_ALL;
- if (!TARGET_FRECIPE)
+ if (!ISA_HAS_FRECIPE)
recip_mask = RECIP_MASK_NONE;
}
@@ -11743,11 +11739,11 @@ loongarch_asm_code_end (void)
loongarch_cpu_strings [la_target.cpu_tune]);
fprintf (asm_out_file, "%s Base ISA: %s\n", ASM_COMMENT_START,
loongarch_isa_base_strings [la_target.isa.base]);
- DUMP_FEATURE (TARGET_FRECIPE);
- DUMP_FEATURE (TARGET_DIV32);
- DUMP_FEATURE (TARGET_LAM_BH);
- DUMP_FEATURE (TARGET_LAMCAS);
- DUMP_FEATURE (TARGET_LD_SEQ_SA);
+ DUMP_FEATURE (ISA_HAS_FRECIPE);
+ DUMP_FEATURE (ISA_HAS_DIV32);
+ DUMP_FEATURE (ISA_HAS_LAM_BH);
+ DUMP_FEATURE (ISA_HAS_LAMCAS);
+ DUMP_FEATURE (ISA_HAS_LD_SEQ_SA);
}
fputs ("\n\n", asm_out_file);
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index d1f5b94f5d6..8510f24835b 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -425,7 +425,7 @@ (define_mode_iterator ST_ANY [QHWD ANYF])
;; A mode for anything legal as a input of a div or mod instruction.
(define_mode_iterator DIV [(DI "TARGET_64BIT")
- (SI "!TARGET_64BIT || TARGET_DIV32")])
+ (SI "!TARGET_64BIT || ISA_HAS_DIV32")])
;; In GPR templates, a string like "mul.<d>" will expand to "mul.w" in the
;; 32-bit version and "mul.d" in the 64-bit version.
@@ -941,7 +941,7 @@ (define_insn "loongarch_frecipe_<fmt>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
UNSPEC_RECIPE))]
- "TARGET_FRECIPE"
+ "ISA_HAS_FRECIPE"
"frecipe.<fmt>\t%0,%1"
[(set_attr "type" "frecipe")
(set_attr "mode" "<UNITMODE>")
@@ -954,7 +954,7 @@ (define_expand "<optab><mode>3"
(match_operand:GPR 2 "register_operand")))]
""
{
- if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !TARGET_DIV32)
+ if (GET_MODE (operands[0]) == SImode && TARGET_64BIT && !ISA_HAS_DIV32)
{
rtx reg1 = gen_reg_rtx (DImode);
rtx reg2 = gen_reg_rtx (DImode);
@@ -994,7 +994,7 @@ (define_insn "<optab>si3_extended"
(sign_extend
(any_div:SI (match_operand:SI 1 "register_operand" "r,r,0")
(match_operand:SI 2 "register_operand" "r,r,r"))))]
- "TARGET_64BIT && TARGET_DIV32"
+ "TARGET_64BIT && ISA_HAS_DIV32"
{
return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
}
@@ -1014,7 +1014,7 @@ (define_insn "<optab>di3_fake"
(any_div:DI (match_operand:DI 1 "register_operand" "r,r,0")
(match_operand:DI 2 "register_operand" "r,r,r")) 0)]
UNSPEC_FAKE_ANY_DIV)))]
- "TARGET_64BIT && !TARGET_DIV32"
+ "TARGET_64BIT && !ISA_HAS_DIV32"
{
return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
}
@@ -1197,7 +1197,7 @@ (define_insn "loongarch_frsqrte_<fmt>"
[(set (match_operand:ANYF 0 "register_operand" "=f")
(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
UNSPEC_RSQRTE))]
- "TARGET_FRECIPE"
+ "ISA_HAS_FRECIPE"
"frsqrte.<fmt>\t%0,%1"
[(set_attr "type" "frsqrte")
(set_attr "mode" "<UNITMODE>")])
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index b285a74acea..8b36f1a1495 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -267,26 +267,26 @@ default value is 4.
; Features added during ISA evolution. This concept is different from ISA
; extension, read Section 1.5 of LoongArch v1.10 Volume 1 for the
; explanation. These features may be implemented and enumerated with
-; CPUCFG independantly, so we use bit flags to specify them.
-Variable
-HOST_WIDE_INT isa_evolution = 0
+; CPUCFG independently, so we use bit flags to specify them.
+TargetVariable
+HOST_WIDE_INT la_isa_evolution = 0
mfrecipe
-Target Mask(ISA_FRECIPE) Var(isa_evolution)
+Target Mask(ISA_FRECIPE) Var(la_isa_evolution)
Support frecipe.{s/d} and frsqrte.{s/d} instructions.
mdiv32
-Target Mask(ISA_DIV32) Var(isa_evolution)
+Target Mask(ISA_DIV32) Var(la_isa_evolution)
Support div.w[u] and mod.w[u] instructions with inputs not sign-extended.
mlam-bh
-Target Mask(ISA_LAM_BH) Var(isa_evolution)
+Target Mask(ISA_LAM_BH) Var(la_isa_evolution)
Support am{swap/add}[_db].{b/h} instructions.
mlamcas
-Target Mask(ISA_LAMCAS) Var(isa_evolution)
+Target Mask(ISA_LAMCAS) Var(la_isa_evolution)
Support amcas[_db].{b/h/w/d} instructions.
mld-seq-sa
-Target Mask(ISA_LD_SEQ_SA) Var(isa_evolution)
+Target Mask(ISA_LD_SEQ_SA) Var(la_isa_evolution)
Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 76d33a3b88a..a1632accdd9 100644
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -1505,7 +1505,7 @@ (define_insn "lsx_vfrecipe_<flsxfmt>"
[(set (match_operand:FLSX 0 "register_operand" "=f")
(unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")]
UNSPEC_LSX_VFRECIPE))]
- "ISA_HAS_LSX && TARGET_FRECIPE"
+ "ISA_HAS_LSX && ISA_HAS_FRECIPE"
"vfrecipe.<flsxfmt>\t%w0,%w1"
[(set_attr "type" "simd_fdiv")
(set_attr "mode" "<MODE>")])
@@ -1538,7 +1538,7 @@ (define_insn "lsx_vfrsqrte_<flsxfmt>"
[(set (match_operand:FLSX 0 "register_operand" "=f")
(unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")]
UNSPEC_LSX_VFRSQRTE))]
- "ISA_HAS_LSX && TARGET_FRECIPE"
+ "ISA_HAS_LSX && ISA_HAS_FRECIPE"
"vfrsqrte.<flsxfmt>\t%w0,%w1"
[(set_attr "type" "simd_fdiv")
(set_attr "mode" "<MODE>")])
diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md
index 71954f95f59..8f35a5b48d2 100644
--- a/gcc/config/loongarch/sync.md
+++ b/gcc/config/loongarch/sync.md
@@ -124,9 +124,9 @@ (define_insn "atomic_load<mode>"
return "ld.<size>\t%0,%1\\n\\t"
"dbar\t0x14";
case MEMMODEL_RELAXED:
- return TARGET_LD_SEQ_SA ? "ld.<size>\t%0,%1"
- : "ld.<size>\t%0,%1\\n\\t"
- "dbar\t0x700";
+ return ISA_HAS_LD_SEQ_SA ? "ld.<size>\t%0,%1"
+ : "ld.<size>\t%0,%1\\n\\t"
+ "dbar\t0x700";
default:
/* The valid memory order variants are __ATOMIC_RELAXED, __ATOMIC_SEQ_CST,
@@ -193,7 +193,7 @@ (define_insn "atomic_add<mode>"
(match_operand:SHORT 1 "reg_or_0_operand" "rJ"))
(match_operand:SI 2 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
- "TARGET_LAM_BH"
+ "ISA_HAS_LAM_BH"
"amadd%A2.<amo>\t$zero,%z1,%0"
[(set (attr "length") (const_int 4))])
@@ -230,7 +230,7 @@ (define_insn "atomic_exchange<mode>_short"
UNSPEC_SYNC_EXCHANGE))
(set (match_dup 1)
(match_operand:SHORT 2 "register_operand" "r"))]
- "TARGET_LAM_BH"
+ "ISA_HAS_LAM_BH"
"amswap%A3.<amo>\t%0,%z2,%1"
[(set (attr "length") (const_int 4))])
@@ -266,7 +266,7 @@ (define_insn "atomic_cas_value_strong<mode>_amcas"
(match_operand:QHWD 3 "reg_or_0_operand" "rJ")
(match_operand:SI 4 "const_int_operand")] ;; mod_s
UNSPEC_COMPARE_AND_SWAP))]
- "TARGET_LAMCAS"
+ "ISA_HAS_LAMCAS"
"ori\t%0,%z2,0\n\tamcas%A4.<amo>\t%0,%z3,%1"
[(set (attr "length") (const_int 8))])
@@ -296,7 +296,7 @@ (define_expand "atomic_compare_and_swap<mode>"
operands[6] = mod_s;
- if (TARGET_LAMCAS)
+ if (ISA_HAS_LAMCAS)
emit_insn (gen_atomic_cas_value_strong<mode>_amcas (operands[1], operands[2],
operands[3], operands[4],
operands[6]));
@@ -422,7 +422,7 @@ (define_expand "atomic_compare_and_swap<mode>"
operands[6] = mod_s;
- if (TARGET_LAMCAS)
+ if (ISA_HAS_LAMCAS)
emit_insn (gen_atomic_cas_value_strong<mode>_amcas (operands[1], operands[2],
operands[3], operands[4],
operands[6]));
@@ -642,7 +642,7 @@ (define_expand "atomic_exchange<mode>"
(match_operand:SHORT 2 "register_operand"))]
""
{
- if (TARGET_LAM_BH)
+ if (ISA_HAS_LAM_BH)
emit_insn (gen_atomic_exchange<mode>_short (operands[0], operands[1], operands[2], operands[3]));
else
{
@@ -663,7 +663,7 @@ (define_insn "atomic_fetch_add<mode>_short"
(match_operand:SHORT 2 "reg_or_0_operand" "rJ"))
(match_operand:SI 3 "const_int_operand")] ;; model
UNSPEC_SYNC_OLD_OP))]
- "TARGET_LAM_BH"
+ "ISA_HAS_LAM_BH"
"amadd%A3.<amo>\t%0,%z2,%1"
[(set (attr "length") (const_int 4))])
@@ -678,7 +678,7 @@ (define_expand "atomic_fetch_add<mode>"
UNSPEC_SYNC_OLD_OP))]
""
{
- if (TARGET_LAM_BH)
+ if (ISA_HAS_LAM_BH)
emit_insn (gen_atomic_fetch_add<mode>_short (operands[0], operands[1],
operands[2], operands[3]));
else
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64
2024-01-08 1:14 [PATCH v2 0/4] Adjust option handling code Yang Yujie
2024-01-08 1:14 ` [PATCH v2 1/4] LoongArch: Handle ISA evolution switches along with other options Yang Yujie
@ 2024-01-08 1:14 ` Yang Yujie
2024-01-08 1:14 ` [PATCH v2 3/4] LoongArch: Use enums for constants Yang Yujie
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Yang Yujie @ 2024-01-08 1:14 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, chenglulu, xuchenghua, Yang Yujie
LoongArch ISA manual v1.10 suggests that software should not depend on
the ISA version number for marking processor features. The ISA version
number is now defined as a collective name of individual ISA evolutions.
Since there is a independent ISA evolution mask now, we can drop the
version information from the base ISA.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Rename.
* config/loongarch/genopts/loongarch.opt.in: Same.
* config/loongarch/loongarch-cpu.cc: Same.
* config/loongarch/loongarch-def.cc: Same.
* config/loongarch/loongarch-def.h: Same.
* config/loongarch/loongarch-opts.cc: Same.
* config/loongarch/loongarch-opts.h: Same.
* config/loongarch/loongarch-str.h: Same.
* config/loongarch/loongarch.opt: Same.
---
gcc/config/loongarch/genopts/loongarch-strings | 2 +-
gcc/config/loongarch/genopts/loongarch.opt.in | 2 +-
gcc/config/loongarch/loongarch-cpu.cc | 2 +-
gcc/config/loongarch/loongarch-def.cc | 14 +++++++-------
gcc/config/loongarch/loongarch-def.h | 6 +++---
gcc/config/loongarch/loongarch-opts.cc | 10 +++++-----
gcc/config/loongarch/loongarch-opts.h | 2 +-
gcc/config/loongarch/loongarch-str.h | 2 +-
gcc/config/loongarch/loongarch.opt | 2 +-
9 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index f40b014f017..ba47be31227 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -29,7 +29,7 @@ STR_CPU_LA464 la464
STR_CPU_LA664 la664
# Base architecture
-STR_ISA_BASE_LA64V100 la64
+STR_ISA_BASE_LA64 la64
# -mfpu
OPTSTR_ISA_EXT_FPU fpu
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index e643deacd21..38ac347c660 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -33,7 +33,7 @@ Name(isa_base) Type(int)
Basic ISAs of LoongArch:
EnumValue
-Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100)
+Enum(isa_base) String(@@STR_ISA_BASE_LA64@@) Value(ISA_BASE_LA64)
;; ISA extensions / adjustments
Enum
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index e1771fc0b4f..97ac5fed9d8 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -133,7 +133,7 @@ fill_native_cpu_config (struct loongarch_target *tgt)
switch (cpucfg_cache[1] & 0x3)
{
case 0x02:
- tmp = ISA_BASE_LA64V100;
+ tmp = ISA_BASE_LA64;
break;
default:
diff --git a/gcc/config/loongarch/loongarch-def.cc b/gcc/config/loongarch/loongarch-def.cc
index 48d28315064..e8c129ce643 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -48,16 +48,16 @@ array_arch<loongarch_isa> loongarch_cpu_default_isa =
array_arch<loongarch_isa> ()
.set (CPU_LOONGARCH64,
loongarch_isa ()
- .base_ (ISA_BASE_LA64V100)
+ .base_ (ISA_BASE_LA64)
.fpu_ (ISA_EXT_FPU64))
.set (CPU_LA464,
loongarch_isa ()
- .base_ (ISA_BASE_LA64V100)
+ .base_ (ISA_BASE_LA64)
.fpu_ (ISA_EXT_FPU64)
.simd_ (ISA_EXT_SIMD_LASX))
.set (CPU_LA664,
loongarch_isa ()
- .base_ (ISA_BASE_LA64V100)
+ .base_ (ISA_BASE_LA64)
.fpu_ (ISA_EXT_FPU64)
.simd_ (ISA_EXT_SIMD_LASX)
.evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA
@@ -153,7 +153,7 @@ array_tune<int> loongarch_cpu_multipass_dfa_lookahead = array_tune<int> ()
array<const char *, N_ISA_BASE_TYPES> loongarch_isa_base_strings =
array<const char *, N_ISA_BASE_TYPES> ()
- .set (ISA_BASE_LA64V100, STR_ISA_BASE_LA64V100);
+ .set (ISA_BASE_LA64, STR_ISA_BASE_LA64);
array<const char *, N_ISA_EXT_TYPES> loongarch_isa_ext_strings =
array<const char *, N_ISA_EXT_TYPES> ()
@@ -189,15 +189,15 @@ array<array<loongarch_isa, N_ABI_EXT_TYPES>, N_ABI_BASE_TYPES>
array<loongarch_isa, N_ABI_EXT_TYPES> ()
.set (ABI_EXT_BASE,
loongarch_isa ()
- .base_ (ISA_BASE_LA64V100)
+ .base_ (ISA_BASE_LA64)
.fpu_ (ISA_EXT_FPU64)))
.set (ABI_BASE_LP64F,
array<loongarch_isa, N_ABI_EXT_TYPES> ()
.set (ABI_EXT_BASE,
loongarch_isa ()
- .base_ (ISA_BASE_LA64V100)
+ .base_ (ISA_BASE_LA64)
.fpu_ (ISA_EXT_FPU32)))
.set (ABI_BASE_LP64S,
array<loongarch_isa, N_ABI_EXT_TYPES> ()
.set (ABI_EXT_BASE,
- loongarch_isa ().base_ (ISA_BASE_LA64V100)));
+ loongarch_isa ().base_ (ISA_BASE_LA64)));
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 1fab4f4d315..f8cb3adf509 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -55,9 +55,9 @@ along with GCC; see the file COPYING3. If not see
/* enum isa_base */
-/* LoongArch V1.00. */
-#define ISA_BASE_LA64V100 0
-#define N_ISA_BASE_TYPES 1
+/* LoongArch64 */
+#define ISA_BASE_LA64 0
+#define N_ISA_BASE_TYPES 1
extern loongarch_def_array<const char *, N_ISA_BASE_TYPES>
loongarch_isa_base_strings;
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index 9483060ab62..7eb1f2d4f2e 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -567,17 +567,17 @@ isa_default_abi (const struct loongarch_isa *isa)
switch (isa->fpu)
{
case ISA_EXT_FPU64:
- if (isa->base >= ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64)
abi.base = ABI_BASE_LP64D;
break;
case ISA_EXT_FPU32:
- if (isa->base >= ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64)
abi.base = ABI_BASE_LP64F;
break;
case ISA_EXT_NONE:
- if (isa->base >= ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64)
abi.base = ABI_BASE_LP64S;
break;
@@ -596,8 +596,8 @@ isa_base_compat_p (const struct loongarch_isa *set1,
{
switch (set2->base)
{
- case ISA_BASE_LA64V100:
- return (set1->base >= ISA_BASE_LA64V100);
+ case ISA_BASE_LA64:
+ return (set1->base >= ISA_BASE_LA64);
default:
gcc_unreachable ();
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index aa0dd32f411..586e67e65ee 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -79,7 +79,7 @@ struct loongarch_flags {
#define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64)
#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D)
-#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100)
+#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64)
#define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \
|| la_target.abi.base == ABI_BASE_LP64F \
|| la_target.abi.base == ABI_BASE_LP64S)
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 2221c57f78e..0a6a36c5783 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -32,7 +32,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_CPU_LA464 "la464"
#define STR_CPU_LA664 "la664"
-#define STR_ISA_BASE_LA64V100 "la64"
+#define STR_ISA_BASE_LA64 "la64"
#define OPTSTR_ISA_EXT_FPU "fpu"
#define STR_NONE "none"
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index 8b36f1a1495..76b42d51d09 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -41,7 +41,7 @@ Name(isa_base) Type(int)
Basic ISAs of LoongArch:
EnumValue
-Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100)
+Enum(isa_base) String(la64) Value(ISA_BASE_LA64)
;; ISA extensions / adjustments
Enum
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] LoongArch: Use enums for constants
2024-01-08 1:14 [PATCH v2 0/4] Adjust option handling code Yang Yujie
2024-01-08 1:14 ` [PATCH v2 1/4] LoongArch: Handle ISA evolution switches along with other options Yang Yujie
2024-01-08 1:14 ` [PATCH v2 2/4] LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64 Yang Yujie
@ 2024-01-08 1:14 ` Yang Yujie
2024-01-08 1:14 ` [PATCH v2 4/4] LoongArch: Simplify -mexplicit-reloc definitions Yang Yujie
2024-01-10 3:57 ` Re:[pushed] [PATCH v2 0/4] Adjust option handling code chenglulu
4 siblings, 0 replies; 6+ messages in thread
From: Yang Yujie @ 2024-01-08 1:14 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, chenglulu, xuchenghua, Yang Yujie
Target features constants from loongarch-def.h are currently defined as macros.
Switch to enums for better look in the debugger.
gcc/ChangeLog:
* config/loongarch/loongarch-def.h: Define constants with
enums instead of Macros.
---
gcc/config/loongarch/loongarch-def.h | 115 ++++++++++++++++-----------
1 file changed, 67 insertions(+), 48 deletions(-)
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index f8cb3adf509..a1237ecf1fd 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -23,12 +23,10 @@ along with GCC; see the file COPYING3. If not see
- ISA extensions (isa_ext),
- base ABI types (abi_base),
- ABI extension types (abi_ext).
-
- - code models (cmodel)
- - other command-line switches (switch)
+ - code models (cmodel)
These values are primarily used for implementing option handling
- logic in "loongarch.opt", "loongarch-driver.c" and "loongarch-opt.c".
+ logic in "loongarch.opt", "loongarch-driver.cc" and "loongarch-opt.cc".
As for the result of this option handling process, the following
scheme is adopted to represent the final configuration:
@@ -53,30 +51,40 @@ along with GCC; see the file COPYING3. If not see
#include "loongarch-def-array.h"
#include "loongarch-tune.h"
-/* enum isa_base */
-/* LoongArch64 */
-#define ISA_BASE_LA64 0
-#define N_ISA_BASE_TYPES 1
+/* ISA base */
+enum {
+ ISA_BASE_LA64 = 0, /* LoongArch64 */
+ N_ISA_BASE_TYPES = 1
+};
+
extern loongarch_def_array<const char *, N_ISA_BASE_TYPES>
loongarch_isa_base_strings;
-/* enum isa_ext_* */
-#define ISA_EXT_NONE 0
-#define ISA_EXT_FPU32 1
-#define ISA_EXT_FPU64 2
-#define N_ISA_EXT_FPU_TYPES 3
-#define ISA_EXT_SIMD_LSX 3
-#define ISA_EXT_SIMD_LASX 4
-#define N_ISA_EXT_TYPES 5
+
+/* ISA extensions */
+enum {
+ ISA_EXT_NONE = 0,
+ ISA_EXT_FPU32 = 1,
+ ISA_EXT_FPU64 = 2,
+ N_ISA_EXT_FPU_TYPES = 3,
+ ISA_EXT_SIMD_LSX = 3,
+ ISA_EXT_SIMD_LASX = 4,
+ N_ISA_EXT_TYPES = 5
+};
+
extern loongarch_def_array<const char *, N_ISA_EXT_TYPES>
loongarch_isa_ext_strings;
-/* enum abi_base */
-#define ABI_BASE_LP64D 0
-#define ABI_BASE_LP64F 1
-#define ABI_BASE_LP64S 2
-#define N_ABI_BASE_TYPES 3
+
+/* Base ABI */
+enum {
+ ABI_BASE_LP64D = 0,
+ ABI_BASE_LP64F = 1,
+ ABI_BASE_LP64S = 2,
+ N_ABI_BASE_TYPES = 3
+};
+
extern loongarch_def_array<const char *, N_ABI_BASE_TYPES>
loongarch_abi_base_strings;
@@ -90,28 +98,38 @@ extern loongarch_def_array<const char *, N_ABI_BASE_TYPES>
(abi_base == ABI_BASE_LP64S)
-/* enum abi_ext */
-#define ABI_EXT_BASE 0
-#define N_ABI_EXT_TYPES 1
+/* ABI Extension */
+enum {
+ ABI_EXT_BASE = 0,
+ N_ABI_EXT_TYPES = 1
+};
+
extern loongarch_def_array<const char *, N_ABI_EXT_TYPES>
loongarch_abi_ext_strings;
-/* enum cmodel */
-#define CMODEL_NORMAL 0
-#define CMODEL_TINY 1
-#define CMODEL_TINY_STATIC 2
-#define CMODEL_MEDIUM 3
-#define CMODEL_LARGE 4
-#define CMODEL_EXTREME 5
-#define N_CMODEL_TYPES 6
+
+/* Code Model */
+enum {
+ CMODEL_NORMAL = 0,
+ CMODEL_TINY = 1,
+ CMODEL_TINY_STATIC = 2,
+ CMODEL_MEDIUM = 3,
+ CMODEL_LARGE = 4,
+ CMODEL_EXTREME = 5,
+ N_CMODEL_TYPES = 6
+};
+
extern loongarch_def_array<const char *, N_CMODEL_TYPES>
loongarch_cmodel_strings;
-/* enum explicit_relocs */
-#define EXPLICIT_RELOCS_AUTO 0
-#define EXPLICIT_RELOCS_NONE 1
-#define EXPLICIT_RELOCS_ALWAYS 2
-#define N_EXPLICIT_RELOCS_TYPES 3
+
+/* Explicit Reloc Type */
+enum {
+ EXPLICIT_RELOCS_AUTO = 0,
+ EXPLICIT_RELOCS_NONE = 1,
+ EXPLICIT_RELOCS_ALWAYS = 2,
+ N_EXPLICIT_RELOCS_TYPES = 3
+};
/* The common default value for variables whose assignments
are triggered by command-line options. */
@@ -159,17 +177,18 @@ struct loongarch_target
int cmodel; /* CMODEL_ */
};
-/* CPU properties. */
-/* index */
-#define CPU_NATIVE 0
-#define CPU_ABI_DEFAULT 1
-#define CPU_LOONGARCH64 2
-#define CPU_LA464 3
-#define CPU_LA664 4
-#define N_ARCH_TYPES 5
-#define N_TUNE_TYPES 5
-
-/* parallel tables. */
+/* CPU model */
+enum {
+ CPU_NATIVE = 0,
+ CPU_ABI_DEFAULT = 1,
+ CPU_LOONGARCH64 = 2,
+ CPU_LA464 = 3,
+ CPU_LA664 = 4,
+ N_ARCH_TYPES = 5,
+ N_TUNE_TYPES = 5
+};
+
+/* CPU model properties */
extern loongarch_def_array<const char *, N_ARCH_TYPES>
loongarch_cpu_strings;
extern loongarch_def_array<loongarch_isa, N_ARCH_TYPES>
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] LoongArch: Simplify -mexplicit-reloc definitions
2024-01-08 1:14 [PATCH v2 0/4] Adjust option handling code Yang Yujie
` (2 preceding siblings ...)
2024-01-08 1:14 ` [PATCH v2 3/4] LoongArch: Use enums for constants Yang Yujie
@ 2024-01-08 1:14 ` Yang Yujie
2024-01-10 3:57 ` Re:[pushed] [PATCH v2 0/4] Adjust option handling code chenglulu
4 siblings, 0 replies; 6+ messages in thread
From: Yang Yujie @ 2024-01-08 1:14 UTC (permalink / raw)
To: gcc-patches; +Cc: xry111, chenglulu, xuchenghua, Yang Yujie
Since we do not need printing or manual parsing of this option,
(whether in the driver or for target attributes to be supported later)
it can be handled in the .opt file framework.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
argument string definitions.
* config/loongarch/loongarch-str.h: Same.
* config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
as aliases to -mexplicit-relocs={always,none}
* config/loongarch/genopts/loongarch.opt: Same.
* config/loongarch/loongarch.cc: Same.
---
gcc/config/loongarch/genopts/loongarch-strings | 6 ------
gcc/config/loongarch/genopts/loongarch.opt.in | 8 ++++----
gcc/config/loongarch/loongarch-str.h | 5 -----
gcc/config/loongarch/loongarch.cc | 12 ------------
gcc/config/loongarch/loongarch.opt | 2 +-
5 files changed, 5 insertions(+), 28 deletions(-)
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index ba47be31227..e434a89c9ee 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -64,9 +64,3 @@ STR_CMODEL_TS tiny-static
STR_CMODEL_MEDIUM medium
STR_CMODEL_LARGE large
STR_CMODEL_EXTREME extreme
-
-# -mexplicit-relocs
-OPTSTR_EXPLICIT_RELOCS explicit-relocs
-STR_EXPLICIT_RELOCS_AUTO auto
-STR_EXPLICIT_RELOCS_NONE none
-STR_EXPLICIT_RELOCS_ALWAYS always
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 38ac347c660..1dbd3ad1e3f 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -181,20 +181,20 @@ Name(explicit_relocs) Type(int)
The code model option names for -mexplicit-relocs:
EnumValue
-Enum(explicit_relocs) String(@@STR_EXPLICIT_RELOCS_AUTO@@) Value(EXPLICIT_RELOCS_AUTO)
+Enum(explicit_relocs) String(auto) Value(EXPLICIT_RELOCS_AUTO)
EnumValue
-Enum(explicit_relocs) String(@@STR_EXPLICIT_RELOCS_NONE@@) Value(EXPLICIT_RELOCS_NONE)
+Enum(explicit_relocs) String(none) Value(EXPLICIT_RELOCS_NONE)
EnumValue
-Enum(explicit_relocs) String(@@STR_EXPLICIT_RELOCS_ALWAYS@@) Value(EXPLICIT_RELOCS_ALWAYS)
+Enum(explicit_relocs) String(always) Value(EXPLICIT_RELOCS_ALWAYS)
mexplicit-relocs=
Target RejectNegative Joined Enum(explicit_relocs) Var(la_opt_explicit_relocs) Init(M_OPT_UNSET)
Use %reloc() assembly operators.
mexplicit-relocs
-Target Var(la_opt_explicit_relocs_backward) Init(M_OPT_UNSET)
+Target Alias(mexplicit-relocs=, always, none)
Use %reloc() assembly operators (for backward compatibility).
mrecip
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 0a6a36c5783..20da2b169ed 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -63,11 +63,6 @@ along with GCC; see the file COPYING3. If not see
#define STR_CMODEL_LARGE "large"
#define STR_CMODEL_EXTREME "extreme"
-#define OPTSTR_EXPLICIT_RELOCS "explicit-relocs"
-#define STR_EXPLICIT_RELOCS_AUTO "auto"
-#define STR_EXPLICIT_RELOCS_NONE "none"
-#define STR_EXPLICIT_RELOCS_ALWAYS "always"
-
#define OPTSTR_FRECIPE "frecipe"
#define OPTSTR_DIV32 "div32"
#define OPTSTR_LAM_BH "lam-bh"
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 95517ec61da..594e5a00c98 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -7533,18 +7533,6 @@ loongarch_option_override_internal (struct gcc_options *opts,
loongarch_update_gcc_opt_status (&la_target, opts, opts_set);
loongarch_cpu_option_override (&la_target, opts, opts_set);
- if (la_opt_explicit_relocs != M_OPT_UNSET
- && la_opt_explicit_relocs_backward != M_OPT_UNSET)
- error ("do not use %qs (with %qs) and %qs (without %qs) together",
- "-mexplicit-relocs=", "=",
- la_opt_explicit_relocs_backward ? "-mexplicit-relocs"
- : "-mno-explicit-relocs", "=");
-
- if (la_opt_explicit_relocs_backward != M_OPT_UNSET)
- la_opt_explicit_relocs = (la_opt_explicit_relocs_backward
- ? EXPLICIT_RELOCS_ALWAYS
- : EXPLICIT_RELOCS_NONE);
-
if (la_opt_explicit_relocs == M_OPT_UNSET)
la_opt_explicit_relocs = (HAVE_AS_EXPLICIT_RELOCS
? (loongarch_mrelax
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index 76b42d51d09..adb2304fbd5 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -202,7 +202,7 @@ Target RejectNegative Joined Enum(explicit_relocs) Var(la_opt_explicit_relocs) I
Use %reloc() assembly operators.
mexplicit-relocs
-Target Var(la_opt_explicit_relocs_backward) Init(M_OPT_UNSET)
+Target Alias(mexplicit-relocs=, always, none)
Use %reloc() assembly operators (for backward compatibility).
mrecip
--
2.43.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re:[pushed] [PATCH v2 0/4] Adjust option handling code
2024-01-08 1:14 [PATCH v2 0/4] Adjust option handling code Yang Yujie
` (3 preceding siblings ...)
2024-01-08 1:14 ` [PATCH v2 4/4] LoongArch: Simplify -mexplicit-reloc definitions Yang Yujie
@ 2024-01-10 3:57 ` chenglulu
4 siblings, 0 replies; 6+ messages in thread
From: chenglulu @ 2024-01-10 3:57 UTC (permalink / raw)
To: Yang Yujie, gcc-patches; +Cc: xry111, xuchenghua
Pushed to r14-7085...r14-7088
在 2024/1/8 上午9:14, Yang Yujie 写道:
> This patchset performs some code cleanup, and is bootstrapped and regtested
> on loongarch64-linux-gnu.
>
> Changes from v1 -> v2:
> * Replaced all TARGET_<evolution> macros from .opt.
> * Fixed definition of ISA_HAS_LAMCAS.
>
> Yang Yujie (4):
> LoongArch: Handle ISA evolution switches along with other options
> LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64
> LoongArch: Use enums for constants
> LoongArch: Simplify -mexplicit-reloc definitions
>
> gcc/config/loongarch/genopts/genstr.sh | 2 +-
> .../loongarch/genopts/loongarch-strings | 8 +-
> gcc/config/loongarch/genopts/loongarch.opt.in | 16 +--
> gcc/config/loongarch/lasx.md | 4 +-
> gcc/config/loongarch/loongarch-builtins.cc | 6 +-
> gcc/config/loongarch/loongarch-c.cc | 2 +-
> gcc/config/loongarch/loongarch-cpu.cc | 2 +-
> gcc/config/loongarch/loongarch-def.cc | 14 +-
> gcc/config/loongarch/loongarch-def.h | 120 +++++++++++-------
> gcc/config/loongarch/loongarch-driver.cc | 5 +-
> gcc/config/loongarch/loongarch-opts.cc | 27 +++-
> gcc/config/loongarch/loongarch-opts.h | 26 +++-
> gcc/config/loongarch/loongarch-str.h | 7 +-
> gcc/config/loongarch/loongarch.cc | 36 ++----
> gcc/config/loongarch/loongarch.md | 12 +-
> gcc/config/loongarch/loongarch.opt | 20 +--
> gcc/config/loongarch/lsx.md | 4 +-
> gcc/config/loongarch/sync.md | 22 ++--
> 18 files changed, 180 insertions(+), 153 deletions(-)
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-01-10 3:57 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2024-01-08 1:14 [PATCH v2 0/4] Adjust option handling code Yang Yujie
2024-01-08 1:14 ` [PATCH v2 1/4] LoongArch: Handle ISA evolution switches along with other options Yang Yujie
2024-01-08 1:14 ` [PATCH v2 2/4] LoongArch: Rename ISA_BASE_LA64V100 to ISA_BASE_LA64 Yang Yujie
2024-01-08 1:14 ` [PATCH v2 3/4] LoongArch: Use enums for constants Yang Yujie
2024-01-08 1:14 ` [PATCH v2 4/4] LoongArch: Simplify -mexplicit-reloc definitions Yang Yujie
2024-01-10 3:57 ` Re:[pushed] [PATCH v2 0/4] Adjust option handling code chenglulu
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