* [PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation
@ 2024-01-10 1:31 Edwin Lu
2024-01-10 1:31 ` [PATCH V2 1/4][RFC] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 1:31 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This series is a prototype for adding all typed instructions to a dfa
scheduling pipeline.
This is what I currently have for cleaning up the cost models. Adding the
vector insns to the dfa pipelines changes the expected output of a lot of test
cases as expected. Should I update the expected output of the test cases to
the output of the new cost model? I'm not fully sure which codegen is more
optimal. Please let me know if I should do so and I'll add a patch adjusting
the expected testcase output.
Edwin Lu (4):
RISC-V: Add non-vector types to dfa pipelines
RISC-V: Add vector related reservations
RISC-V: Use default cost model for insn scheduling for tests affected
in PR113249
RISC-V: Enable assert for insn_has_dfa_reservation
---
V2:
- Update non-vector insn types and add new pipelines
- Add -fno-schedule-insn -fno-schedule-insn2 to some test cases
---
gcc/config/riscv/generic-ooo.md | 40 ++++-
gcc/config/riscv/generic.md | 163 +++++++++++++++++-
gcc/config/riscv/riscv.cc | 6 +-
gcc/config/riscv/riscv.md | 18 +-
gcc/config/riscv/sifive-7.md | 161 ++++++++++++++++-
gcc/config/riscv/vector.md | 2 +-
gcc/config/riscv/zc.md | 96 +++++------
.../g++.target/riscv/rvv/base/bug-1.C | 2 +
.../riscv/rvv/autovec/reduc/reduc_call-2.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-102.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-108.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-114.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-119.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-12.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-16.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-17.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-19.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-21.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-23.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-25.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-27.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-29.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-31.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-33.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-35.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-4.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-40.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-44.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-50.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-56.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-62.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-68.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-74.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-79.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-8.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-84.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-90.c | 2 +
.../riscv/rvv/base/binop_vx_constraint-96.c | 2 +
.../rvv/base/float-point-dynamic-frm-30.c | 2 +
.../gcc.target/riscv/rvv/base/pr108185-1.c | 2 +
.../gcc.target/riscv/rvv/base/pr108185-2.c | 2 +
.../gcc.target/riscv/rvv/base/pr108185-3.c | 2 +
.../gcc.target/riscv/rvv/base/pr108185-4.c | 2 +
.../gcc.target/riscv/rvv/base/pr108185-5.c | 2 +
.../gcc.target/riscv/rvv/base/pr108185-6.c | 2 +
.../gcc.target/riscv/rvv/base/pr108185-7.c | 2 +
.../riscv/rvv/base/shift_vx_constraint-1.c | 2 +
.../gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 2 +
.../riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 +
.../riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 +
.../riscv/rvv/vsetvl/vlmax_back_prop-32.c | 2 +
.../riscv/rvv/vsetvl/vlmax_back_prop-33.c | 2 +
.../riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 +
.../riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 +
.../riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 +
.../riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 +
gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 +
65 files changed, 532 insertions(+), 70 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V2 1/4][RFC] RISC-V: Add non-vector types to dfa pipelines
2024-01-10 1:31 [PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation Edwin Lu
@ 2024-01-10 1:31 ` Edwin Lu
2024-01-10 1:31 ` [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations Edwin Lu
` (2 subsequent siblings)
3 siblings, 0 replies; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 1:31 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This patch adds non-vector related insn reservations and updates/creates
new insn reservations so all non-vector typed instructions have a reservation.
gcc/ChangeLog:
* config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
(generic_ooo_branch): ditto
* config/riscv/generic.md (generic_sfb_alu): ditto
(generic_fmul_half): ditto
* config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
* config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
(sifive_7_popcount): ditto
* config/riscv/vector.md: change rdfrm to fmove
* config/riscv/zc.md: change pushpop to load/store
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
V2:
- Add insn reservations for HF fmul
- Remove/adjust insn types
---
gcc/config/riscv/generic-ooo.md | 15 +++++-
gcc/config/riscv/generic.md | 20 +++++--
gcc/config/riscv/riscv.md | 18 +++----
gcc/config/riscv/sifive-7.md | 17 +++++-
gcc/config/riscv/vector.md | 2 +-
gcc/config/riscv/zc.md | 96 ++++++++++++++++-----------------
6 files changed, 102 insertions(+), 66 deletions(-)
diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index 421a7bb929d..ef8cb96daf4 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -115,9 +115,20 @@ (define_insn_reservation "generic_ooo_vec_loadstore_seg" 10
(define_insn_reservation "generic_ooo_alu" 1
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
- move,bitmanip,min,max,minu,maxu,clz,ctz"))
+ move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
+ condmove,mvpair,zicond"))
"generic_ooo_issue,generic_ooo_ixu_alu")
+(define_insn_reservation "generic_ooo_sfb_alu" 2
+ (and (eq_attr "tune" "generic_ooo")
+ (eq_attr "type" "sfb_alu"))
+ "generic_ooo_issue,generic_ooo_ixu_alu")
+
+;; Branch instructions
+(define_insn_reservation "generic_ooo_branch" 1
+ (and (eq_attr "tune" "generic_ooo")
+ (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+ "generic_ooo_issue,generic_ooo_ixu_alu")
;; Float move, convert and compare.
(define_insn_reservation "generic_ooo_float_move" 3
@@ -184,7 +195,7 @@ (define_insn_reservation "generic_ooo_popcount" 2
(define_insn_reservation "generic_ooo_vec_alu" 3
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
- vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov"))
+ vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector float comparison, conversion etc.
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index b99ae345bb3..45986cfea89 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,9 @@ (define_cpu_unit "fdivsqrt" "pipe0")
(define_insn_reservation "generic_alu" 1
(and (eq_attr "tune" "generic")
- (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
+ (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
+ move,bitmanip,min,max,minu,maxu,clz,ctz,rotate,atomic,\
+ condmove,crypto,mvpair,zicond"))
"alu")
(define_insn_reservation "generic_load" 3
@@ -47,12 +49,17 @@ (define_insn_reservation "generic_xfer" 3
(define_insn_reservation "generic_branch" 1
(and (eq_attr "tune" "generic")
- (eq_attr "type" "branch,jump,call,jalr"))
+ (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
+ "alu")
+
+(define_insn_reservation "generic_sfb_alu" 2
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "sfb_alu"))
"alu")
(define_insn_reservation "generic_imul" 10
(and (eq_attr "tune" "generic")
- (eq_attr "type" "imul,clmul"))
+ (eq_attr "type" "imul,clmul,cpop"))
"imuldiv*10")
(define_insn_reservation "generic_idivsi" 34
@@ -67,6 +74,12 @@ (define_insn_reservation "generic_idivdi" 66
(eq_attr "mode" "DI")))
"imuldiv*66")
+(define_insn_reservation "generic_fmul_half" 5
+ (and (eq_attr "tune" "generic")
+ (and (eq_attr "type" "fadd,fmul,fmadd")
+ (eq_attr "mode" "HF")))
+ "alu")
+
(define_insn_reservation "generic_fmul_single" 5
(and (eq_attr "tune" "generic")
(and (eq_attr "type" "fadd,fmul,fmadd")
@@ -88,3 +101,4 @@ (define_insn_reservation "generic_fsqrt" 25
(and (eq_attr "tune" "generic")
(eq_attr "type" "fsqrt"))
"fdivsqrt*25")
+
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 84212430dc0..afa15c433d0 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -322,9 +322,7 @@ (define_attr "ext_enabled" "no,yes"
;; rotate rotation instructions
;; atomic atomic instructions
;; condmove conditional moves
-;; cbo cache block instructions
;; crypto cryptography instructions
-;; pushpop zc push and pop instructions
;; mvpair zc move pair instructions
;; zicond zicond instructions
;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
@@ -464,8 +462,8 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
- atomic,condmove,cbo,crypto,pushpop,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,
- rdfrm,vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
+ atomic,condmove,crypto,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,
+ vsetvl,vsetvl_pre,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
@@ -3649,7 +3647,7 @@ (define_insn "riscv_clean_<mode>"
UNSPECV_CLEAN)]
"TARGET_ZICBOM"
"cbo.clean\t%a0"
- [(set_attr "type" "cbo")]
+ [(set_attr "type" "store")]
)
(define_insn "riscv_flush_<mode>"
@@ -3657,7 +3655,7 @@ (define_insn "riscv_flush_<mode>"
UNSPECV_FLUSH)]
"TARGET_ZICBOM"
"cbo.flush\t%a0"
- [(set_attr "type" "cbo")]
+ [(set_attr "type" "store")]
)
(define_insn "riscv_inval_<mode>"
@@ -3665,7 +3663,7 @@ (define_insn "riscv_inval_<mode>"
UNSPECV_INVAL)]
"TARGET_ZICBOM"
"cbo.inval\t%a0"
- [(set_attr "type" "cbo")]
+ [(set_attr "type" "store")]
)
(define_insn "riscv_zero_<mode>"
@@ -3673,7 +3671,7 @@ (define_insn "riscv_zero_<mode>"
UNSPECV_ZERO)]
"TARGET_ZICBOZ"
"cbo.zero\t%a0"
- [(set_attr "type" "cbo")]
+ [(set_attr "type" "store")]
)
(define_insn "prefetch"
@@ -3689,7 +3687,7 @@ (define_insn "prefetch"
default: gcc_unreachable ();
}
}
- [(set_attr "type" "cbo")])
+ [(set_attr "type" "store")])
(define_insn "riscv_prefetchi_<mode>"
[(unspec_volatile:X [(match_operand:X 0 "address_operand" "r")
@@ -3697,7 +3695,7 @@ (define_insn "riscv_prefetchi_<mode>"
UNSPECV_PREI)]
"TARGET_ZICBOP"
"prefetch.i\t%a0"
- [(set_attr "type" "cbo")])
+ [(set_attr "type" "store")])
(define_expand "extv<mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index a63394c8c58..52904f546ed 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -34,7 +34,7 @@ (define_insn_reservation "sifive_7_fpstore" 1
(define_insn_reservation "sifive_7_branch" 1
(and (eq_attr "tune" "sifive_7")
- (eq_attr "type" "branch"))
+ (eq_attr "type" "branch,ret,trap"))
"sifive_7_B")
(define_insn_reservation "sifive_7_sfb_alu" 2
@@ -59,7 +59,8 @@ (define_insn_reservation "sifive_7_div" 16
(define_insn_reservation "sifive_7_alu" 2
(and (eq_attr "tune" "sifive_7")
- (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move"))
+ (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move,bitmanip,\
+ rotate,min,max,minu,maxu,clz,ctz,atomic,condmove,crypto,mvpair,zicond"))
"sifive_7_A|sifive_7_B")
(define_insn_reservation "sifive_7_load_immediate" 1
@@ -67,6 +68,12 @@ (define_insn_reservation "sifive_7_load_immediate" 1
(eq_attr "type" "nop,const,auipc"))
"sifive_7_A|sifive_7_B")
+(define_insn_reservation "sifive_7_hfma" 5
+ (and (eq_attr "tune" "sifive_7")
+ (and (eq_attr "type" "fadd,fmul,fmadd")
+ (eq_attr "mode" "HF")))
+ "sifive_7_B")
+
(define_insn_reservation "sifive_7_sfma" 5
(and (eq_attr "tune" "sifive_7")
(and (eq_attr "type" "fadd,fmul,fmadd")
@@ -106,6 +113,12 @@ (define_insn_reservation "sifive_7_f2i" 3
(eq_attr "type" "mfc"))
"sifive_7_A")
+;; Popcount and clmul.
+(define_insn_reservation "sifive_7_popcount" 2
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "cpop,clmul"))
+ "sifive_7_A")
+
(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
"sifive_7_alu,sifive_7_branch")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 24b7b4394be..a379ba7439e 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -1036,7 +1036,7 @@ (define_insn "frrmsi"
(reg:SI FRM_REGNUM))]
"TARGET_VECTOR"
"frrm\t%0"
- [(set_attr "type" "rdfrm")
+ [(set_attr "type" "fmove")
(set_attr "mode" "SI")]
)
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 216232cb9f2..462ab37569e 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_<mode>"
(const_int <slot0_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_<mode>"
(const_int <slot1_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_<mode>"
(const_int <slot2_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s1}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_<mode>"
(const_int <slot3_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s2}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_<mode>"
(const_int <slot4_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s3}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_<mode>"
(const_int <slot5_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s4}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_<mode>"
(const_int <slot6_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s5}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_<mode>"
(const_int <slot7_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s6}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_<mode>"
(const_int <slot8_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s7}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_<mode>"
(const_int <slot9_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s8}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_<mode>"
(const_int <slot10_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s9}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_pop_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_<mode>"
(const_int <slot12_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s11}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_ra_<mode>"
[(set (reg:X SP_REGNUM)
@@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -378,7 +378,7 @@ (define_insn "@gpr_multi_popret_up_to_s0_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -397,7 +397,7 @@ (define_insn "@gpr_multi_popret_up_to_s1_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s1}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -419,7 +419,7 @@ (define_insn "@gpr_multi_popret_up_to_s2_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s2}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -444,7 +444,7 @@ (define_insn "@gpr_multi_popret_up_to_s3_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s3}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -472,7 +472,7 @@ (define_insn "@gpr_multi_popret_up_to_s4_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s4}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -503,7 +503,7 @@ (define_insn "@gpr_multi_popret_up_to_s5_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s5}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -537,7 +537,7 @@ (define_insn "@gpr_multi_popret_up_to_s6_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s6}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -574,7 +574,7 @@ (define_insn "@gpr_multi_popret_up_to_s7_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s7}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -614,7 +614,7 @@ (define_insn "@gpr_multi_popret_up_to_s8_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s8}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -657,7 +657,7 @@ (define_insn "@gpr_multi_popret_up_to_s9_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s9}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popret_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -706,7 +706,7 @@ (define_insn "@gpr_multi_popret_up_to_s11_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s11}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
[(set (reg:X SP_REGNUM)
@@ -722,7 +722,7 @@ (define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -741,7 +741,7 @@ (define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -763,7 +763,7 @@ (define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s1}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -788,7 +788,7 @@ (define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s2}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -816,7 +816,7 @@ (define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s3}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -847,7 +847,7 @@ (define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s4}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -881,7 +881,7 @@ (define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s5}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -918,7 +918,7 @@ (define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s6}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -958,7 +958,7 @@ (define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s7}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1001,7 +1001,7 @@ (define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s8}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1047,7 +1047,7 @@ (define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s9}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1099,7 +1099,7 @@ (define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s11}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "load")])
(define_insn "@gpr_multi_push_up_to_ra_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1110,7 +1110,7 @@ (define_insn "@gpr_multi_push_up_to_ra_<mode>"
(match_operand 0 "stack_push_up_to_ra_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s0_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1124,7 +1124,7 @@ (define_insn "@gpr_multi_push_up_to_s0_<mode>"
(match_operand 0 "stack_push_up_to_s0_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s1_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1141,7 +1141,7 @@ (define_insn "@gpr_multi_push_up_to_s1_<mode>"
(match_operand 0 "stack_push_up_to_s1_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s1}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s2_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1161,7 +1161,7 @@ (define_insn "@gpr_multi_push_up_to_s2_<mode>"
(match_operand 0 "stack_push_up_to_s2_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s2}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s3_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1184,7 +1184,7 @@ (define_insn "@gpr_multi_push_up_to_s3_<mode>"
(match_operand 0 "stack_push_up_to_s3_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s3}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s4_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1210,7 +1210,7 @@ (define_insn "@gpr_multi_push_up_to_s4_<mode>"
(match_operand 0 "stack_push_up_to_s4_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s4}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s5_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1239,7 +1239,7 @@ (define_insn "@gpr_multi_push_up_to_s5_<mode>"
(match_operand 0 "stack_push_up_to_s5_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s5}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s6_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1271,7 +1271,7 @@ (define_insn "@gpr_multi_push_up_to_s6_<mode>"
(match_operand 0 "stack_push_up_to_s6_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s6}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s7_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1306,7 +1306,7 @@ (define_insn "@gpr_multi_push_up_to_s7_<mode>"
(match_operand 0 "stack_push_up_to_s7_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s7}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s8_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1344,7 +1344,7 @@ (define_insn "@gpr_multi_push_up_to_s8_<mode>"
(match_operand 0 "stack_push_up_to_s8_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s8}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s9_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1385,7 +1385,7 @@ (define_insn "@gpr_multi_push_up_to_s9_<mode>"
(match_operand 0 "stack_push_up_to_s9_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s9}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
(define_insn "@gpr_multi_push_up_to_s11_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1432,7 +1432,7 @@ (define_insn "@gpr_multi_push_up_to_s11_<mode>"
(match_operand 0 "stack_push_up_to_s11_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s11}, %0"
-[(set_attr "type" "pushpop")])
+[(set_attr "type" "store")])
;; ZCMP mv
(define_insn "*mva01s<X:mode>"
--
2.34.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations
2024-01-10 1:31 [PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation Edwin Lu
2024-01-10 1:31 ` [PATCH V2 1/4][RFC] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
@ 2024-01-10 1:31 ` Edwin Lu
2024-01-10 16:00 ` Robin Dapp
2024-01-10 1:31 ` [PATCH V2 3/4][RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249 Edwin Lu
2024-01-10 1:31 ` [PATCH V2 4/4][RFC] RISC-V: Enable assert for insn_has_dfa_reservation Edwin Lu
3 siblings, 1 reply; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 1:31 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu, Robin Dapp
This patch copies the vector reservations from generic-ooo.md and
inserts them into generic.md and sifive.md. Creates new vector crypto related
insn reservations.
gcc/ChangeLog:
* config/riscv/generic-ooo.md (generic_ooo_crypto_aes): create reservation
(generic_ooo_crypto_sha): ditto
(generic_ooo_crypto_sm): ditto
(generic_ooo_vec_vesetvl): ditto
(generic_ooo_vec_vsetvl): ditto
* config/riscv/generic.md (pipe0): ditto
(generic_vec_load): ditto
(generic_vec_store): ditto
(generic_vec_loadstore_seg): ditto
(generic_vec_alu): ditto
(generic_vec_fcmp): ditto
(generic_vec_imul): ditto
(generic_vec_fadd): ditto
(generic_vec_fmul): ditto
(generic_crypto): ditto
(generic_crypto_aes): ditto
(generic_crypto_sha): ditto
(generic_crypto_sm): ditto
(generic_perm): ditto
(generic_vec_reduction): ditto
(generic_vec_ordered_reduction): ditto
(generic_vec_idiv): ditto
(generic_vec_float_divsqrt): ditto
(generic_vec_mask): ditto
(generic_vec_vesetvl): ditto
(generic_vec_setrm): ditto
(generic_vec_readlen): ditto
* config/riscv/sifive-7.md (sifive_7): ditto
(sifive_7_vec_load): ditto
(sifive_7_vec_store): ditto
(sifive_7_vec_loadstore_seg): ditto
(sifive_7_vec_alu): ditto
(sifive_7_vec_fcmp): ditto
(sifive_7_vec_imul): ditto
(sifive_7_vec_fadd): ditto
(sifive_7_vec_fmul): ditto
(sifive_7_crypto): ditto
(sifive_7_crypto_aes): ditto
(sifive_7_crypto_sha): ditto
(sifive_7_crypto_sm): ditto
(sifive_7_perm): ditto
(sifive_7_vec_reduction): ditto
(sifive_7_vec_ordered_reduction): ditto
(sifive_7_vec_idiv): ditto
(sifive_7_vec_float_divsqrt): ditto
(sifive_7_vec_mask): ditto
(sifive_7_vec_vesetvl): ditto
(sifive_7_vec_setrm): ditto
(sifive_7_vec_readlen): ditto
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
Co-authored-by: Robin Dapp <rdapp.gcc@gmail.com>
---
V2:
- Remove unnecessary syntax changes in generic-ooo
- Add new vector crypto reservations and types to
pipelines
---
gcc/config/riscv/generic-ooo.md | 27 +++++-
gcc/config/riscv/generic.md | 143 +++++++++++++++++++++++++++++++
gcc/config/riscv/sifive-7.md | 144 ++++++++++++++++++++++++++++++++
3 files changed, 311 insertions(+), 3 deletions(-)
diff --git a/gcc/config/riscv/generic-ooo.md b/gcc/config/riscv/generic-ooo.md
index ef8cb96daf4..fb5f34c0ef2 100644
--- a/gcc/config/riscv/generic-ooo.md
+++ b/gcc/config/riscv/generic-ooo.md
@@ -195,7 +195,8 @@ (define_insn_reservation "generic_ooo_popcount" 2
(define_insn_reservation "generic_ooo_vec_alu" 3
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
- vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector"))
+ vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\
+ vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector float comparison, conversion etc.
@@ -209,7 +210,8 @@ (define_insn_reservation "generic_ooo_vec_fcmp" 3
;; Vector integer multiplication.
(define_insn_reservation "generic_ooo_vec_imul" 4
(and (eq_attr "tune" "generic_ooo")
- (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul"))
+ (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
+ vghsh,vgmul"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector float addition.
@@ -230,6 +232,25 @@ (define_insn_reservation "generic_ooo_crypto" 4
(eq_attr "type" "crypto"))
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
+;; Vector crypto, AES
+(define_insn_reservation "generic_ooo_crypto_aes" 4
+ (and (eq_attr "tune" "generic_ooo")
+ (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz"))
+ "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
+
+;; Vector crypto, sha
+(define_insn_reservation "generic_ooo_crypto_sha" 4
+ (and (eq_attr "tune" "generic_ooo")
+ (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl"))
+ "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
+
+;; Vector crypto, SM3/4
+(define_insn_reservation "generic_ooo_crypto_sm" 4
+ (and (eq_attr "tune" "generic_ooo")
+ (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c"))
+ "generic_ooo_vxu_issue,generic_ooo_vxu_alu")
+
+
;; Vector permute.
(define_insn_reservation "generic_ooo_perm" 3
(and (eq_attr "tune" "generic_ooo")
@@ -271,7 +292,7 @@ (define_insn_reservation "generic_ooo_vec_mask" 2
"generic_ooo_vxu_issue,generic_ooo_vxu_alu")
;; Vector vsetvl.
-(define_insn_reservation "generic_ooo_vec_vesetvl" 1
+(define_insn_reservation "generic_ooo_vec_vsetvl" 1
(and (eq_attr "tune" "generic_ooo")
(eq_attr "type" "vsetvl,vsetvl_pre"))
"generic_ooo_vxu_issue")
diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index 45986cfea89..45c9027229a 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -25,6 +25,15 @@ (define_cpu_unit "alu" "pipe0")
(define_cpu_unit "imuldiv" "pipe0")
(define_cpu_unit "fdivsqrt" "pipe0")
+;; Separate issue queue for vector instructions.
+(define_cpu_unit "generic_vxu_issue" "pipe0")
+
+;; Vector execution unit.
+(define_cpu_unit "generic_vxu_alu" "pipe0")
+
+;; Vector subunit that does mult/div/sqrt.
+(define_cpu_unit "generic_vxu_multicycle" "pipe0")
+
(define_insn_reservation "generic_alu" 1
(and (eq_attr "tune" "generic")
(eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
@@ -102,3 +111,137 @@ (define_insn_reservation "generic_fsqrt" 25
(eq_attr "type" "fsqrt"))
"fdivsqrt*25")
+;; Vector load/store
+(define_insn_reservation "generic_vec_load" 6
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+(define_insn_reservation "generic_vec_store" 6
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector segment loads/stores.
+(define_insn_reservation "generic_vec_loadstore_seg" 10
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
+ vssegte,vssegts,vssegtux,vssegtox"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Regular vector operations and integer comparisons.
+(define_insn_reservation "generic_vec_alu" 3
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
+ vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\
+ vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector float comparison, conversion etc.
+(define_insn_reservation "generic_vec_fcmp" 3
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
+ vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
+ vfncvtftoi,vfncvtftof"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector integer multiplication.
+(define_insn_reservation "generic_vec_imul" 4
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
+ vghsh,vgmul"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector float addition.
+(define_insn_reservation "generic_vec_fadd" 4
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vfalu,vfwalu"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector float multiplication and FMA.
+(define_insn_reservation "generic_vec_fmul" 6
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector crypto, assumed to be a generic operation for now.
+(define_insn_reservation "generic_crypto" 4
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "crypto"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector crypto, AES
+(define_insn_reservation "generic_crypto_aes" 4
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector crypto, sha
+(define_insn_reservation "generic_crypto_sha" 4
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector crypto, SM3/4
+(define_insn_reservation "generic_crypto_sm" 4
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector permute.
+(define_insn_reservation "generic_perm" 3
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\
+ vislide1down,vfslide1up,vfslide1down,vgather,vcompress"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector reduction.
+(define_insn_reservation "generic_vec_reduction" 8
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vired,viwred,vfredu,vfwredu"))
+ "generic_vxu_issue,generic_vxu_multicycle")
+
+;; Vector ordered reduction, assume the latency number is for
+;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost
+;; for larger vectors.
+(define_insn_reservation "generic_vec_ordered_reduction" 10
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vfredo,vfwredo"))
+ "generic_vxu_issue,generic_vxu_multicycle*3")
+
+;; Vector integer division, assume not pipelined.
+(define_insn_reservation "generic_vec_idiv" 16
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vidiv"))
+ "generic_vxu_issue,generic_vxu_multicycle*3")
+
+;; Vector float divisions and sqrt, assume not pipelined.
+(define_insn_reservation "generic_vec_float_divsqrt" 16
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vfdiv,vfsqrt"))
+ "generic_vxu_issue,generic_vxu_multicycle*3")
+
+;; Vector mask operations.
+(define_insn_reservation "generic_vec_mask" 2
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
+ vfmovvf,vfmovfv"))
+ "generic_vxu_issue,generic_vxu_alu")
+
+;; Vector vsetvl.
+(define_insn_reservation "generic_vec_vesetvl" 1
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "vsetvl,vsetvl_pre"))
+ "generic_vxu_issue")
+
+;; Vector rounding mode setters, assume pipeline barrier.
+(define_insn_reservation "generic_vec_setrm" 20
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "wrvxrm,wrfrm"))
+ "generic_vxu_issue,generic_vxu_issue*3")
+
+;; Vector read vlen/vlenb.
+(define_insn_reservation "generic_vec_readlen" 4
+ (and (eq_attr "tune" "generic")
+ (eq_attr "type" "rdvlenb,rdvl"))
+ "generic_vxu_issue,generic_vxu_issue")
diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index 52904f546ed..97ec7d0847c 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -12,6 +12,15 @@ (define_cpu_unit "sifive_7_B" "sifive_7")
(define_cpu_unit "sifive_7_idiv" "sifive_7")
(define_cpu_unit "sifive_7_fpu" "sifive_7")
+;; Separate issue queue for vector instructions.
+(define_cpu_unit "sifive_7_vxu_issue" "sifive_7")
+
+;; Vector execution unit.
+(define_cpu_unit "sifive_7_vxu_alu" "sifive_7")
+
+;; Vector subunit that does mult/div/sqrt.
+(define_cpu_unit "sifive_7_vxu_multicycle" "sifive_7")
+
(define_insn_reservation "sifive_7_load" 3
(and (eq_attr "tune" "sifive_7")
(eq_attr "type" "load"))
@@ -119,6 +128,141 @@ (define_insn_reservation "sifive_7_popcount" 2
(eq_attr "type" "cpop,clmul"))
"sifive_7_A")
+;; Vector load/store
+(define_insn_reservation "sifive_7_vec_load" 6
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vlde,vldm,vlds,vldux,vldox,vldff,vldr"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+(define_insn_reservation "sifive_7_vec_store" 6
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vste,vstm,vsts,vstux,vstox,vstr"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector segment loads/stores.
+(define_insn_reservation "sifive_7_vec_loadstore_seg" 10
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
+ vssegte,vssegts,vssegtux,vssegtox"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Regular vector operations and integer comparisons.
+(define_insn_reservation "sifive_7_vec_alu" 3
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vialu,viwalu,vext,vicalu,vshift,vnshift,viminmax,vicmp,\
+ vimov,vsalu,vaalu,vsshift,vnclip,vmov,vfmov,vector,\
+ vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector float comparison, conversion etc.
+(define_insn_reservation "sifive_7_vec_fcmp" 3
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
+ vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
+ vfncvtftoi,vfncvtftof"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector integer multiplication.
+(define_insn_reservation "sifive_7_vec_imul" 4
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
+ vghsh,vgmul"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector float addition.
+(define_insn_reservation "sifive_7_vec_fadd" 4
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vfalu,vfwalu"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector float multiplication and FMA.
+(define_insn_reservation "sifive_7_vec_fmul" 6
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector crypto, assumed to be a generic operation for now.
+(define_insn_reservation "sifive_7_crypto" 4
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "crypto"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector crypto, AES
+(define_insn_reservation "sifive_7_crypto_aes" 4
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector crypto, sha
+(define_insn_reservation "sifive_7_crypto_sha" 4
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector crypto, SM3/4
+(define_insn_reservation "sifive_7_crypto_sm" 4
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vsm4k,vsm4r,vsm3me,vsm3c"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector permute.
+(define_insn_reservation "sifive_7_perm" 3
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vimerge,vfmerge,vslideup,vslidedown,vislide1up,\
+ vislide1down,vfslide1up,vfslide1down,vgather,vcompress"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector reduction.
+(define_insn_reservation "sifive_7_vec_reduction" 8
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vired,viwred,vfredu,vfwredu"))
+ "sifive_7_vxu_issue,sifive_7_vxu_multicycle")
+
+;; Vector ordered reduction, assume the latency number is for
+;; a 128-bit vector. It is scaled in riscv_sched_adjust_cost
+;; for larger vectors.
+(define_insn_reservation "sifive_7_vec_ordered_reduction" 10
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vfredo,vfwredo"))
+ "sifive_7_vxu_issue,sifive_7_vxu_multicycle*3")
+
+;; Vector integer division, assume not pipelined.
+(define_insn_reservation "sifive_7_vec_idiv" 16
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vidiv"))
+ "sifive_7_vxu_issue,sifive_7_vxu_multicycle*3")
+
+;; Vector float divisions and sqrt, assume not pipelined.
+(define_insn_reservation "sifive_7_vec_float_divsqrt" 16
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vfdiv,vfsqrt"))
+ "sifive_7_vxu_issue,sifive_7_vxu_multicycle*3")
+
+;; Vector mask operations.
+(define_insn_reservation "sifive_7_vec_mask" 2
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
+ vfmovvf,vfmovfv"))
+ "sifive_7_vxu_issue,sifive_7_vxu_alu")
+
+;; Vector vsetvl.
+(define_insn_reservation "sifive_7_vec_vesetvl" 1
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "vsetvl,vsetvl_pre"))
+ "sifive_7_vxu_issue")
+
+;; Vector rounding mode setters, assume pipeline barrier.
+(define_insn_reservation "sifive_7_vec_setrm" 20
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "wrvxrm,wrfrm"))
+ "sifive_7_vxu_issue,sifive_7_vxu_issue*3")
+
+;; Vector read vlen/vlenb.
+(define_insn_reservation "sifive_7_vec_readlen" 4
+ (and (eq_attr "tune" "sifive_7")
+ (eq_attr "type" "rdvlenb,rdvl"))
+ "sifive_7_vxu_issue,sifive_7_vxu_issue")
+
(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
"sifive_7_alu,sifive_7_branch")
--
2.34.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V2 3/4][RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249
2024-01-10 1:31 [PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation Edwin Lu
2024-01-10 1:31 ` [PATCH V2 1/4][RFC] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
2024-01-10 1:31 ` [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations Edwin Lu
@ 2024-01-10 1:31 ` Edwin Lu
2024-01-10 1:31 ` [PATCH V2 4/4][RFC] RISC-V: Enable assert for insn_has_dfa_reservation Edwin Lu
3 siblings, 0 replies; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 1:31 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
Use default cost model scheduling on these test cases. All these tests
introduce scan dump failures with -mtune generic-ooo. Since the vector
cost models are the same across all three tunes, some of the tests
in PR113249 will be fixed with this patch series.
Unfortunately, 40 unique testsuite failures (scan dumps) will still be present.
I don't know how optimal the new output is compared to the old. Should I update
the testcase expected output to match the new scan dumps?
PR target/113249
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/bug-1.C: use default tune scheduling
* gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-50.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-56.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-62.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-68.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-74.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-79.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-84.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-90.c: ditto
* gcc.target/riscv/rvv/base/binop_vx_constraint-96.c: ditto
* gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c: ditto
* gcc.target/riscv/rvv/base/pr108185-1.c: ditto
* gcc.target/riscv/rvv/base/pr108185-2.c: ditto
* gcc.target/riscv/rvv/base/pr108185-3.c: ditto
* gcc.target/riscv/rvv/base/pr108185-4.c: ditto
* gcc.target/riscv/rvv/base/pr108185-5.c: ditto
* gcc.target/riscv/rvv/base/pr108185-6.c: ditto
* gcc.target/riscv/rvv/base/pr108185-7.c: ditto
* gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: ditto
* gcc.target/riscv/rvv/vsetvl/pr111037-3.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c: ditto
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c: ditto
* gfortran.dg/vect/vect-8.f90: ditto
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
V2:
- New patch
---
gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-102.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-108.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-114.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-119.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-12.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-16.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-17.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-19.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-21.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-23.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-25.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-27.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-29.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-31.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-33.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-35.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-40.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-44.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-50.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-56.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-62.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-68.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-74.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-79.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-84.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-90.c | 2 ++
.../gcc.target/riscv/rvv/base/binop_vx_constraint-96.c | 2 ++
.../gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c | 2 ++
gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c | 2 ++
.../gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c | 2 ++
gcc/testsuite/gfortran.dg/vect/vect-8.f90 | 2 ++
58 files changed, 116 insertions(+)
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
index c1070f9eb16..6f62a64224d 100644
--- a/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/bug-1.C
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
template < class T >
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
index 7be22d60bf2..17a6b6f27fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/reduc/reduc_call-2.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-additional-options "-march=rv32gcv_zvfh -mabi=ilp32d --param=riscv-autovec-preference=scalable -fno-vect-cost-model -ffast-math" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "reduc_call-1.c"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
index 4b24b971cba..8386b42e9b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
index 99acc51b4ff..e2ed4b76a16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
index d595c446503..61340be8362 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
index 0b51175f66c..0f1485e3c0a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, uint64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
index 634c12a4c0e..173ac625ada 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
index 651d61001c1..1edba8980b4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
index d19a9fda235..75340c3da6c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
index 16f431542d8..7e4aedc1cdc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
index 347c846dcbb..755e92a9cd7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
index bc414440ba2..2c82dc0688a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
index ce3f3af9c3d..e2ac6a3d9e1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
index 4946f84b916..436a0e85f3d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
index 5f2eede0422..72b321607c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
index 5f2eede0422..72b321607c3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
index 88fcba60345..6908c78e19b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
index 88fcba60345..6908c78e19b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
index 87a16453fea..ee1db1c41ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
index c0321cefb9a..fb969eb50a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
index ab0f13ba255..542f43eca49 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
index 3893e17511d..31109a81ec3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
index b0ea553bf89..924f4507ba3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
index 350697d764d..659d8d9e702 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
index 0f138c5d3c6..63874605759 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
index f4cbf095357..a214d70cb2c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
index d606078e85f..efa659b2752 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
index 9bf9ff59de7..6a26248096d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
index bca55b239f9..429fe129003 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, uint64_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
index 586e26499db..0cd0af76186 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
index d1bbb78f5ed..bb1690e81e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
void f (void * in, void *out, int32_t x, int n)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
index bf5772073f7..5b666a920da 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-30.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
index c3d0b10271a..4c6e88e7eed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
index bd13ba916da..0844e3e8713 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-2.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
index 99928f7b1cc..49a574485fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-3.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
index 321cd5c818e..cef0a11b2d4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-4.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gc_zve64d -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
index 575a7842cdf..3f0d67726bc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-5.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
index 95a11d37016..4ed658899f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-6.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
index 8f6f0b11f09..95b7ff97666 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr108185-7.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
index 250e017cc86..9e0b41ccba7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
/* { dg-final { check-function-bodies "**" "" } } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
index 110e55b3cbe..5e1859cd13b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gc_zve64f_zvfh -mabi=ilp32d -O3" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
index 4583504bd5a..f4f0e52971a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-28.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
index f16f4b9c37d..7e01b81682b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-29.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
index 43b443be6cb..5615cb1f97f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-32.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
index 67855581fb2..c906b153ab8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-33.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
index 960c9bff765..006df7edf8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-17.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
index 5f22e8d0e8e..cc6d8221516 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-18.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
index e5f35c0f018..9704e444d54 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_single_block-19.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
index 0532c7d4207..476735dcb2e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
index b664c4b67eb..c7b7db33849 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-11.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
index 04c4b886eec..80ff75f6d2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-12.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
index 1404c9dc0d5..127dc7ff06d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-4.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
index 1404c9dc0d5..127dc7ff06d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-5.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
index 609c68dfcbe..e19e869e241 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-6.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
index 043f17737ae..90eca5b1ae6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-7.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
index 0bedde84005..17b217bc82c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-8.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
index 0bedde84005..17b217bc82c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-9.c
@@ -1,5 +1,7 @@
/* { dg-do compile } */
/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
+// PR113249
+/* { dg-additional-options "-fno-schedule-insns -fno-schedule-insns2" } */
#include "riscv_vector.h"
diff --git a/gcc/testsuite/gfortran.dg/vect/vect-8.f90 b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
index 938dfc29754..f77ec9fb87a 100644
--- a/gcc/testsuite/gfortran.dg/vect/vect-8.f90
+++ b/gcc/testsuite/gfortran.dg/vect/vect-8.f90
@@ -1,6 +1,8 @@
! { dg-do compile }
! { dg-require-effective-target vect_double }
! { dg-additional-options "-fno-tree-loop-distribute-patterns -finline-matmul-limit=0" }
+! PR113249
+! { dg-options "-fno-schedule-insns -fno-schedule-insns2" { target { riscv*-*-* } } }
module lfk_prec
integer, parameter :: dp=kind(1.d0)
--
2.34.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH V2 4/4][RFC] RISC-V: Enable assert for insn_has_dfa_reservation
2024-01-10 1:31 [PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation Edwin Lu
` (2 preceding siblings ...)
2024-01-10 1:31 ` [PATCH V2 3/4][RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249 Edwin Lu
@ 2024-01-10 1:31 ` Edwin Lu
3 siblings, 0 replies; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 1:31 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
Enables assert that every typed instruction is associated with a
dfa reservation
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
V2:
- No changes
---
gcc/config/riscv/riscv.cc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 32183d63180..e275fcc2245 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8150,9 +8150,11 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
/* If we ever encounter an insn without an insn reservation, trip
an assert so we can find and fix this problem. */
-#if 0
+ if (! insn_has_dfa_reservation_p (insn)) {
+ print_rtl(stderr, insn);
+ fprintf(stderr, "%d", get_attr_type (insn));
+ }
gcc_assert (insn_has_dfa_reservation_p (insn));
-#endif
return more - 1;
}
--
2.34.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations
2024-01-10 1:31 ` [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations Edwin Lu
@ 2024-01-10 16:00 ` Robin Dapp
2024-01-10 18:24 ` Edwin Lu
0 siblings, 1 reply; 11+ messages in thread
From: Robin Dapp @ 2024-01-10 16:00 UTC (permalink / raw)
To: Edwin Lu, gcc-patches; +Cc: rdapp.gcc, gnu-toolchain
Hi Edwin,
> This patch copies the vector reservations from generic-ooo.md and
> inserts them into generic.md and sifive.md. Creates new vector crypto related
> insn reservations.
In principle, the changes look good to me but I wonder if we could
split off the vector parts from generic-ooo into their own md file
(generic-vector-ooo or so?) and include this in the others? Or is
there a reason why you decided against this?
A recurring question in vector cost model discussions seems to be how
to handle the situation when a tune model does not specify a "vector tune
model". The problem exists for the scheduler descriptions and the
normal vector cost model (and possibly insn_costs as well).
Juzhe just implemented a fallback so we always use the "generic rvv" cost
model. Your changes would be in the same vein and if we could split
them off then we'd be able to easier exchange one scheduler descriptions
for another one (say if one tune model wants to use an in-order vector
model).
There is also still the question of whether to set all latencies
to 1 for an OOO core but this question should be settled separately
as soon as we have proper hardware benchmark results. If so we
would probably rename generic-vector-ooo into
generic-vector-in-order ;)
Regards
Robin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations
2024-01-10 16:00 ` Robin Dapp
@ 2024-01-10 18:24 ` Edwin Lu
2024-01-10 18:24 ` Edwin Lu
2024-01-10 19:16 ` Robin Dapp
0 siblings, 2 replies; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 18:24 UTC (permalink / raw)
To: Robin Dapp, gcc-patches; +Cc: gnu-toolchain
Hi Robin,
On 1/10/2024 8:00 AM, Robin Dapp wrote:
> Hi Edwin,
>
>> This patch copies the vector reservations from generic-ooo.md and
>> inserts them into generic.md and sifive.md. Creates new vector crypto related
>> insn reservations.
>
> In principle, the changes look good to me but I wonder if we could
> split off the vector parts from generic-ooo into their own md file
> (generic-vector-ooo or so?) and include this in the others? Or is
> there a reason why you decided against this?
>
I forgot we could include other md files into another file (I'll double
check that there isn't anything fancy for including other pipelines),
but I also thought that eventually all the tunes would have their own
vector cost pipelines. Since all the pipelines should be tuned to their
cost model, they would be different anyway. If it would be simpler for
now, I could separate the files out.
> A recurring question in vector cost model discussions seems to be how
> to handle the situation when a tune model does not specify a "vector tune
> model". The problem exists for the scheduler descriptions and the
> normal vector cost model (and possibly insn_costs as well).
>
> Juzhe just implemented a fallback so we always use the "generic rvv" cost
> model. Your changes would be in the same vein and if we could split
> them off then we'd be able to easier exchange one scheduler descriptions
> for another one (say if one tune model wants to use an in-order vector
> model).
>
I think I'm getting a bit confused. Is there a reason why we would want
to exchange scheduler descriptions like the example you provided? I'm
just thinking why a in-order model would want to use an ooo vector model
and vice versa. Please correct me if I got the wrong idea.
I also want to double check, isn't forcing all typed instructions to be
part of a dfa pipeline in effect removing a situation where a tune model
does not specify a "vector tune model"? At least from my testing with
the assert statement, I get ICEs when trying to run the testsuite
without the vector tune model even on gc.
> There is also still the question of whether to set all latencies
> to 1 for an OOO core but this question should be settled separately
> as soon as we have proper hardware benchmark results. If so we
> would probably rename generic-vector-ooo into
> generic-vector-in-order ;)
>
> Regards
> Robin
>
>
I agree the latencies can be tweaked after we get those benchmarks :)
Edwin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations
2024-01-10 18:24 ` Edwin Lu
@ 2024-01-10 18:24 ` Edwin Lu
2024-01-10 19:16 ` Robin Dapp
1 sibling, 0 replies; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 18:24 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain
Hi Robin,
On 1/10/2024 8:00 AM, Robin Dapp wrote:
> Hi Edwin,
>
>> This patch copies the vector reservations from generic-ooo.md and
>> inserts them into generic.md and sifive.md. Creates new vector crypto related
>> insn reservations.
>
> In principle, the changes look good to me but I wonder if we could
> split off the vector parts from generic-ooo into their own md file
> (generic-vector-ooo or so?) and include this in the others? Or is
> there a reason why you decided against this?
>
I forgot we could include other md files into another file (I'll double
check that there isn't anything fancy for including other pipelines),
but I also thought that eventually all the tunes would have their own
vector cost pipelines. Since all the pipelines should be tuned to their
cost model, they would be different anyway. If it would be simpler for
now, I could separate the files out.
> A recurring question in vector cost model discussions seems to be how
> to handle the situation when a tune model does not specify a "vector tune
> model". The problem exists for the scheduler descriptions and the
> normal vector cost model (and possibly insn_costs as well).
>
> Juzhe just implemented a fallback so we always use the "generic rvv" cost
> model. Your changes would be in the same vein and if we could split
> them off then we'd be able to easier exchange one scheduler descriptions
> for another one (say if one tune model wants to use an in-order vector
> model).
>
I think I'm getting a bit confused. Is there a reason why we would want
to exchange scheduler descriptions like the example you provided? I'm
just thinking why a in-order model would want to use an ooo vector model
and vice versa. Please correct me if I got the wrong idea.
I also want to double check, isn't forcing all typed instructions to be
part of a dfa pipeline in effect removing a situation where a tune model
does not specify a "vector tune model"? At least from my testing with
the assert statement, I get ICEs when trying to run the testsuite
without the vector tune model even on gc.
> There is also still the question of whether to set all latencies
> to 1 for an OOO core but this question should be settled separately
> as soon as we have proper hardware benchmark results. If so we
> would probably rename generic-vector-ooo into
> generic-vector-in-order ;)
>
> Regards
> Robin
>
>
I agree the latencies can be tweaked after we get those benchmarks :)
Edwin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations
2024-01-10 18:24 ` Edwin Lu
2024-01-10 18:24 ` Edwin Lu
@ 2024-01-10 19:16 ` Robin Dapp
2024-01-10 22:39 ` Edwin Lu
1 sibling, 1 reply; 11+ messages in thread
From: Robin Dapp @ 2024-01-10 19:16 UTC (permalink / raw)
To: Edwin Lu, gcc-patches; +Cc: rdapp.gcc, gnu-toolchain
> Since all the pipelines should be tuned to their cost model, they
> would be different anyway. If it would be simpler for now, I could
> separate the files out.
> I think I'm getting a bit confused. Is there a reason why we would
> want to exchange scheduler descriptions like the example you
> provided? I'm just thinking why a in-order model would want to use an
> ooo vector model and vice versa. Please correct me if I got the wrong
> idea.
Yeah, the confusion is understandable as it's all in flow and several
things I mentioned are artifacts of us not yet being stabilized (or
actually having hard data to base our decisions on).
Usually, once a uarch has settled there is no reason to exchange
anything, just smaller tweaks might be done. I was more thinking of
the near to mid-term future where larger changes like ripping out
one thing and using another one altogether might still happen.
Regarding out of order vs in order - for in-order pipelines we will
always want to get latencies right. For out of order it is a balancing
act (proper latencies often mean more spilling and the processor will
reorder correctly anyway).
So you're mostly right that the argument is not very strong as soon
as we really know what to do and not to do.
> I also want to double check, isn't forcing all typed instructions to
> be part of a dfa pipeline in effect removing a situation where a tune
> model does not specify a "vector tune model"? At least from my
> testing with the assert statement, I get ICEs when trying to run the
> testsuite without the vector tune model even on gc.
There are (at least) three parts of the "tune model":
- vector cost model, specifying the cost of generic vector operations,
not necessarily corresponding to an insn
- insn cost, specifying the cost of an individual insn, usually close
to latency but sometimes also "complexity" or other things.
- insn latency and other hardware scheduler properties.
We can leave out any of those which will make us fall back to default
values. Even if we forced a scheduler description we could still have
the default fallback for the other two and generate unfavorable code
as a result.
However, this is of course not desirable and we will soon have a
reasonable vector cost model that corresponds to the non-uarch
specific properties of the vector spec. Once this is in place
we will also want a somewhat generic vector scheduler description
that goes hand in hand with that. Despite the name, the vector
part of generic-ooo could be used for in-order vector uarchs and
we might want to define a different description for out-of-order
uarchs. That's a separate discussion but at least for that
contingency it would make sense to easily interchange the scheduler
description ;)
Regards
Robin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations
2024-01-10 19:16 ` Robin Dapp
@ 2024-01-10 22:39 ` Edwin Lu
2024-01-10 22:39 ` Edwin Lu
0 siblings, 1 reply; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 22:39 UTC (permalink / raw)
To: Robin Dapp, gcc-patches; +Cc: gnu-toolchain
>> Since all the pipelines should be tuned to their cost model, they
>> would be different anyway. If it would be simpler for now, I could
>> separate the files out.
>> I think I'm getting a bit confused. Is there a reason why we would
>> want to exchange scheduler descriptions like the example you
>> provided? I'm just thinking why a in-order model would want to use an
>> ooo vector model and vice versa. Please correct me if I got the wrong
>> idea.
>
> Yeah, the confusion is understandable as it's all in flow and several
> things I mentioned are artifacts of us not yet being stabilized (or
> actually having hard data to base our decisions on).
>
> Usually, once a uarch has settled there is no reason to exchange
> anything, just smaller tweaks might be done. I was more thinking of
> the near to mid-term future where larger changes like ripping out
> one thing and using another one altogether might still happen.
>
> Regarding out of order vs in order - for in-order pipelines we will
> always want to get latencies right. For out of order it is a balancing
> act (proper latencies often mean more spilling and the processor will
> reorder correctly anyway).
>
> So you're mostly right that the argument is not very strong as soon
> as we really know what to do and not to do.
>
That makes sense to me!
>> I also want to double check, isn't forcing all typed instructions to
>> be part of a dfa pipeline in effect removing a situation where a tune
>> model does not specify a "vector tune model"? At least from my
>> testing with the assert statement, I get ICEs when trying to run the
>> testsuite without the vector tune model even on gc.
>
> There are (at least) three parts of the "tune model":
> - vector cost model, specifying the cost of generic vector operations,
> not necessarily corresponding to an insn
> - insn cost, specifying the cost of an individual insn, usually close
> to latency but sometimes also "complexity" or other things.
> - insn latency and other hardware scheduler properties.
>
> We can leave out any of those which will make us fall back to default
> values. Even if we forced a scheduler description we could still have
> the default fallback for the other two and generate unfavorable code
> as a result.
>
So if I'm understanding things correctly, the costs the Juzhe is working
on in riscv.cc would be part of the vector cost model since they don't
correspond to individual instructions and only target vector code. These
costs would be the default fallback in the event of having no scheduler
descriptions for the insn.
The vector pipelines I'm working describes the insn latency categorized
by the insn type. The scheduler will attempt to generate favorable code
by this description but also consider the vector cost model. That is,
it's possible for an insn with a latency of 1 and cost of 10 to be
replaced by an insn with a latency of 2 and cost of 3.
The insn cost is the cost of every insn which can be specified
elsewhere. These override the values in the vector cost model for vector
insns? Where are these specified?
Then, all of these combined form a tune model like generic-ooo or rocket.
> However, this is of course not desirable and we will soon have a
> reasonable vector cost model that corresponds to the non-uarch
> specific properties of the vector spec. Once this is in place
> we will also want a somewhat generic vector scheduler description
> that goes hand in hand with that. Despite the name, the vector
> part of generic-ooo could be used for in-order vector uarchs and
> we might want to define a different description for out-of-order
> uarchs. That's a separate discussion but at least for that
> contingency it would make sense to easily interchange the scheduler
> description ;)
>
I think I understand everything. I'm currently testing a run with a
generic-vector-ooo file and I'm a little unsure how we would create a
second generic-vector-in-order file such that each insn maps only to one
reservation without using tune attributes but I guess that will be an
implementation detail for later :)
Edwin
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations
2024-01-10 22:39 ` Edwin Lu
@ 2024-01-10 22:39 ` Edwin Lu
0 siblings, 0 replies; 11+ messages in thread
From: Edwin Lu @ 2024-01-10 22:39 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain
>> Since all the pipelines should be tuned to their cost model, they
>> would be different anyway. If it would be simpler for now, I could
>> separate the files out.
>> I think I'm getting a bit confused. Is there a reason why we would
>> want to exchange scheduler descriptions like the example you
>> provided? I'm just thinking why a in-order model would want to use an
>> ooo vector model and vice versa. Please correct me if I got the wrong
>> idea.
>
> Yeah, the confusion is understandable as it's all in flow and several
> things I mentioned are artifacts of us not yet being stabilized (or
> actually having hard data to base our decisions on).
>
> Usually, once a uarch has settled there is no reason to exchange
> anything, just smaller tweaks might be done. I was more thinking of
> the near to mid-term future where larger changes like ripping out
> one thing and using another one altogether might still happen.
>
> Regarding out of order vs in order - for in-order pipelines we will
> always want to get latencies right. For out of order it is a balancing
> act (proper latencies often mean more spilling and the processor will
> reorder correctly anyway).
>
> So you're mostly right that the argument is not very strong as soon
> as we really know what to do and not to do.
>
That makes sense to me!
>> I also want to double check, isn't forcing all typed instructions to
>> be part of a dfa pipeline in effect removing a situation where a tune
>> model does not specify a "vector tune model"? At least from my
>> testing with the assert statement, I get ICEs when trying to run the
>> testsuite without the vector tune model even on gc.
>
> There are (at least) three parts of the "tune model":
> - vector cost model, specifying the cost of generic vector operations,
> not necessarily corresponding to an insn
> - insn cost, specifying the cost of an individual insn, usually close
> to latency but sometimes also "complexity" or other things.
> - insn latency and other hardware scheduler properties.
>
> We can leave out any of those which will make us fall back to default
> values. Even if we forced a scheduler description we could still have
> the default fallback for the other two and generate unfavorable code
> as a result.
>
So if I'm understanding things correctly, the costs the Juzhe is working
on in riscv.cc would be part of the vector cost model since they don't
correspond to individual instructions and only target vector code. These
costs would be the default fallback in the event of having no scheduler
descriptions for the insn.
The vector pipelines I'm working describes the insn latency categorized
by the insn type. The scheduler will attempt to generate favorable code
by this description but also consider the vector cost model. That is,
it's possible for an insn with a latency of 1 and cost of 10 to be
replaced by an insn with a latency of 2 and cost of 3.
The insn cost is the cost of every insn which can be specified
elsewhere. These override the values in the vector cost model for vector
insns? Where are these specified?
Then, all of these combined form a tune model like generic-ooo or rocket.
> However, this is of course not desirable and we will soon have a
> reasonable vector cost model that corresponds to the non-uarch
> specific properties of the vector spec. Once this is in place
> we will also want a somewhat generic vector scheduler description
> that goes hand in hand with that. Despite the name, the vector
> part of generic-ooo could be used for in-order vector uarchs and
> we might want to define a different description for out-of-order
> uarchs. That's a separate discussion but at least for that
> contingency it would make sense to easily interchange the scheduler
> description ;)
>
I think I understand everything. I'm currently testing a run with a
generic-vector-ooo file and I'm a little unsure how we would create a
second generic-vector-in-order file such that each insn maps only to one
reservation without using tune attributes but I guess that will be an
implementation detail for later :)
Edwin
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2024-01-10 22:39 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-10 1:31 [PATCH V2 0/4][RFC] RISC-V: Associate typed insns to dfa reservation Edwin Lu
2024-01-10 1:31 ` [PATCH V2 1/4][RFC] RISC-V: Add non-vector types to dfa pipelines Edwin Lu
2024-01-10 1:31 ` [PATCH V2 2/4][RFC] RISC-V: Add vector related reservations Edwin Lu
2024-01-10 16:00 ` Robin Dapp
2024-01-10 18:24 ` Edwin Lu
2024-01-10 18:24 ` Edwin Lu
2024-01-10 19:16 ` Robin Dapp
2024-01-10 22:39 ` Edwin Lu
2024-01-10 22:39 ` Edwin Lu
2024-01-10 1:31 ` [PATCH V2 3/4][RFC] RISC-V: Use default cost model for insn scheduling for tests affected in PR113249 Edwin Lu
2024-01-10 1:31 ` [PATCH V2 4/4][RFC] RISC-V: Enable assert for insn_has_dfa_reservation Edwin Lu
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).