From: Kito Cheng <kito.cheng@sifive.com>
To: rep.dot.nop@gmail.com, jeffreyalaw@gmail.com,
rdapp.gcc@gmail.com, juzhe.zhong@rivai.ai,
gcc-patches@gcc.gnu.org
Cc: Kito Cheng <kito.cheng@sifive.com>
Subject: [PATCH] RISC-V: Tweak the wording for the sorry message
Date: Fri, 19 Jan 2024 10:34:57 +0800 [thread overview]
Message-ID: <20240119023457.1870618-1-kito.cheng@sifive.com> (raw)
Use "does not" rather than "cannot", because it's implementation issue.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_override_options_internal): Tweak
sorry message.
---
gcc/config/riscv/riscv.cc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f1d5129397f..dd6e68a08c2 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8798,13 +8798,13 @@ riscv_override_options_internal (struct gcc_options *opts)
We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
if (TARGET_MIN_VLEN_OPTS (opts) > 4096)
- sorry ("Current RISC-V GCC cannot support VLEN greater than 4096bit for "
+ sorry ("Current RISC-V GCC does not support VLEN greater than 4096bit for "
"'V' Extension");
/* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
big-endian after finishing full coverage testing. */
if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
- sorry ("Current RISC-V GCC cannot support RVV in big-endian mode");
+ sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
/* Convert -march to a chunks count. */
riscv_vector_chunks = riscv_convert_vector_bits (opts);
--
2.34.1
next reply other threads:[~2024-01-19 2:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-19 2:34 Kito Cheng [this message]
2024-01-19 2:35 ` juzhe.zhong
2024-01-19 2:41 ` Kito Cheng
2024-01-19 9:40 ` rep.dot.nop
2024-01-19 9:43 ` juzhe.zhong
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