From: Lulu Cheng <chenglulu@loongson.cn>
To: gcc-patches@gcc.gnu.org
Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn,
Lulu Cheng <chenglulu@loongson.cn>
Subject: [PATCH v5 4/5] LoongArch: Added support for loading __get_tls_addr symbol address using call36.
Date: Mon, 29 Jan 2024 16:22:00 +0800 [thread overview]
Message-ID: <20240129082201.26087-5-chenglulu@loongson.cn> (raw)
In-Reply-To: <20240129082201.26087-1-chenglulu@loongson.cn>
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
Add support for call36.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c: New test.
---
gcc/config/loongarch/loongarch.cc | 22 ++++++++++++++-----
...icit-relocs-medium-call36-auto-tls-ld-gd.c | 5 +++++
2 files changed, 21 insertions(+), 6 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 684ae81870c..564de9c2642 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -2807,17 +2807,27 @@ loongarch_call_tls_get_addr (rtx sym, enum loongarch_symbol_type type, rtx v0)
case CMODEL_MEDIUM:
{
- rtx reg = gen_reg_rtx (Pmode);
if (la_opt_explicit_relocs != EXPLICIT_RELOCS_NONE)
{
- emit_insn (gen_pcalau12i (Pmode, reg, loongarch_tls_symbol));
- rtx call = gen_call_value_internal_1 (Pmode, v0, reg,
- loongarch_tls_symbol,
- const0_rtx);
- insn = emit_call_insn (call);
+ rtx call;
+
+ if (HAVE_AS_SUPPORT_CALL36)
+ call = gen_call_value_internal (v0, loongarch_tls_symbol,
+ const0_rtx);
+ else
+ {
+ rtx reg = gen_reg_rtx (Pmode);
+ emit_insn (gen_pcalau12i (Pmode, reg,
+ loongarch_tls_symbol));
+ call = gen_call_value_internal_1 (Pmode, v0, reg,
+ loongarch_tls_symbol,
+ const0_rtx);
+ }
+ insn = emit_call_insn (call);
}
else
{
+ rtx reg = gen_reg_rtx (Pmode);
emit_move_insn (reg, loongarch_tls_symbol);
insn = emit_call_insn (gen_call_value_internal (v0,
reg,
diff --git a/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c
new file mode 100644
index 00000000000..d1a4820834c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/explicit-relocs-medium-call36-auto-tls-ld-gd.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -fPIC -mexplicit-relocs=auto -mcmodel=medium -fplt" } */
+/* { dg-final { scan-assembler "pcaddu18i\t\\\$r1,%call36\\\(__tls_get_addr\\\)" { target { tls_native && loongarch_call36_support } } } } */
+
+#include "./explicit-relocs-auto-tls-ld-gd.c"
--
2.39.3
next prev parent reply other threads:[~2024-01-29 8:22 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-29 8:21 [PATCH v5 0/5] When cmodel=extreme, add macro implementation and fix problems with explicit relos implementation Lulu Cheng
2024-01-29 8:21 ` [PATCH v5 1/5] LoongArch: Merge template got_load_tls_{ld/gd/le/ie} Lulu Cheng
2024-01-29 8:21 ` [PATCH v5 2/5] LoongArch: Add the macro implementation of mcmodel=extreme Lulu Cheng
2024-01-29 8:21 ` [PATCH v5 3/5] LoongArch: Enable explicit reloc for extreme TLS GD/LD with -mexplicit-relocs=auto Lulu Cheng
2024-01-29 8:22 ` Lulu Cheng [this message]
2024-01-29 8:22 ` [PATCH v5 5/5] LoongArch: Don't split the instructions containing relocs for extreme code model Lulu Cheng
2024-02-02 1:17 ` [pushed][PATCH v5 0/5] When cmodel=extreme, add macro implementation and fix problems with explicit relos implementation chenglulu
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