* [PATCH] RISC-V: Revert this weekend's changes
@ 2024-04-22 20:59 Palmer Dabbelt
0 siblings, 0 replies; only message in thread
From: Palmer Dabbelt @ 2024-04-22 20:59 UTC (permalink / raw)
To: gcc-patches; +Cc: Palmer Dabbelt
Looks like we had a bunch of commits over the weekend that didn't get
tested/reviewed. Some didn't even make it to the lists so it's hard to
tell exactly what happened, but the result was a trunk that doesn't even
build and a bunch of ICEs after some trivial fix ups landed on the
lists.
So let's just go back to what worked. We're bumping up right next to a
release, it's a really bad time to be breaking stuff this badly. It's
still not clear exactly what was broken here, so if something's wrong
then we should still fix it -- let's just at least build things until
GCC-14 branches.
gcc/ChangeLog:
* config/riscv/constraints.md (TARGET_VECTOR ? V_REGS :
NO_REGS): Revert to 90ded7512e1 ("Daily bump.").
* config/riscv/riscv.md (none,W21,W42,W84,W43,W86,W87,W0):
Likewise.
(no,W21,W42,W84,W41,W81,W82): Likewise.
(no,yes): Likewise.
* config/riscv/vector.md: Likewise.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c: Revert to
90ded7512e1 ("Daily bump.").
* gcc.target/riscv/rvv/base/pr112431-10.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-11.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-12.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-13.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-16.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-17.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-18.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-22.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-23.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-24.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-25.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-26.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-27.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-28.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-29.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-30.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-31.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-32.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-33.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-37.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-38.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-39.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-40.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-41.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-42.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-7.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-8.c: Likewise.
* gcc.target/riscv/rvv/base/pr112431-9.c: Likewise.
Fixes: cacc55a4c0b ("Revert "RISC-V: Rename vconstraint into group_overlap"")
Fixes: b78c88438cf ("Revert "RISC-V: Robostify the W43, W86, W87 constraint enabled attribute"")
Fixes: b991193eb8a ("RISC-V: Add xfail test case for highpart overlap floating-point widen insn")
Fixes: 4df96b4ec78 ("Revert "RISC-V: Support highpart overlap for floating-point widen instructions"")
Fixes: a367b99f916 ("RISC-V: Add xfail test case for indexed load overlap with SRC EEW < DEST EEW")
Fixes: 9257c7a7205 ("Revert "RISC-V: Support highpart overlap for indexed load with SRC EEW < DEST EEW"")
Fixes: c7506847c02 ("RISC-V: Add xfail test case for highest-number regno ternary overlap")
Fixes: cc46b6d4f3b ("Revert "RISC-V: Support highest-number regno overlap for widen ternary"")
Fixes: c4fdbdac122 ("RISC-V: Add xfail test case for widening register overlap of vf4/vf8")
Fixes: ec78916bb37 ("Revert "RISC-V: Support widening register overlap for vf4/vf8"")
Fixes: 338640fbee2 ("RISC-V: Add xfail test case for highpart register overlap of vx/vf widen")
Fixes: ef2392236ec ("Revert "RISC-V: Support highpart register overlap for widen vx/vf instructions"")
Fixes: d37b34fe82e ("RISC-V: Add xfail test case for incorrect overlap on v0")
Fixes: 3afcb04bd7d ("Revert "RISC-V: Fix overlap group incorrect overlap on v0"")
Fixes: 1690e47e101 ("RISC-V: Add xfail test case for wv insn highest overlap")
Fixes: f5447eae72f ("Revert "RISC-V: Support highest overlap for wv instructions"")
Fixes: 9f10005dbc9 ("RISC-V: Add xfail test case for wv insn register overlap")
Fixes: 0cbeafe2651 ("Revert "RISC-V: Support one more overlap for wv instructions"")
---
I haven't even built this one myself so I'm definately not going to
commit it, but I figured it'd be best to get something on the lists as
we're pretty broken. If someone has a patch stack that gets things
building and fixes the ICEs then I'm happy to look at that, but it's not
even clear what we were trying to fix in the first place.
Either way, I think we've found a pretty major issue with our
development process here.
---
gcc/config/riscv/constraints.md | 12 +-
gcc/config/riscv/riscv.md | 40 +-
gcc/config/riscv/vector.md | 483 +++++++++---------
.../costmodel/riscv/rvv/dynamic-lmul8-11.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-10.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-11.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-12.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-13.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-16.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-17.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-18.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-22.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-23.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-24.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-25.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-26.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-27.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-28.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-29.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-30.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-31.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-32.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-33.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-37.c | 6 +-
.../gcc.target/riscv/rvv/base/pr112431-38.c | 8 +-
.../gcc.target/riscv/rvv/base/pr112431-39.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-40.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-41.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-42.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-7.c | 4 +-
.../gcc.target/riscv/rvv/base/pr112431-8.c | 2 +-
.../gcc.target/riscv/rvv/base/pr112431-9.c | 2 +-
32 files changed, 326 insertions(+), 279 deletions(-)
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index e37c6936bfa..972e8842c9f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -173,14 +173,14 @@ (define_register_constraint "W42" "TARGET_VECTOR ? V_REGS : NO_REGS"
(define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS"
"A vector register has register number % 8 == 4." "regno % 8 == 4")
-(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS"
- "A vector register has register number % 4 == 1." "regno % 4 == 1")
+(define_register_constraint "W43" "TARGET_VECTOR ? V_REGS : NO_REGS"
+ "A vector register has register number % 4 == 3." "regno % 4 == 3")
-(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS"
- "A vector register has register number % 8 == 1." "regno % 8 == 1")
+(define_register_constraint "W86" "TARGET_VECTOR ? V_REGS : NO_REGS"
+ "A vector register has register number % 8 == 6." "regno % 8 == 6")
-(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS"
- "A vector register has register number % 8 == 2." "regno % 8 == 2")
+(define_register_constraint "W87" "TARGET_VECTOR ? V_REGS : NO_REGS"
+ "A vector register has register number % 8 == 7." "regno % 8 == 7")
;; This constraint is used to match instruction "csrr %0, vlenb" which is generated in "mov<mode>".
;; VLENB is a run-time constant which represent the vector register length in bytes.
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 1693d4008c6..c2b4323c53a 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -538,24 +538,48 @@ (define_attr "fp_vector_disabled" "no,yes"
]
(const_string "no")))
-(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82"
- (const_string "no"))
+;; Widening instructions have group-overlap constraints. Those are only
+;; valid for certain register-group sizes. This attribute marks the
+;; alternatives not matching the required register-group size as disabled.
+(define_attr "group_overlap" "none,W21,W42,W84,W43,W86,W87,W0"
+ (const_string "none"))
-(define_attr "vconstraint_enabled" "no,yes"
- (cond [(eq_attr "vconstraint" "no")
+(define_attr "group_overlap_valid" "no,yes"
+ (cond [(eq_attr "group_overlap" "none")
(const_string "yes")
- (and (eq_attr "vconstraint" "W21")
+ (and (eq_attr "group_overlap" "W21")
(match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 2"))
(const_string "no")
- (and (eq_attr "vconstraint" "W42,W41")
+ (and (eq_attr "group_overlap" "W42")
(match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4"))
(const_string "no")
- (and (eq_attr "vconstraint" "W84,W81,W82")
+ (and (eq_attr "group_overlap" "W84")
(match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8"))
(const_string "no")
+
+ ;; According to RVV ISA:
+ ;; The destination EEW is greater than the source EEW, the source EMUL is at least 1,
+ ;; and the overlap is in the highest-numbered part of the destination register group
+ ;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or v4 is not).
+ ;; So the source operand should have LMUL >= 1.
+ (and (eq_attr "group_overlap" "W43")
+ (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 4
+ && riscv_get_v_regno_alignment (GET_MODE (operands[3])) >= 1"))
+ (const_string "no")
+
+ (and (eq_attr "group_overlap" "W86,W87")
+ (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != 8
+ && riscv_get_v_regno_alignment (GET_MODE (operands[3])) >= 1"))
+ (const_string "no")
+
+ ;; W21 supports highest-number overlap for source LMUL = 1.
+ ;; For 'wv' variant, we can also allow wide source operand overlaps dest operand.
+ (and (eq_attr "group_overlap" "W0")
+ (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) > 1"))
+ (const_string "no")
]
(const_string "yes")))
@@ -587,7 +611,7 @@ (define_attr "enabled" "no,yes"
(eq_attr "fp_vector_disabled" "yes")
(const_string "no")
- (eq_attr "vconstraint_enabled" "no")
+ (eq_attr "group_overlap_valid" "no")
(const_string "no")
(eq_attr "spec_restriction_disabled" "yes")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index cb5174a5e91..8b1c24c5d79 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -2254,67 +2254,70 @@ (define_insn "@pred_indexed_<order>load<mode>_same_eew"
;; DEST eew is greater than SOURCE eew.
(define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew"
- [(set (match_operand:VEEWEXT2 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VEEWEXT2 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VEEWEXT2
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:VEEWEXT2
- [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
+ [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")
(mem:BLK (scratch))
- (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
- (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")] ORDER)
+ (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vl<order>xei<double_trunc_sew>.v\t%0,(%z3),%4%p1"
[(set_attr "type" "vld<order>x")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
(define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew"
- [(set (match_operand:VEEWEXT4 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VEEWEXT4 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VEEWEXT4
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:VEEWEXT4
- [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
+ [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")
(mem:BLK (scratch))
- (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
- (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr")] ORDER)
+ (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vl<order>xei<quad_trunc_sew>.v\t%0,(%z3),%4%p1"
[(set_attr "type" "vld<order>x")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")])
(define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew"
- [(set (match_operand:VEEWEXT8 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VEEWEXT8 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VEEWEXT8
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(unspec:VEEWEXT8
- [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
+ [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
(mem:BLK (scratch))
- (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
- (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" "W87,W87,W87,W87, vr, vr")] ORDER)
+ (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vl<order>xei<oct_trunc_sew>.v\t%0,(%z3),%4%p1"
[(set_attr "type" "vld<order>x")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "group_overlap" "W87,W87,W87,W87,none,none")])
;; DEST eew is smaller than SOURCE eew.
(define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew"
@@ -3730,64 +3733,66 @@ (define_insn "@pred_<optab><mode>"
;; Vector Double-Widening Sign-extend and Zero-extend.
(define_insn "@pred_<optab><mode>_vf2"
- [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
- (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
+ (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"v<sz>ext.vf2\t%0,%3%p1"
[(set_attr "type" "vext")
(set_attr "mode" "<MODE>")
- (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")])
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
;; Vector Quad-Widening Sign-extend and Zero-extend.
(define_insn "@pred_<optab><mode>_vf4"
- [(set (match_operand:VQEXTI 0 "register_operand" "=&vr,&vr")
+ [(set (match_operand:VQEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VQEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_extend:VQEXTI
- (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<V_QUAD_TRUNC> 3 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr"))
+ (match_operand:VQEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"v<sz>ext.vf4\t%0,%3%p1"
[(set_attr "type" "vext")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")])
;; Vector Oct-Widening Sign-extend and Zero-extend.
(define_insn "@pred_<optab><mode>_vf8"
- [(set (match_operand:VOEXTI 0 "register_operand" "=&vr,&vr")
+ [(set (match_operand:VOEXTI 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VOEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_extend:VOEXTI
- (match_operand:<V_OCT_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<V_OCT_TRUNC> 3 "register_operand" "W87,W87,W87,W87, vr, vr"))
+ (match_operand:VOEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"v<sz>ext.vf8\t%0,%3%p1"
[(set_attr "type" "vext")
- (set_attr "mode" "<MODE>")])
+ (set_attr "mode" "<MODE>")
+ (set_attr "group_overlap" "W87,W87,W87,W87,none,none")])
;; Vector Widening Add/Subtract/Multiply.
(define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
@@ -3813,69 +3818,72 @@ (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
(define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
- [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_widen_binop:VWEXTI
(any_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
(any_extend:VWEXTI
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
- (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ"))))
+ (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
[(set_attr "type" "vi<widen_binop_insn_type>")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
(define_insn "@pred_single_widen_sub<any_extend:su><mode>"
- [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(minus:VWEXTI
- (match_operand:VWEXTI 3 "register_operand" " vr, vr")
+ (match_operand:VWEXTI 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr")
(any_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
- (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr")))
+ (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
[(set_attr "type" "viwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
(define_insn "@pred_single_widen_add<any_extend:su><mode>"
- [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus:VWEXTI
(any_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
- (match_operand:VWEXTI 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr"))
+ (match_operand:VWEXTI 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr"))
+ (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
[(set_attr "type" "viwalu")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
(define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
[(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
@@ -3922,46 +3930,47 @@ (define_insn "@pred_widen_mulsu<mode>"
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
(define_insn "@pred_widen_mulsu<mode>_scalar"
- [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(mult:VWEXTI
(sign_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
(zero_extend:VWEXTI
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
- (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ"))))
+ (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vwmulsu.vx\t%0,%3,%z4%p1"
[(set_attr "type" "viwmul")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
;; vwcvt<u>.x.x.v
(define_insn "@pred_<optab><mode>"
- [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
- (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
- (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
- (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus:VWEXTI
(any_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
(vec_duplicate:VWEXTI
(reg:<VEL> X0_REGNUM)))
- (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
+ (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vwcvt<u>.x.x.v\t%0,%3%p1"
[(set_attr "type" "viwalu")
@@ -3970,7 +3979,7 @@ (define_insn "@pred_<optab><mode>"
(set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
(set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
(set (attr "avl_type_idx") (const_int 7))
- (set_attr "vconstraint" "W21,W21,W42,W42,W84,W84,no,no")])
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
;; -------------------------------------------------------------------------------
;; ---- Predicated integer Narrowing operations
@@ -5927,29 +5936,30 @@ (define_insn "@pred_widen_mul_plus<su><mode>"
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
(define_insn "@pred_widen_mul_plus<su><mode>_scalar"
- [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (match_operand 8 "const_int_operand" " i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus:VWEXTI
(mult:VWEXTI
(any_extend:VWEXTI
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 3 "register_operand" " r")))
+ (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
(any_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
- (match_operand:VWEXTI 2 "register_operand" " 0"))
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
+ (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
(match_dup 2)))]
"TARGET_VECTOR"
- "vwmacc<u>.vx\t%0,%3,%4%p1"
+ "vwmacc<u>.vx\t%0,%z3,%4%p1"
[(set_attr "type" "viwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
(define_insn "@pred_widen_mul_plussu<mode>"
[(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
@@ -5976,54 +5986,56 @@ (define_insn "@pred_widen_mul_plussu<mode>"
(set_attr "mode" "<V_DOUBLE_TRUNC>")])
(define_insn "@pred_widen_mul_plussu<mode>_scalar"
- [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (match_operand 8 "const_int_operand" " i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus:VWEXTI
(mult:VWEXTI
(sign_extend:VWEXTI
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 3 "register_operand" " r")))
+ (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
(zero_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
- (match_operand:VWEXTI 2 "register_operand" " 0"))
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
+ (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
(match_dup 2)))]
"TARGET_VECTOR"
- "vwmaccsu.vx\t%0,%3,%4%p1"
+ "vwmaccsu.vx\t%0,%z3,%4%p1"
[(set_attr "type" "viwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
(define_insn "@pred_widen_mul_plusus<mode>_scalar"
- [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
+ [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
(if_then_else:VWEXTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (match_operand 8 "const_int_operand" " i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(plus:VWEXTI
(mult:VWEXTI
(zero_extend:VWEXTI
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 3 "register_operand" " r")))
+ (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
(sign_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
- (match_operand:VWEXTI 2 "register_operand" " 0"))
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
+ (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
(match_dup 2)))]
"TARGET_VECTOR"
- "vwmaccus.vx\t%0,%3,%4%p1"
+ "vwmaccus.vx\t%0,%z3,%4%p1"
[(set_attr "type" "viwmuladd")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
;; -------------------------------------------------------------------------------
;; ---- Predicated BOOL mask operations
@@ -7103,81 +7115,84 @@ (define_insn "@pred_dual_widen_<optab><mode>"
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_dual_widen_<optab><mode>_scalar"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VWEXTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (match_operand 9 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 9 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(any_widen_binop:VWEXTF
(float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
(float_extend:VWEXTF
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f, f, f, f, f, f, f, f, f, f, f"))))
+ (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vfw<insn>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
(define_insn "@pred_single_widen_add<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
(if_then_else:VWEXTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (match_operand 9 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus:VWEXTF
(float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr"))
+ (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr"))
+ (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfwadd.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
(define_insn "@pred_single_widen_sub<mode>"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
(if_then_else:VWEXTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 5 "vector_length_operand" " rK, rK")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
- (match_operand 9 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(minus:VWEXTF
- (match_operand:VWEXTF 3 "register_operand" " vr, vr")
+ (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr")
(float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
- (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr")))
+ (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfwsub.wv\t%0,%3,%4%p1"
[(set_attr "type" "vfwalu")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr")
@@ -7241,15 +7256,15 @@ (define_insn "@pred_widen_mul_<optab><mode>"
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_<optab><mode>_scalar"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
+ [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
(if_then_else:VWEXTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (match_operand 8 "const_int_operand" " i")
- (match_operand 9 "const_int_operand" " i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
@@ -7257,17 +7272,18 @@ (define_insn "@pred_widen_mul_<optab><mode>_scalar"
(mult:VWEXTF
(float_extend:VWEXTF
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 3 "register_operand" " f")))
+ (match_operand:<VSUBEL> 3 "register_operand" " f, f, f, f, f, f, f")))
(float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
- (match_operand:VWEXTF 2 "register_operand" " 0"))
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
+ (match_operand:VWEXTF 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
(match_dup 2)))]
"TARGET_VECTOR"
"vfw<macc_msac>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
+ (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
(define_insn "@pred_widen_mul_neg_<optab><mode>"
[(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
@@ -7299,15 +7315,15 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>"
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
- [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
+ [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
(if_then_else:VWEXTF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
- (match_operand 5 "vector_length_operand" " rK")
- (match_operand 6 "const_int_operand" " i")
- (match_operand 7 "const_int_operand" " i")
- (match_operand 8 "const_int_operand" " i")
- (match_operand 9 "const_int_operand" " i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
+ (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
+ (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
@@ -7316,17 +7332,18 @@ (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
(mult:VWEXTF
(float_extend:VWEXTF
(vec_duplicate:<V_DOUBLE_TRUNC>
- (match_operand:<VSUBEL> 3 "register_operand" " f")))
+ (match_operand:<VSUBEL> 3 "register_operand" " f, f, f, f, f, f, f")))
(float_extend:VWEXTF
- (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
- (match_operand:VWEXTF 2 "register_operand" " 0"))
+ (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))))
+ (match_operand:VWEXTF 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
(match_dup 2)))]
"TARGET_VECTOR"
"vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
[(set_attr "type" "vfwmuladd")
(set_attr "mode" "<V_DOUBLE_TRUNC>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
+ (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point comparison operations
@@ -7696,84 +7713,88 @@ (define_insn "@pred_<float_cvt><mode>"
;; -------------------------------------------------------------------------------
(define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
- [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VWCONVERTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VWCONVERTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
- (match_operand 8 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(unspec:VWCONVERTI
- [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
- (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
+ [(match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")] VFCVTS)
+ (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.x<v_su>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
(set_attr "mode" "<VNCONVERT>")
(set (attr "frm_mode")
- (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
+ (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
(define_insn "@pred_widen_<fix_cvt><mode>"
- [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VWCONVERTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VWCONVERTI
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_fix:VWCONVERTI
- (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
- (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
+ (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftoi")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
(define_insn "@pred_widen_<float_cvt><mode>"
- [(set (match_operand:V_VLSF 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:V_VLSF
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(any_float:V_VLSF
- (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
- (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
+ (match_operand:V_VLSF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.x<u>.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtitof")
- (set_attr "mode" "<VNCONVERT>")])
+ (set_attr "mode" "<VNCONVERT>")
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
(define_insn "@pred_extend<mode>"
- [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=&vr, &vr")
+ [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
(if_then_else:VWEXTF_ZVFHMIN
(unspec:<VM>
- [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
- (match_operand 4 "vector_length_operand" " rK, rK")
- (match_operand 5 "const_int_operand" " i, i")
- (match_operand 6 "const_int_operand" " i, i")
- (match_operand 7 "const_int_operand" " i, i")
+ [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
+ (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
+ (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
+ (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
(float_extend:VWEXTF_ZVFHMIN
- (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
- (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0")))]
+ (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
+ (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
"TARGET_VECTOR"
"vfwcvt.f.f.v\t%0,%3%p1"
[(set_attr "type" "vfwcvtftof")
- (set_attr "mode" "<V_DOUBLE_TRUNC>")])
+ (set_attr "mode" "<V_DOUBLE_TRUNC>")
+ (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
;; -------------------------------------------------------------------------------
;; ---- Predicated floating-point narrow conversions
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
index 5a39f04b140..c9e28251225 100644
--- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
+++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul8-11.c
@@ -40,7 +40,7 @@ void foo2 (int64_t *__restrict a,
}
/* { dg-final { scan-assembler {e64,m8} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
/* { dg-final { scan-tree-dump-not "Preferring smaller LMUL loop because it has unexpected spills" "vect" } } */
/* { dg-final { scan-tree-dump-times "Maximum lmul = 8" 1 "vect" } } */
/* { dg-final { scan-tree-dump-times "Maximum lmul = 4" 1 "vect" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c
index 5d3f2fbe46d..5f161b31fa1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c
@@ -101,4 +101,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c
index 6a2301b523f..82827d14e34 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c
@@ -65,4 +65,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c
index 0f3eb4d58de..c4ae60755ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c
index 71786995c56..fde7076d34f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c
@@ -185,4 +185,4 @@ foo2 (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
index 42d11611d98..98f42458883 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c
@@ -65,4 +65,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
index 9ecc62e234b..9b60005344d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c
index 4365fe0af54..dd65b2fa098 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c
index ac56703c75c..90db18217bb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-22.c
@@ -185,4 +185,4 @@ foo2 (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-23.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-23.c
index f91119307f4..ee0b928e9df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-23.c
@@ -116,4 +116,4 @@ foo2 (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-24.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-24.c
index bcd60c0a7c3..603e2941cd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-24.c
@@ -83,4 +83,4 @@ foo2 (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-25.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-25.c
index 57a8ef28486..0b52b9f24eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-25.c
@@ -101,4 +101,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-26.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-26.c
index 0f05e2b2e1d..d21a73765ed 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-26.c
@@ -65,4 +65,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-27.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-27.c
index d640bcf74ba..2423f7b33ee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-27.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-28.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-28.c
index c16cbdfe9f9..d81afd2610f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-28.c
@@ -101,4 +101,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-29.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-29.c
index cee6afafe87..2f8adb8ebee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-29.c
@@ -65,4 +65,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-30.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-30.c
index f2e23628022..d3ce98852db 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-30.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-31.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-31.c
index 2cf006bd4c9..72b928a579b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-31.c
@@ -65,4 +65,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-32.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-32.c
index 284b7a2891c..273c5fca642 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-32.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-33.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-33.c
index 82baf0fadb3..a5c2ad1de62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-33.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
index 66e81ea905a..6337ff875fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-37.c
@@ -97,7 +97,7 @@ foo9 (void *in, void *out)
}
/* { dg-final { scan-assembler-not {vmv1r} } } */
-/* { dg-final { scan-assembler-not {vmv2r} { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-not {vmv8r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c
index a0cf9afc88e..7b7d6cc7e98 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-38.c
@@ -75,8 +75,8 @@ foo6 (void *in, void *out)
__riscv_vse64_v_f64m8 (out, result, 4);
}
-/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-not {vmv2r} { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
-/* { dg-final { scan-assembler-not {vmv8r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv1r} } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c
index 770b5411666..47820dd29f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-39.c
@@ -152,7 +152,7 @@ foo2 (void *in, void *out, int n)
}
/* { dg-final { scan-assembler-not {vmv1r} } } */
-/* { dg-final { scan-assembler-not {vmv2r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c
index f044a504fc8..e44b8010579 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-40.c
@@ -89,6 +89,6 @@ foo2 (void *in, void *out, int n)
/* { dg-final { scan-assembler-not {vmv1r} } } */
/* { dg-final { scan-assembler-not {vmv2r} } } */
-/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c
index 6bdcac82ea8..dc27006f6f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-41.c
@@ -58,5 +58,5 @@ foo2 (void *in, void *out, int n)
/* { dg-final { scan-assembler-not {vmv1r} } } */
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
-/* { dg-final { scan-assembler-not {vmv8r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv8r} } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
index fa5dac58a20..1ee5b20a899 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-42.c
@@ -21,7 +21,7 @@ reduc_plus_float (float *__restrict a, int n)
return r;
}
-/* { dg-final { scan-assembler-not {vmv1r} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {vmv1r} } } */
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c
index 59cbd7ff4be..7064471496c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c
@@ -101,4 +101,6 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
+
+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c
index 3a8ca02bd21..ab56d0d69af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c
@@ -65,4 +65,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c
index 88ab1d9da5c..82f369c0cd9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c
@@ -48,4 +48,4 @@ foo (char const *buf, size_t len)
/* { dg-final { scan-assembler-not {vmv2r} } } */
/* { dg-final { scan-assembler-not {vmv4r} } } */
/* { dg-final { scan-assembler-not {vmv8r} } } */
-/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */
+/* { dg-final { scan-assembler-not {csrr} } } */
--
2.44.0
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