From: Jeff Law <jeffreyalaw@gmail.com>
To: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
gcc-patches <gcc-patches@gcc.gnu.org>
Cc: jinma <jinma@linux.alibaba.com>,
"Kito.cheng" <Kito.cheng@sifive.com>,
palmer <palmer@rivosinc.com>
Subject: Re: FW: [RFC] RISC-V: Support risc-v bfloat16 This patch support bfloat16 in riscv like x86_64 and arm.
Date: Thu, 1 Jun 2023 10:48:47 -0600 [thread overview]
Message-ID: <2eebb749-c837-1cb4-e3ca-c0d24dfae4a1@gmail.com> (raw)
In-Reply-To: <FE2C77BD90448D1A+2023060115010849316338@rivai.ai>
On 6/1/23 01:01, juzhe.zhong@rivai.ai wrote:
> I plan to implement BF16 vector in GCC but still waiting for ISA
> ratified since GCC policy doesn't allow un-ratified ISA.
Right. So those specs need to move along further before we can start
integrating code.
>
> Currently, we are working on INT8,INT16,INT32,INT64,FP16,FP32,FP64
> auto-vectorizaiton.
> It should very simple BF16 in current vector framework in GCC.
In prior architectures I've worked on the bulk of BF16 work was just
adding additional entries to existing iterators. So I agree, it should
be very simple :-)
Jeff
next prev parent reply other threads:[~2023-06-01 16:48 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-07 9:12 Liao Shihua
2023-04-25 13:23 ` Kito Cheng
2023-06-01 6:51 ` Jin Ma
[not found] ` <MW5PR11MB59081DA700F563D0DD24161FA9499@MW5PR11MB5908.namprd11.prod.outlook.com>
2023-06-01 7:01 ` FW: " juzhe.zhong
2023-06-01 16:48 ` Jeff Law [this message]
2023-06-01 16:56 ` Palmer Dabbelt
2023-06-01 17:53 ` Jeff Law
2023-06-01 16:59 ` Philipp Tomsich
2023-06-01 9:07 ` Liao Shihua
2023-06-15 7:51 ` Jin Ma
2023-06-15 9:52 ` Jin Ma
2023-06-17 15:31 ` Jeff Law
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