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* [PATCH] RISC-V: Use dominance analysis in global vsetvl elimination
@ 2023-09-11  3:33 Juzhe-Zhong
  2023-09-11  7:03 ` Kito Cheng
  0 siblings, 1 reply; 3+ messages in thread
From: Juzhe-Zhong @ 2023-09-11  3:33 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, kito.cheng, jeffreyalaw, rdapp.gcc, Juzhe-Zhong

I found that it's more reasonable to use existing dominance analysis.

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Use dominance analysis.
	(pass_vsetvl::init): Ditto.
	(pass_vsetvl::done): Ditto.

---
 gcc/config/riscv/riscv-vsetvl.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 134b97737ae..f81361c4ccd 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -4054,7 +4054,7 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const
     }
 
   /* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  */
-  hash_set<basic_block> pred_cfg_bbs = get_all_predecessors (cfg_bb);
+  auto_vec<basic_block> pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
   FOR_EACH_EDGE (e, ei, cfg_bb->preds)
     {
       sbitmap avout = m_vector_manager->vector_avout[e->src->index];
@@ -4243,6 +4243,7 @@ pass_vsetvl::init (void)
     {
       /* Initialization of RTL_SSA.  */
       calculate_dominance_info (CDI_DOMINATORS);
+      calculate_dominance_info (CDI_POST_DOMINATORS);
       df_analyze ();
       crtl->ssa = new function_info (cfun);
     }
@@ -4264,6 +4265,7 @@ pass_vsetvl::done (void)
     {
       /* Finalization of RTL_SSA.  */
       free_dominance_info (CDI_DOMINATORS);
+      free_dominance_info (CDI_POST_DOMINATORS);
       if (crtl->ssa->perform_pending_updates ())
 	cleanup_cfg (0);
       delete crtl->ssa;
-- 
2.36.3


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH] RISC-V: Use dominance analysis in global vsetvl elimination
  2023-09-11  3:33 [PATCH] RISC-V: Use dominance analysis in global vsetvl elimination Juzhe-Zhong
@ 2023-09-11  7:03 ` Kito Cheng
  2023-09-11  7:42   ` juzhe.zhong
  0 siblings, 1 reply; 3+ messages in thread
From: Kito Cheng @ 2023-09-11  7:03 UTC (permalink / raw)
  To: Juzhe-Zhong; +Cc: gcc-patches, kito.cheng

LGTM, and I guess you will remove get_all_predecessors once LMUL cost
model can use dominator info as well?


On Mon, Sep 11, 2023 at 11:34 AM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> I found that it's more reasonable to use existing dominance analysis.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Use dominance analysis.
>         (pass_vsetvl::init): Ditto.
>         (pass_vsetvl::done): Ditto.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 134b97737ae..f81361c4ccd 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -4054,7 +4054,7 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const
>      }
>
>    /* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  */
> -  hash_set<basic_block> pred_cfg_bbs = get_all_predecessors (cfg_bb);
> +  auto_vec<basic_block> pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
>    FOR_EACH_EDGE (e, ei, cfg_bb->preds)
>      {
>        sbitmap avout = m_vector_manager->vector_avout[e->src->index];
> @@ -4243,6 +4243,7 @@ pass_vsetvl::init (void)
>      {
>        /* Initialization of RTL_SSA.  */
>        calculate_dominance_info (CDI_DOMINATORS);
> +      calculate_dominance_info (CDI_POST_DOMINATORS);
>        df_analyze ();
>        crtl->ssa = new function_info (cfun);
>      }
> @@ -4264,6 +4265,7 @@ pass_vsetvl::done (void)
>      {
>        /* Finalization of RTL_SSA.  */
>        free_dominance_info (CDI_DOMINATORS);
> +      free_dominance_info (CDI_POST_DOMINATORS);
>        if (crtl->ssa->perform_pending_updates ())
>         cleanup_cfg (0);
>        delete crtl->ssa;
> --
> 2.36.3
>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: Re: [PATCH] RISC-V: Use dominance analysis in global vsetvl elimination
  2023-09-11  7:03 ` Kito Cheng
@ 2023-09-11  7:42   ` juzhe.zhong
  0 siblings, 0 replies; 3+ messages in thread
From: juzhe.zhong @ 2023-09-11  7:42 UTC (permalink / raw)
  To: kito.cheng; +Cc: gcc-patches, Kito.cheng

[-- Attachment #1: Type: text/plain, Size: 2349 bytes --]

Committed. Thanks kito.


>> I guess you will remove get_all_predecessors once LMUL cost
>> model can use dominator info as well?
Yes. I am trying but there is a failed case for dynamic LMUL.
Not sure whether it can work now.



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-09-11 15:03
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng
Subject: Re: [PATCH] RISC-V: Use dominance analysis in global vsetvl elimination
LGTM, and I guess you will remove get_all_predecessors once LMUL cost
model can use dominator info as well?
 
 
On Mon, Sep 11, 2023 at 11:34 AM Juzhe-Zhong <juzhe.zhong@rivai.ai> wrote:
>
> I found that it's more reasonable to use existing dominance analysis.
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv-vsetvl.cc (pass_vsetvl::global_eliminate_vsetvl_insn): Use dominance analysis.
>         (pass_vsetvl::init): Ditto.
>         (pass_vsetvl::done): Ditto.
>
> ---
>  gcc/config/riscv/riscv-vsetvl.cc | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
> index 134b97737ae..f81361c4ccd 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -4054,7 +4054,7 @@ pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const
>      }
>
>    /* Step1: Reshape the VL/VTYPE status to make sure everything compatible.  */
> -  hash_set<basic_block> pred_cfg_bbs = get_all_predecessors (cfg_bb);
> +  auto_vec<basic_block> pred_cfg_bbs = get_dominated_by (CDI_POST_DOMINATORS, cfg_bb);
>    FOR_EACH_EDGE (e, ei, cfg_bb->preds)
>      {
>        sbitmap avout = m_vector_manager->vector_avout[e->src->index];
> @@ -4243,6 +4243,7 @@ pass_vsetvl::init (void)
>      {
>        /* Initialization of RTL_SSA.  */
>        calculate_dominance_info (CDI_DOMINATORS);
> +      calculate_dominance_info (CDI_POST_DOMINATORS);
>        df_analyze ();
>        crtl->ssa = new function_info (cfun);
>      }
> @@ -4264,6 +4265,7 @@ pass_vsetvl::done (void)
>      {
>        /* Finalization of RTL_SSA.  */
>        free_dominance_info (CDI_DOMINATORS);
> +      free_dominance_info (CDI_POST_DOMINATORS);
>        if (crtl->ssa->perform_pending_updates ())
>         cleanup_cfg (0);
>        delete crtl->ssa;
> --
> 2.36.3
>
 

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2023-09-11  7:42 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2023-09-11  3:33 [PATCH] RISC-V: Use dominance analysis in global vsetvl elimination Juzhe-Zhong
2023-09-11  7:03 ` Kito Cheng
2023-09-11  7:42   ` juzhe.zhong

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