[RISC-V] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis

[RISC-V] Fix incorrect if-then-else nesting of Zbs usage in constant synthesis

[Jeff Law]

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So I managed to goof the if-then-else level of the bseti bits last week. 
  They were supposed to be a last ditch effort to improve the result, 
but ended up inside a conditional where they don't really belong.  I 
almost always use Zba, Zbb and Zbs together, so it slipped by.

So it's NFC if you always test with Zbb and Zbs enabled together.  But 
if you enabled Zbs without Zbb you'd see a failure to use bseti.

Planning to commit once pre-commit CI passes.

I'm attaching the actual patch (P) and a diff with whitespace ignored 
(P2) so it's easier to see what actually changed.

Jeff

[-- Attachment #2: P --]
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diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6f1c67bf3f7..dddb7f8d673 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -869,50 +869,51 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
 	  codes[1].use_uw = false;
 	  cost = 2;
 	}
-      /* Final cases, particularly focused on bseti.  */
-      else if (cost > 2 && TARGET_ZBS)
-	{
-	  int i = 0;
+    }
 
-	  /* First handle any bits set by LUI.  Be careful of the
-	     SImode sign bit!.  */
-	  if (value & 0x7ffff800)
-	    {
-	      alt_codes[i].code = (i == 0 ? UNKNOWN : IOR);
-	      alt_codes[i].value = value & 0x7ffff800;
-	      alt_codes[i].use_uw = false;
-	      value &= ~0x7ffff800;
-	      i++;
-	    }
+  /* Final cases, particularly focused on bseti.  */
+  if (cost > 2 && TARGET_ZBS)
+    {
+      int i = 0;
 
-	  /* Next, any bits we can handle with addi.  */
-	  if (value & 0x7ff)
-	    {
-	      alt_codes[i].code = (i == 0 ? UNKNOWN : PLUS);
-	      alt_codes[i].value = value & 0x7ff;
-	      alt_codes[i].use_uw = false;
-	      value &= ~0x7ff;
-	      i++;
-	    }
+      /* First handle any bits set by LUI.  Be careful of the
+	 SImode sign bit!.  */
+      if (value & 0x7ffff800)
+	{
+	  alt_codes[i].code = (i == 0 ? UNKNOWN : IOR);
+	  alt_codes[i].value = value & 0x7ffff800;
+	  alt_codes[i].use_uw = false;
+	  value &= ~0x7ffff800;
+	   i++;
+	}
 
-	  /* And any residuals with bseti.  */
-	  while (i < cost && value)
-	    {
-	      HOST_WIDE_INT bit = ctz_hwi (value);
-	      alt_codes[i].code = (i == 0 ? UNKNOWN : IOR);
-	      alt_codes[i].value = 1UL << bit;
-	      alt_codes[i].use_uw = false;
-	      value &= ~(1ULL << bit);
-	      i++;
-	    }
+      /* Next, any bits we can handle with addi.  */
+      if (value & 0x7ff)
+	{
+	  alt_codes[i].code = (i == 0 ? UNKNOWN : PLUS);
+	  alt_codes[i].value = value & 0x7ff;
+	  alt_codes[i].use_uw = false;
+	  value &= ~0x7ff;
+	  i++;
+	}
 
-	  /* If LUI+ADDI+BSETI resulted in a more efficient
-	     sequence, then use it.  */
-	  if (i < cost)
-	    {
-	      memcpy (codes, alt_codes, sizeof (alt_codes));
-	      cost = i;
-	    }
+      /* And any residuals with bseti.  */
+      while (i < cost && value)
+	{
+	  HOST_WIDE_INT bit = ctz_hwi (value);
+	  alt_codes[i].code = (i == 0 ? UNKNOWN : IOR);
+	  alt_codes[i].value = 1UL << bit;
+	  alt_codes[i].use_uw = false;
+	  value &= ~(1ULL << bit);
+	  i++;
+	}
+
+      /* If LUI+ADDI+BSETI resulted in a more efficient
+	 sequence, then use it.  */
+      if (i < cost)
+	{
+	  memcpy (codes, alt_codes, sizeof (alt_codes));
+	  cost = i;
 	}
     }
 

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diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 6f1c67bf3f7..dddb7f8d673 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -869,8 +869,10 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
 	  codes[1].use_uw = false;
 	  cost = 2;
 	}
+    }
+
   /* Final cases, particularly focused on bseti.  */
-      else if (cost > 2 && TARGET_ZBS)
+  if (cost > 2 && TARGET_ZBS)
     {
       int i = 0;
 
@@ -914,7 +916,6 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS],
 	  cost = i;
 	}
     }
-    }
 
   gcc_assert (cost <= RISCV_MAX_INTEGER_OPS);
   return cost;