From: Jeff Law <jeffreyalaw@gmail.com>
To: Stefan O'Rear <sorear@fastmail.com>,
"Wang, Yanzhang" <yanzhang.wang@intel.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
"kito.cheng@sifive.com" <kito.cheng@sifive.com>,
"Li, Pan2" <pan2.li@intel.com>
Subject: Re: [PATCH] RISCV: Add -m(no)-omit-leaf-frame-pointer support.
Date: Mon, 26 Jun 2023 08:30:26 -0600 [thread overview]
Message-ID: <3d60b047-3061-701d-faea-0149c63cdeb1@gmail.com> (raw)
In-Reply-To: <9be7090c-bef3-40b9-be6e-d4c61e10eb27@app.fastmail.com>
On 6/25/23 12:45, Stefan O'Rear wrote:
>
> To clarify: are you proposing to make ra (or t1 in the hypothetical) a fixed
> register for all functions, or only those heuristically identified as potentially
> larger than 1MiB? And would this extend to forcing the creation of stack frames
> for all functions, including very small functions? I am concerned this would
> result in a substantial performance regression.For the case Yanzhang is discussing (firmware and such), yes. And
that's simply the cost they're going to have to pay for wanting
consistent backtraces without utilizing dwarf unwind info, sframe or orc.
Normal builds won't be using those options and thus won't suffer from
those performance penalties.
>
> Without seeing the patch I can't know if I'm missing something obvious but I
> would say t1 has three advantages:
>
> 1. Consistency with tail, possibly simpler implementation.
And as I've already stated, this sequence is defined by the assembler.
While I do want to revisit a compiler only solution, it's way down on my
list of things to improve if I do a cost/benefit analysis. If someone
wants to take a stab at it, I'm all for it. But it's not a simple
problem due the phase ordering issues.
>
> 2. Very few functions use all seven t-registers. qemu linux-user in 2016 had an
> off-by-one bug that corrupted t6 in sigreturn and it took months for anyone to
> notice. By contrast, ra has live data in every non-_Noreturn function.
That's a terrible way to evaluate the impact. The right way is to use
real benchmarks. Not synthetic benchmarks. Not indirect observations
that require triggering a bug in a sigreturn path. Build and run a real
benchmark.
>
> 3. Any jalr instruction which has rs1=ra has a hint effect on the return address
> stack (call, return, or coroutine swap); a jalr which is intended to be treated
> as a plain jump must have rs1!=ra, rs1!=t0.
I'm well aware of these concerns. We support disambiguating various
jump forms to facilitate different branch predictors.
jeff
next prev parent reply other threads:[~2023-06-26 14:30 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-02 7:07 yanzhang.wang
2023-06-03 2:43 ` Jeff Law
2023-06-05 2:49 ` Wang, Yanzhang
2023-06-07 2:13 ` Jeff Law
2023-06-07 3:50 ` Wang, Yanzhang
2023-06-08 15:05 ` Jeff Law
2023-06-21 8:14 ` Wang, Yanzhang
2023-06-24 15:01 ` Jeff Law
2023-06-25 1:40 ` Stefan O'Rear
2023-06-25 12:49 ` Jeff Law
2023-06-25 18:45 ` Stefan O'Rear
2023-06-26 14:30 ` Jeff Law [this message]
2023-06-26 14:50 ` Kito Cheng
2023-06-26 16:51 ` Jeff Law
2023-06-05 1:04 ` Li, Pan2
2023-06-05 3:36 ` Wang, Yanzhang
2023-07-13 6:12 ` yanzhang.wang
2023-07-18 7:49 ` [PATCH v3] " yanzhang.wang
2023-07-21 3:49 ` Kito Cheng
2023-07-21 4:11 ` Jeff Law
2023-08-02 1:51 ` Wang, Yanzhang
2023-08-03 6:12 ` Jeff Law
2023-08-03 6:16 ` Li, Pan2
2023-08-03 6:22 ` Li, Pan2
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