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From: Kito Cheng <kito.cheng@gmail.com>
To: yanzhang.wang@intel.com
Cc: gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai,
	kito.cheng@sifive.com,  jeffreyalaw@gmail.com, pan2.li@intel.com
Subject: Re: [PATCH v3] RISCV: Add -m(no)-omit-leaf-frame-pointer support.
Date: Fri, 21 Jul 2023 11:49:20 +0800	[thread overview]
Message-ID: <CA+yXCZBeThy57v930V7W70EPz-Z7vSXUayJ-q6-0FOcXBPc6Qg@mail.gmail.com> (raw)
In-Reply-To: <20230718074958.2806939-1-yanzhang.wang@intel.com>

LGTM, I think long jump is another issue and making ra become a fixed
register will escalate to an ABI issue, so that should not be a
blocker for this patch.

On Tue, Jul 18, 2023 at 4:10 PM yanzhang.wang--- via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Yanzhang Wang <yanzhang.wang@intel.com>
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc (riscv_save_reg_p): Save ra for leaf
>           when enabling -mno-omit-leaf-frame-pointer
>         (riscv_option_override): Override omit-frame-pointer.
>         (riscv_frame_pointer_required): Save s0 for non-leaf function
>         (TARGET_FRAME_POINTER_REQUIRED): Override defination
>         * config/riscv/riscv.opt: Add option support.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/omit-frame-pointer-1.c: New test.
>         * gcc.target/riscv/omit-frame-pointer-2.c: New test.
>         * gcc.target/riscv/omit-frame-pointer-3.c: New test.
>         * gcc.target/riscv/omit-frame-pointer-4.c: New test.
>         * gcc.target/riscv/omit-frame-pointer-test.c: New test.
>
> Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
> ---
>  gcc/config/riscv/riscv.cc                     | 34 ++++++++++++++++++-
>  gcc/config/riscv/riscv.opt                    |  4 +++
>  .../gcc.target/riscv/omit-frame-pointer-1.c   |  7 ++++
>  .../gcc.target/riscv/omit-frame-pointer-2.c   |  7 ++++
>  .../gcc.target/riscv/omit-frame-pointer-3.c   |  7 ++++
>  .../gcc.target/riscv/omit-frame-pointer-4.c   |  7 ++++
>  .../riscv/omit-frame-pointer-test.c           | 13 +++++++
>  7 files changed, 78 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 706c18416db..caae6168c29 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -379,6 +379,10 @@ static const struct riscv_tune_info riscv_tune_info_table[] = {
>  #include "riscv-cores.def"
>  };
>
> +/* Global variable to distinguish whether we should save and restore s0/fp for
> +   function.  */
> +static bool riscv_save_frame_pointer;
> +
>  void riscv_frame_info::reset(void)
>  {
>    total_size = 0;
> @@ -4948,7 +4952,11 @@ riscv_save_reg_p (unsigned int regno)
>    if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
>      return true;
>
> -  if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
> +  /* Need not to use ra for leaf when frame pointer is turned off by option
> +     whatever the omit-leaf-frame's value.  */
> +  bool keep_leaf_ra = frame_pointer_needed && crtl->is_leaf
> +    && !TARGET_OMIT_LEAF_FRAME_POINTER;
> +  if (regno == RETURN_ADDR_REGNUM && (crtl->calls_eh_return || keep_leaf_ra))
>      return true;
>
>    /* If this is an interrupt handler, then must save extra registers.  */
> @@ -6577,6 +6585,21 @@ riscv_option_override (void)
>    if (flag_pic)
>      riscv_cmodel = CM_PIC;
>
> +  /* We need to save the fp with ra for non-leaf functions with no fp and ra
> +     for leaf functions while no-omit-frame-pointer with
> +     omit-leaf-frame-pointer.  The x_flag_omit_frame_pointer has the first
> +     priority to determine whether the frame pointer is needed.  If we do not
> +     override it, the fp and ra will be stored for leaf functions, which is not
> +     our wanted.  */
> +  riscv_save_frame_pointer = false;
> +  if (TARGET_OMIT_LEAF_FRAME_POINTER_P (global_options.x_target_flags))
> +    {
> +      if (!global_options.x_flag_omit_frame_pointer)
> +       riscv_save_frame_pointer = true;
> +
> +      global_options.x_flag_omit_frame_pointer = 1;
> +    }
> +
>    /* We get better code with explicit relocs for CM_MEDLOW, but
>       worse code for the others (for now).  Pick the best default.  */
>    if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0)
> @@ -7857,6 +7880,12 @@ riscv_preferred_else_value (unsigned, tree, unsigned int nops, tree *ops)
>    return nops == 3 ? ops[2] : ops[0];
>  }
>
> +static bool
> +riscv_frame_pointer_required (void)
> +{
> +  return riscv_save_frame_pointer && !crtl->is_leaf;
> +}
> +
>  /* Initialize the GCC target structure.  */
>  #undef TARGET_ASM_ALIGNED_HI_OP
>  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> @@ -8161,6 +8190,9 @@ riscv_preferred_else_value (unsigned, tree, unsigned int nops, tree *ops)
>  #undef TARGET_PREFERRED_ELSE_VALUE
>  #define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value
>
> +#undef TARGET_FRAME_POINTER_REQUIRED
> +#define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required
> +
>  struct gcc_target targetm = TARGET_INITIALIZER;
>
>  #include "gt-riscv.h"
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index dd062f1c8bd..4dfd8f78ad5 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -138,6 +138,10 @@ Enable the CSR checking for the ISA-dependent CRS and the read-only CSR.
>  The ISA-dependent CSR are only valid when the specific ISA is set.  The
>  read-only CSR can not be written by the CSR instructions.
>
> +momit-leaf-frame-pointer
> +Target Mask(OMIT_LEAF_FRAME_POINTER) Save
> +Omit the frame pointer in leaf functions.
> +
>  Mask(64BIT)
>
>  Mask(MUL)
> diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c
> new file mode 100644
> index 00000000000..c96123ea702
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-1.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline" } */
> +
> +#include "omit-frame-pointer-test.c"
> +
> +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 2 } } */
> +/* { dg-final { scan-assembler-times "sd\ts0,\[0-9\]+\\(sp\\)" 2 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c
> new file mode 100644
> index 00000000000..067148c6a58
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-2.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fno-omit-frame-pointer -momit-leaf-frame-pointer -fno-inline" } */
> +
> +#include "omit-frame-pointer-test.c"
> +
> +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */
> +/* { dg-final { scan-assembler-times "sd\ts0,\[0-9\]+\\(sp\\)" 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c
> new file mode 100644
> index 00000000000..b4d7d6f4f0d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-3.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fomit-frame-pointer -mno-omit-leaf-frame-pointer -fno-inline" } */
> +
> +#include "omit-frame-pointer-test.c"
> +
> +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */
> +/* { dg-final { scan-assembler-not "sd\ts0,\[0-9\]+\\(sp\\)"} } */
> diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c
> new file mode 100644
> index 00000000000..5a5b540ef4e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-4.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fomit-frame-pointer -momit-leaf-frame-pointer -fno-inline" } */
> +
> +#include "omit-frame-pointer-test.c"
> +
> +/* { dg-final { scan-assembler-times "sd\tra,\[0-9\]+\\(sp\\)" 1 } } */
> +/* { dg-final { scan-assembler-not "sd\ts0,\[0-9\]+\\(sp\\)"} } */
> diff --git a/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c
> new file mode 100644
> index 00000000000..cf19f001e29
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/omit-frame-pointer-test.c
> @@ -0,0 +1,13 @@
> +int inc(int n)
> +{
> +  return n + 1;
> +}
> +
> +
> +int bar(void)
> +{
> +  int n = 100;
> +  n = inc(n);
> +  n = inc(n) + 100;
> +  return n;
> +}
> --
> 2.40.1
>

  reply	other threads:[~2023-07-21  3:49 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-02  7:07 [PATCH] " yanzhang.wang
2023-06-03  2:43 ` Jeff Law
2023-06-05  2:49   ` Wang, Yanzhang
2023-06-07  2:13     ` Jeff Law
2023-06-07  3:50       ` Wang, Yanzhang
2023-06-08 15:05         ` Jeff Law
2023-06-21  8:14           ` Wang, Yanzhang
2023-06-24 15:01             ` Jeff Law
2023-06-25  1:40               ` Stefan O'Rear
2023-06-25 12:49                 ` Jeff Law
2023-06-25 18:45                   ` Stefan O'Rear
2023-06-26 14:30                     ` Jeff Law
2023-06-26 14:50                       ` Kito Cheng
2023-06-26 16:51                         ` Jeff Law
2023-06-05  1:04 ` Li, Pan2
2023-06-05  3:36   ` Wang, Yanzhang
2023-07-13  6:12 ` yanzhang.wang
2023-07-18  7:49 ` [PATCH v3] " yanzhang.wang
2023-07-21  3:49   ` Kito Cheng [this message]
2023-07-21  4:11     ` Jeff Law
2023-08-02  1:51       ` Wang, Yanzhang
2023-08-03  6:12         ` Jeff Law
2023-08-03  6:16           ` Li, Pan2
2023-08-03  6:22             ` Li, Pan2

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