rs6000, built-in cleanup patch series

rs6000, built-in cleanup patch series

[Carl Love]

GCC maintainers:

The following series of patches cleanup some of the rs6000 built-in support.  Some of the first patches fix errors in the definition of a few of the built-ins.  The built-ins are supposed to have unsigned arguments but are listed as signed.  Some of the built-ins are supposed to return unsigned values but were defined to return a signed value.

There are a number of built-ins that are not documented but are duplicates of other documented built-ins.  The duplicate definitions are removed so users will only use the supported documented built-ins.

There are a number of the built-ins that are not documented in either the Power Vector Intrinsic Reference manual or in the gcc/doc/extend.texi file.  The patch adds the missing documentation as needed.  

Also most of the built-ins do not have test cases.  The patch adds test cases for the various built-ins.

                                Carl 

[PATCH 01/11] rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins

[Carl Love]

GCC maintainers:

This patch fixes the arguments and return type for the various __builtin_vsx_cmple* built-ins.  They were defined as signed but should have been defined as unsigned.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 

-----------------------------------------------------

rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins

The built-ins __builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u2di,
__builtin_vsx_cmple_u4si and __builtin_vsx_cmple_u8hi should take
unsigned arguments and return an unsigned result.  This patch changes
the arguments and return type from signed to unsigned.

The documentation for the signed and unsigned versions of
__builtin_vsx_cmple is missing from extend.texi.  This patch adds the
missing documentation.

Test cases are added for each of the signed and unsigned built-ins.

gcc/ChangeLog:
	* config/rs6000/rs6000-builtins.def (__builtin_vsx_cmple_u16qi,
	__builtin_vsx_cmple_u2di, __builtin_vsx_cmple_u4si): Change
	arguments and return from signed to unsigned.
	* doc/extend.texi (__builtin_vsx_cmple_16qi,
	__builtin_vsx_cmple_8hi, __builtin_vsx_cmple_4si,
	__builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u8hi,
	__builtin_vsx_cmple_u4si): Add documentation.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vsx-cmple.c: New test file.
---
 gcc/config/rs6000/rs6000-builtins.def        |  10 +-
 gcc/doc/extend.texi                          |  23 ++++
 gcc/testsuite/gcc.target/powerpc/vsx-cmple.c | 127 +++++++++++++++++++
 3 files changed, 155 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-cmple.c

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 3bc7fed6956..d66a53a0fab 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1349,16 +1349,16 @@
   const vss __builtin_vsx_cmple_8hi (vss, vss);
     CMPLE_8HI vector_ngtv8hi {}
 
-  const vsc __builtin_vsx_cmple_u16qi (vsc, vsc);
+  const vuc __builtin_vsx_cmple_u16qi (vuc, vuc);
     CMPLE_U16QI vector_ngtuv16qi {}
 
-  const vsll __builtin_vsx_cmple_u2di (vsll, vsll);
+  const vull __builtin_vsx_cmple_u2di (vull, vull);
     CMPLE_U2DI vector_ngtuv2di {}
 
-  const vsi __builtin_vsx_cmple_u4si (vsi, vsi);
+  const vui __builtin_vsx_cmple_u4si (vui, vui);
     CMPLE_U4SI vector_ngtuv4si {}
 
-  const vss __builtin_vsx_cmple_u8hi (vss, vss);
+  const vus __builtin_vsx_cmple_u8hi (vus, vus);
     CMPLE_U8HI vector_ngtuv8hi {}
 
   const vd __builtin_vsx_concat_2df (double, double);
@@ -1769,7 +1769,7 @@
   const vf __builtin_vsx_xvcvuxdsp (vull);
     XVCVUXDSP vsx_xvcvuxdsp {}
 
-  const vd __builtin_vsx_xvcvuxwdp (vsi);
+  const vd __builtin_vsx_xvcvuxwdp (vui);
     XVCVUXWDP vsx_xvcvuxwdp {}
 
   const vf __builtin_vsx_xvcvuxwsp (vsi);
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 2b8ba1949bf..4d8610f6aa8 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22522,6 +22522,29 @@ if the VSX instruction set is available.  The @samp{vec_vsx_ld} and
 @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X},
 @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
 
+
+@smallexample
+vector signed char __builtin_vsx_cmple_16qi (vector signed char,
+                                             vector signed char);
+vector signed short __builtin_vsx_cmple_8hi (vector signed short,
+                                             vector signed short);
+vector signed int __builtin_vsx_cmple_4si (vector signed int,
+                                             vector signed int);
+vector unsigned char __builtin_vsx_cmple_u16qi (vector unsigned char,
+                                                vector unsigned char);
+vector unsigned short __builtin_vsx_cmple_u8hi (vector unsigned short,
+                                                vector unsigned short);
+vector unsigned int __builtin_vsx_cmple_u4si (vector unsigned int,
+                                              vector unsigned int);
+@end smallexample
+
+The builti-ins @code{__builtin_vsx_cmple_16qi}, @code{__builtin_vsx_cmple_8hi},
+@code{__builtin_vsx_cmple_4si}, @code{__builtin_vsx_cmple_u16qi},
+@code{__builtin_vsx_cmple_u8hi} and @code{__builtin_vsx_cmple_u4si} compare
+vectors of their defined type.  The corresponding result element is set to
+all ones if the two argument elements are less than or equal and all zeros
+otherwise.
+
 @node PowerPC AltiVec Built-in Functions Available on ISA 2.07
 @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
new file mode 100644
index 00000000000..081817b4ba3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
@@ -0,0 +1,127 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -save-temps" } */
+
+#define DEBUG 0
+
+#include <altivec.h>
+
+#if DEBUG
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+void abort (void);
+
+#if DEBUG
+  #define ACTION(NAME, TYPE_NAME)                                         \
+  printf ("test_vsx_cmple_%s: result_%s[%d] = 0x%x, expected_result_%s[%d] = 0x%x\n", \
+  	  #NAME, #TYPE_NAME, i, result_##TYPE_NAME[i],                    \
+  	  #TYPE_NAME, i, (int)expected_result_##TYPE_NAME[i]);
+#else
+  #define ACTION(NAME, TYPE_NAME)                                         \
+  abort();
+#endif
+
+#define TEST(NAME, TYPE, TYPE_NAME)					\
+void test_vsx_cmple_##NAME (vector TYPE arg1_##TYPE_NAME,               \
+			    vector TYPE arg2_##TYPE_NAME,               \
+			    vector TYPE expected_result_##TYPE_NAME)    \
+{                                                                       \
+  vector TYPE result_##TYPE_NAME;					\
+  int i, len = 16/sizeof(TYPE);						\
+                                                                        \
+  result_##TYPE_NAME = __builtin_vsx_cmple_##NAME (arg1_##TYPE_NAME,    \
+						   arg2_##TYPE_NAME);   \
+  for (i = 0; i < len; i++)                                             \
+    if (result_##TYPE_NAME[i] != expected_result_##TYPE_NAME[i])        \
+      ACTION(TYPE, TYPE_NAME)                                           \
+}
+
+int main ()
+{
+
+  vector signed char vsc_arg1, vsc_arg2, vsc_expected_result;
+  vector signed short vsh_arg1, vsh_arg2, vsh_expected_result;
+  vector signed int vsi_arg1, vsi_arg2, vsi_expected_result;
+  vector signed long long vsll_arg1, vsll_arg2, vsll_expected_result;
+  vector unsigned char vuc_arg1, vuc_arg2, vuc_expected_result;
+  vector unsigned short vuh_arg1, vuh_arg2, vuh_expected_result;
+  vector unsigned int vui_arg1, vui_arg2, vui_expected_result;
+  vector unsigned long long vull_arg1, vull_arg2, vull_expected_result;
+
+  vsc_arg1 = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+				   14, 15, 16};
+  vsc_arg2 = (vector signed char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
+				   21, 22, 23, 24, 25, 26};
+  vsc_expected_result = (vector signed char) {0xFF, 0xFF, 0xFF, 0xFF,
+					      0xFF, 0xFF, 0xFF, 0xFF,
+					      0xFF, 0xFF, 0xFF, 0xFF,
+					      0xFF, 0xFF, 0xFF, 0xFF};
+  /* Test for __builtin_vsx_cmple_16qi */
+  TEST (16qi, signed char, vsc)
+  test_vsx_cmple_16qi (vsc_arg1, vsc_arg2, vsc_expected_result);
+
+  vsh_arg1 = (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8};
+  vsh_arg2 = (vector signed short) {11, 12, 13, 14, 15, 16, 17, 18};
+  vsh_expected_result = (vector signed short) {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
+					       0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
+  /* Test for __builtin_vsx_cmple_8hi */
+  TEST (8hi, signed short, vsh)
+  test_vsx_cmple_8hi (vsh_arg1, vsh_arg2, vsh_expected_result);
+
+  vsi_arg1 = (vector signed int) {1, 2, 3, 4};
+  vsi_arg2 = (vector signed int) {11, 12, 13, 14};
+  vsi_expected_result = (vector signed int) {0xFFFFFFFF, 0xFFFFFFFF,
+					     0xFFFFFFFF, 0xFFFFFFFF};
+  /* Test for __builtin_vsx_cmple_4si */
+  TEST (4si, signed int, vsi)
+  test_vsx_cmple_4si (vsi_arg1, vsi_arg2, vsi_expected_result);
+
+  vsll_arg1 = (vector signed long long) {1, 2};
+  vsll_arg2 = (vector signed long long) {11, 12};
+  vsll_expected_result = (vector signed long long) {0xFFFFFFFFFFFFFFFF,
+						    0xFFFFFFFFFFFFFFFF};
+  /* Test for __builtin_vsx_cmple_2di */
+  TEST (2di, signed long long, vsll)
+  test_vsx_cmple_2di (vsll_arg1, vsll_arg2, vsll_expected_result);
+
+  vuc_arg1 = (vector unsigned char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+				     14, 15, 16};
+  vuc_arg2 = (vector unsigned char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
+				     22, 23, 24, 25, 26};
+  vuc_expected_result = (vector unsigned char) {0xFF, 0xFF, 0xFF, 0xFF,
+						0xFF, 0xFF, 0xFF, 0xFF,
+						0xFF, 0xFF, 0xFF, 0xFF,
+						0xFF, 0xFF, 0xFF, 0xFF};
+  /* Test for __builtin_vsx_cmple_u16qi */
+  TEST (u16qi, unsigned char, vuc)
+  test_vsx_cmple_u16qi (vuc_arg1, vuc_arg2, vuc_expected_result);
+
+  vuh_arg1 = (vector unsigned short) {1, 2, 3, 4, 5, 6, 7, 8};
+  vuh_arg2 = (vector unsigned short) {11, 12, 13, 14, 15, 16, 17, 18};
+  vuh_expected_result = (vector unsigned short) {0xFFFF, 0xFFFF,
+						 0xFFFF, 0xFFFF,
+						 0xFFFF, 0xFFFF,
+						 0xFFFF, 0xFFFF};
+  /* Test for __builtin_vsx_cmple_u8hi */
+  TEST (u8hi, unsigned short, vuh)
+  test_vsx_cmple_u8hi (vuh_arg1, vuh_arg2, vuh_expected_result);
+
+  vui_arg1 = (vector unsigned int) {1, 2, 3, 4};
+  vui_arg2 = (vector unsigned int) {11, 12, 13, 14};
+  vui_expected_result = (vector unsigned int) {0xFFFFFFFF, 0xFFFFFFFF,
+					       0xFFFFFFFF, 0xFFFFFFFF};
+  /* Test for __builtin_vsx_cmple_u4si */
+  TEST (u4si, unsigned int, vui)
+  test_vsx_cmple_u4si (vui_arg1, vui_arg2, vui_expected_result);
+
+  vull_arg1 = (vector unsigned long long) {1, 2};
+  vull_arg2 = (vector unsigned long long) {11, 12};
+  vull_expected_result = (vector unsigned long long) {0xFFFFFFFFFFFFFFFF,
+						      0xFFFFFFFFFFFFFFFF};
+  /* Test for __builtin_vsx_cmple_u2di */
+  TEST (u2di, unsigned long long, vull)
+  test_vsx_cmple_u2di (vull_arg1, vull_arg2, vull_expected_result);
+  return 0;
+}
-- 
2.43.0

[PATCH 02/11] rs6000, fix arguments, add documentation for vector, element conversions

[Carl Love]

GCC maintainers:

This patch fixes the  return type for the __builtin_vsx_xvcvdpuxws and __builtin_vsx_xvcvspuxds built-ins.  They were defined as signed but should have been defined as unsigned.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 

-----------------------------------------------------
rs6000, fix arguments, add documentation for vector element conversions

The return type for the __builtin_vsx_xvcvdpuxws, __builtin_vsx_xvcvspuxds,
__builtin_vsx_xvcvspuxws built-ins should be unsigned.  This patch changes
the return values from signed to unsigned.

The documentation for the vector element conversion built-ins:

__builtin_vsx_xvcvspsxws
__builtin_vsx_xvcvspsxds
__builtin_vsx_xvcvspuxds
__builtin_vsx_xvcvdpsxws
__builtin_vsx_xvcvdpuxws
__builtin_vsx_xvcvdpuxds_uns
__builtin_vsx_xvcvspdp
__builtin_vsx_xvcvdpsp
__builtin_vsx_xvcvspuxws
__builtin_vsx_xvcvsxwdp
__builtin_vsx_xvcvuxddp_uns
__builtin_vsx_xvcvuxwdp

is missing from extend.texi.  This patch adds the missing documentation.

This patch also adds runnable test cases for each of the built-ins.

gcc/ChangeLog:
	* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvdpuxws,
	__builtin_vsx_xvcvspuxds, __builtin_vsx_xvcvspuxws): Change
	return type from signed to unsigned.
	* doc/extend.texi (__builtin_vsx_xvcvspsxws,
	__builtin_vsx_xvcvspsxds, __builtin_vsx_xvcvspuxds,
	__builtin_vsx_xvcvdpsxws, __builtin_vsx_xvcvdpuxws,
	__builtin_vsx_xvcvdpuxds_uns, __builtin_vsx_xvcvspdp,
	__builtin_vsx_xvcvdpsp, __builtin_vsx_xvcvspuxws,
	__builtin_vsx_xvcvsxwdp, __builtin_vsx_xvcvuxddp_uns,
	__builtin_vsx_xvcvuxwdp): Add documentation for builtins.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vsx-builtin-runnable-1.c: New test file.
---
 gcc/config/rs6000/rs6000-builtins.def         |   6 +-
 gcc/doc/extend.texi                           | 135 ++++++++++
 .../powerpc/vsx-builtin-runnable-1.c          | 233 ++++++++++++++++++
 3 files changed, 371 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index d66a53a0fab..fd316f629e5 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1724,7 +1724,7 @@
   const vull __builtin_vsx_xvcvdpuxds_uns (vd);
     XVCVDPUXDS_UNS vsx_fixuns_truncv2dfv2di2 {}
 
-  const vsi __builtin_vsx_xvcvdpuxws (vd);
+  const vui __builtin_vsx_xvcvdpuxws (vd);
     XVCVDPUXWS vsx_xvcvdpuxws {}
 
   const vd __builtin_vsx_xvcvspdp (vf);
@@ -1736,10 +1736,10 @@
   const vsi __builtin_vsx_xvcvspsxws (vf);
     XVCVSPSXWS vsx_fix_truncv4sfv4si2 {}
 
-  const vsll __builtin_vsx_xvcvspuxds (vf);
+  const vull __builtin_vsx_xvcvspuxds (vf);
     XVCVSPUXDS vsx_xvcvspuxds {}
 
-  const vsi __builtin_vsx_xvcvspuxws (vf);
+  const vui __builtin_vsx_xvcvspuxws (vf);
     XVCVSPUXWS vsx_fixuns_truncv4sfv4si2 {}
 
   const vd __builtin_vsx_xvcvsxddp (vsll);
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 4d8610f6aa8..583b1d890bf 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21360,6 +21360,141 @@ __float128 __builtin_sqrtf128 (__float128);
 __float128 __builtin_fmaf128 (__float128, __float128, __float128);
 @end smallexample
 
+@smallexample
+vector int __builtin_vsx_xvcvspsxws (vector float);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvspsxws} converts the single precision floating
+point vector element i to a signed single-precision integer value using
+round to zero storing the result in element i.  If the source element is NaN
+the result is set to 0x80000000 and VXCI is set to 1.  If the source
+element is SNaN then VXSNAN is also set to 1.  If the rounded value is greater
+than 2^31 - 1 the result is 0x7FFFFFFF and VXCVI is set to 1.  If the
+rounded value is less than -2^31, the result is set to 0x80000000 and
+VXCVI is set to 1. If the rounded result is inexact then XX is set to 1.
+
+@smallexample
+vector signed long long int __builtin_vsx_xvcvspsxds (vector float);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvspsxds} converts the single precision floating
+point vector element to a double precision signed integer value using the
+round to zero rounding mode.  If the source element is NaN the result
+is set to 0x8000000000000000 and VXCI is set to 1.  If the source element is
+SNaN then VXSNAN is also set to 1.  If the rounded value is greater than
+2^63 - 1 the result is 0x7FFFFFFFFFFFFFFF and VXCVI is set to 1.  If the
+rounded value is less than zero, the result is set to 0x8000000000000000 and
+VXCVI is set to 1.  If the rounded result is inexact then XX is set to 1.
+
+@smallexample
+vector unsigned long long __builtin_vsx_xvcvspuxds (vector float);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvspuxds} converts the single precision floating
+point vector element 2*i to an unsigned double-precision integer value using
+round to zero storing the result in element i.  If the source element is NaN
+the result is set to 0x0000000000000000 and VXCI is set to 1.  If the source
+element is SNaN then VXSNAN is also set to 1.  If the rounded value is greater
+than 2^63 - 1 the result is 0xFFFFFFFFFFFFFFFF and VXCVI is set to 1.  If the
+rounded value is less than -2^63, the result is set to 0x0000000000000000 and
+VXCVI is set to 1.  If the rounded result is inexact then XX is set to 1.
+
+@smallexample
+vector signed int __builtin_vsx_xvcvdpsxws (vector double);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvdpsxws} converts the ith double precision floating
+point vector element to a single-precision integer value using the round to
+zero rounding mode.  The single precision integer value is placed into vector
+elements j and j+1 where j = i*2.  If the source element is NaN the result
+is set to 0x80000000 and VXCI is set to 1.  If the source element is SNaN then
+VXSNAN is also set to 1.  If the rounded value is greater than 2^31 - 1 the
+result is 0x7FFFFFFF and VXCVI is set to 1.  If the rounded value is less than
+-2^31, the result is set to 0x80000000 and VXCVI is set to 1.  If the rounded
+result is inexact then XX is set to 1.
+
+@smallexample
+vector unsigned int __builtin_vsx_xvcvdpuxws (vector double);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvdpuxws} converts the ith double precision floating
+point vector element to a unsigned single-precision integer value using the
+round to zero rounding mode.  The single precision integer value is placed into
+vector elements j and j+1 where j = i*2.  If the source element is NaN the
+result is set to 0x00000000 and VXCI is set to 1.  If the source element is
+SNaN then VXSNAN is also set to 1.  If the rounded value is greater than
+2^31 - 1 the result is 0xFFFFFFFF and VXCVI is set to 1.  If the rounded value
+is less than zero, the result is set to 0x00000000 and VXCVI is set to 1.  If
+the rounded result is inexact then XX is set to 1.
+
+@smallexample
+vector unsigned long long int __builtin_vsx_xvcvdpuxds_uns (vector double);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvdpuxds_uns} converts the double precision floating
+point vector element to a double precision unsigned integer value using the
+round to zero rounding mode.  If the source element is NaN the result is set
+to 0x0000000000000000 and VXCI is set to 1.  If the source element is SNaN
+then VXSNAN is also set to 1.  If the rounded value is greater than 2^63 - 1
+the result is 0xFFFFFFFFFFFFFFFF and VXCVI is set to 1.  If the rounded value
+is less than zero, the result is set to 0x0000000000000000 and VXCVI is set to
+1.  If the rounded result is inexact then XX is set to 1.
+
+@smallexample
+vector double __builtin_vsx_xvcvspdp (vector float);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvspdp} converts single precision floating
+point vector element to a double precision floating point value.  Input element
+at index 2*i is stored in the destination element i.
+
+@smallexample
+vector float __builtin_vsx_xvcvdpsp (vector double);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvdpsp} converts the ith double precision floating
+point vector element to a single-precision floating point value using the
+rounding mode specified by RN.  The single precision value is placed into
+vector elements j and j+1 where j = i*2.  The rounding mode, RN, is specified
+by bits [62:63] of the FPSCR.
+
+@smallexample
+vector unsigned int __builtin_vsx_xvcvspuxws (vector float);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvspuxws} converts the single precision floating
+point vector element i to an unsigned single-precision integer value using
+round to zero storing the result in element i.  If the source element is NaN
+the result is set to 0x00000000 and VXCI is set to 1.  If the source element
+is SNaN then VXSNAN is also set to 1.  If the rounded value is greater than
+2^31 - 1 the result is 0xFFFFFFFF and VXCVI is set to 1.  If the rounded
+value is less than -2^31, the result is set to 0x00000000 and VXCVI is set
+to 1. If the rounded result is inexact then XX is set to 1.
+
+@smallexample
+vector double __builtin_vsx_xvcvsxwdp (vector signed int);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvsxwdp} converts single precision integer value
+to a double precision floating point value.  Input element at index 2*i is
+stored in the destination element i.
+
+@smallexample
+vector double __builtin_vsx_xvcvuxddp_uns (vector unsigned long long);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvuxddp_uns} converts unsigned double-precision
+integer value to a double precision floating point value.  Input element
+at index i is stored in the destination element i.
+
+@smallexample
+vector double __builtin_vsx_xvcvuxwdp (vector unsigned int);
+@end smallexample
+
+The @code{__builtin_vsx_xvcvuxwdp} converts single precision unsigned integer
+value to a double precision floating point value.  Input element at index 2*i
+is stored in the destination element i.
+
 @node Basic PowerPC Built-in Functions Available on ISA 2.07
 @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c
new file mode 100644
index 00000000000..91d16c3ba72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c
@@ -0,0 +1,233 @@
+/* { dg-do run { target { lp64 } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power7" } */
+
+#define DEBUG 0
+
+#if DEBUG
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+void abort (void);
+
+int main ()
+{
+  int i;
+  vector double vd_arg1, vd_result, vd_expected_result;
+  vector float vf_arg1, vf_result, vf_expected_result;
+  vector int vsi_arg1;
+  vector unsigned int vui_arg1;
+  vector int vsi_result, vsi_expected_result;
+  vector unsigned int vui_result, vui_expected_result;
+  vector signed long long int vsll_result, vsll_expected_result;
+  vector unsigned long long int vull_arg1;
+  vector unsigned long long int vull_result, vull_expected_result;
+
+  /* VSX Vector Convert with round to zero Single-Precision floating point to
+     Single-Precision signed integer format using the round to zero mode.  */
+
+  vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234,
+			    9999999999956789012345678.9};
+  vsi_result = __builtin_vsx_xvcvspsxws (vf_arg1);
+  vsi_expected_result = (vector signed int) {12345, 7654, -2, 0x7fffffff};
+
+  for (i = 0; i < 4; i++)
+    if (vsi_result[i] != vsi_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvspsxws: vsi_result[%d] = 0x%x, vsi_expected_result[%d] = 0x%x\n",
+	     i, vsi_result[i], i, vsi_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert with round Single-Precision floating point to
+     Double-Precision signed integer format using the round to zero mode.  */
+
+  vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234,
+			    9999999999956789012345678.9};
+  vsll_result = __builtin_vsx_xvcvspsxds (vf_arg1);
+  vsll_expected_result = (vector signed long long) {7654, 0x7fffffffffffffff};
+
+  for (i = 0; i < 2; i++)
+    if (vsll_result[i] != vsll_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvspsxds: vsll_result[%d] = 0x%llx, vsll_expected_result[%d] = 0x%llx\n",
+	     i, vsll_result[i], i, vsll_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert with round Single-Precision floating point to
+     Double-Precision unsigned integer format using the round to zero mode.  */
+
+  vf_arg1 = (vector float) {12345.98, 764.321, -2.1234,
+			    9999999999956789012345678.9};
+  vull_result = __builtin_vsx_xvcvspuxds (vf_arg1);
+  vull_expected_result = (vector unsigned long long) {764, 0xffffffffffffffff};
+
+  for (i = 0; i < 2; i++)
+    if (vull_result[i] != vull_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvspuxds: vull_result[%d] = 0x%llx, vull_expected_result[%d] = 0x%llx\n",
+	     i, vull_result[i], i, vull_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert with round Double-Precision floating point to
+     signed Single-Precision integer format using the round to zero mode.  */
+
+  vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789};
+  /* Each double-precision value, i, is converted to single precision integer
+     and placed in vector elements j and j+1 where j = i*2.  The round to
+     zero rounding mode is used.  */
+  vsi_result = __builtin_vsx_xvcvdpsxws (vd_arg1);
+  vsi_expected_result = (vector int) {12345, 12345, -2, -2};
+
+  for (i = 0; i < 4; i++)
+    if (vsi_result[i] != vsi_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvdpsxws: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n",
+	     i, vsi_result[i], i, vsi_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert with round Double-Precision floating point to
+     unsigned Single-Precision integer format using the round to zero mode.  */
+
+  vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789};
+  /* Each double-precision value, i, is converted to single precision integer
+     and placed in vector elements j and j+1 where j = i*2.  The round to
+     zero rounding mode is used.  */
+  vui_result = __builtin_vsx_xvcvdpuxws (vd_arg1);
+  vui_expected_result = (vector unsigned int) {12345, 12345, 0, 0};
+
+  for (i = 0; i < 4; i++)
+    if (vui_result[i] != vui_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvdpuxws: vui_result[%d] = %d, vui_expected_result[%d] = %d\n",
+	     i, vui_result[i], i, vui_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert with round Double-Precision floating point to
+     Double-Precision unsigned integer format using the round to zero mode.  */
+
+  vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789};
+  vull_result = __builtin_vsx_xvcvdpuxds_uns (vd_arg1);
+  vull_expected_result = (vector unsigned long long) {12345, 0};
+
+  for (i = 0; i < 2; i++)
+    if (vull_result[i] != vull_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvdpuxds_uns: vull_result[%d] = %lld, vull_expected_result[%d] = %lld\n",
+	     i, vull_result[i], i, vull_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert Single-Precision floating point to Double-Precision
+     floating point  */
+
+  vf_arg1 = (vector float) {12345.98, -2.0, 31.11, -55.5};
+  vd_result = __builtin_vsx_xvcvspdp (vf_arg1);
+  vd_expected_result = (vector double) {-2.0, -55.5};
+
+  for (i = 0; i < 2; i++)
+    if (vd_result[i] != vd_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvspdp: vd_result[%d] = %f, vf_expected_result[%d] = %f\n",
+	     i, vd_result[i], i, vd_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert with round Double-Precision float point format to
+     Single-Precision floating point format using the rounding mode specified
+     by the RN field of the FPSCR.  */
+
+  vd_arg1 = (vector double) {12345.12345, -0.1234567890123456789};
+  /* Each double-precision value, i, is converted to single precision and
+     placed in vector elements j and j+1 where j = i*2.  */
+  vf_result = __builtin_vsx_xvcvdpsp (vd_arg1);
+  vf_expected_result = (vector float) {12345.12345, 12345.12345,
+				       -0.1234567890, -0.1234567890};
+
+  for (i = 0; i < 4; i++)
+    if (vf_result[i] != vf_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvdpsp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
+	     i, vf_result[i], i, vf_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert with round Single-Precision floating point to
+     Single-Precision unsigned integer format using the round to zero mode.  */
+
+  vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234,
+			    9999999999956789012345678.9};
+  vui_result = __builtin_vsx_xvcvspuxws (vf_arg1);
+  vui_expected_result = (vector unsigned int) {12345, 7654, 0x0, 0xffffffff};
+
+  for (i = 0; i < 4; i++)
+    if (vui_result[i] != vui_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvspuxws: vui_result[%d] = 0x%x, vui_expected_result[%d] = 0x%x\n",
+	     i, vui_result[i], i, vui_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert Signed integer word to Double-Precision floating point
+     format. */
+
+  vsi_arg1 = (vector int) {2345, 98, -2, -55};
+  vd_result = __builtin_vsx_xvcvsxwdp (vsi_arg1);
+  vd_expected_result = (vector double) {98.0, -55.0};
+
+  for (i = 0; i < 2; i++)
+    if (vd_result[i] != vd_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvsxwdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n",
+	     i, vd_result[i], i, vd_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert with round unsigned Double-Word integer to
+     Double-Precision floating point format.  */
+
+  vull_arg1 = (vector unsigned long long) {12398, 22255};
+  vd_result = __builtin_vsx_xvcvuxddp_uns (vull_arg1);
+  vd_expected_result = (vector double) {12398.0, 22255.0};
+
+  for (i = 0; i < 2; i++)
+    if (vd_result[i] != vd_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvuxddp_uns: vd_result[%d] = %f, vd_expected_result[%d] = %f\n",
+	     i, vd_result[i], i, vd_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Convert unsigned Single-Precision integer to Double-Precision
+     floating point format.  */
+
+  vui_arg1 = (vector unsigned int) {12398, 22255, 345, 87};
+  vd_result = __builtin_vsx_xvcvuxwdp (vui_arg1);
+  vd_expected_result = (vector double) {22255.0, 87.0};
+
+  for (i = 0; i < 2; i++)
+    if (vd_result[i] != vd_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcvuxwdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n",
+	     i, vd_result[i], i, vd_expected_result[i]);
+#else
+      abort();
+#endif
+  return 0;
+}
-- 
2.43.0

[PATCH 03/11] rs6000, remove duplicated built-ins

[Carl Love]

GCC maintainers:

There are a number of undocumented built-ins that are duplicates of other documented built-ins.  This patch removes the duplicates so users will only use the documented built-in.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 

-----------------------------------------------------

rs6000, remove duplicated built-ins

The following undocumented built-ins are same as existing documented
overloaded builtins.

  const vf __builtin_vsx_xxmrghw (vf, vf);
same as  vf __builtin_vec_mergeh (vf, vf);      (overloaded vec_mergeh)

  const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi);
same as vsi __builtin_vec_mergeh (vsi, vsi);   (overloaded vec_mergeh)

  const vf __builtin_vsx_xxmrglw (vf, vf);
same as vf __builtin_vec_mergel (vf, vf);      (overloaded vec_mergel)

  const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
same as vsi __builtin_vec_mergel (vsi, vsi);   (overloaded vec_mergel)

  const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc);
same as vsc __builtin_vec_sel (vsc, vsc, vuc);  (overloaded vec_sel)

  const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc);
same as vuc __builtin_vec_sel (vuc, vuc, vuc);  (overloaded vec_sel)

  const vd __builtin_vsx_xxsel_2df (vd, vd, vd);
same as  vd __builtin_vec_sel (vd, vd, vull);   (overloaded vec_sel)

  const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll);
same as vsll __builtin_vec_sel (vsll, vsll, vsll);  (overloaded vec_sel)

  const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull);
same as vull __builtin_vec_sel (vull, vull, vsll);  (overloaded vec_sel)

  const vf __builtin_vsx_xxsel_4sf (vf, vf, vf);
same as vf __builtin_vec_sel (vf, vf, vsi)          (overloaded vec_sel)

  const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi);
same as vsi __builtin_vec_sel (vsi, vsi, vbi);      (overloaded vec_sel)

  const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui);
same as vui __builtin_vec_sel (vui, vui, vui);      (overloaded vec_sel)

  const vss __builtin_vsx_xxsel_8hi (vss, vss, vss);
same as vss __builtin_vec_sel (vss, vss, vbs);      (overloaded vec_sel)

  const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus);
same as vus __builtin_vec_sel (vus, vus, vus);      (overloaded vec_sel)

This patch removed the duplicate built-in definitions so only the
documented built-ins will be available for use.  The case statements in
rs6000_gimple_fold_builtin that ar no longer needed are also removed.

gcc/ChangeLog:
	* config/rs6000/rs6000-builtins.def (__builtin_vsx_xxmrghw,
	__builtin_vsx_xxmrghw_4si, __builtin_vsx_xxmrglw,
	__builtin_vsx_xxmrglw_4si, __builtin_vsx_xxsel_16qi,
	__builtin_vsx_xxsel_16qi_uns, __builtin_vsx_xxsel_2df,
	__builtin_vsx_xxsel_2di, __builtin_vsx_xxsel_2di_uns,
	__builtin_vsx_xxsel_4sf, __builtin_vsx_xxsel_4si,
	__builtin_vsx_xxsel_4si_uns, __builtin_vsx_xxsel_8hi,
	__builtin_vsx_xxsel_8hi_uns): Removed built-in definition.
	* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin):
	remove case entries RS6000_BIF_XXMRGLW_4SI,
	RS6000_BIF_XXMRGLW_4SF, RS6000_BIF_XXMRGHW_4SI,
	RS6000_BIF_XXMRGHW_4SF.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vsx-builtin-3.c (__builtin_vsx_xxsel_4si,
	__builtin_vsx_xxsel_8hi, __builtin_vsx_xxsel_16qi,
	__builtin_vsx_xxsel_4sf, __builtin_vsx_xxsel_2df): Remove test
	cases for removed built-ins.
---
 gcc/config/rs6000/rs6000-builtin.cc           |  4 --
 gcc/config/rs6000/rs6000-builtins.def         | 42 -------------------
 .../gcc.target/powerpc/vsx-builtin-3.c        |  6 ---
 3 files changed, 52 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 6698274031b..e436cbe4935 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -2110,20 +2110,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
     /* vec_mergel (integrals).  */
     case RS6000_BIF_VMRGLH:
     case RS6000_BIF_VMRGLW:
-    case RS6000_BIF_XXMRGLW_4SI:
     case RS6000_BIF_VMRGLB:
     case RS6000_BIF_VEC_MERGEL_V2DI:
-    case RS6000_BIF_XXMRGLW_4SF:
     case RS6000_BIF_VEC_MERGEL_V2DF:
       fold_mergehl_helper (gsi, stmt, 1);
       return true;
     /* vec_mergeh (integrals).  */
     case RS6000_BIF_VMRGHH:
     case RS6000_BIF_VMRGHW:
-    case RS6000_BIF_XXMRGHW_4SI:
     case RS6000_BIF_VMRGHB:
     case RS6000_BIF_VEC_MERGEH_V2DI:
-    case RS6000_BIF_XXMRGHW_4SF:
     case RS6000_BIF_VEC_MERGEH_V2DF:
       fold_mergehl_helper (gsi, stmt, 0);
       return true;
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index fd316f629e5..96d095da2cb 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1925,18 +1925,6 @@
   const signed int __builtin_vsx_xvtsqrtsp_fg (vf);
     XVTSQRTSP_FG vsx_tsqrtv4sf2_fg {}
 
-  const vf __builtin_vsx_xxmrghw (vf, vf);
-    XXMRGHW_4SF vsx_xxmrghw_v4sf {}
-
-  const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi);
-    XXMRGHW_4SI vsx_xxmrghw_v4si {}
-
-  const vf __builtin_vsx_xxmrglw (vf, vf);
-    XXMRGLW_4SF vsx_xxmrglw_v4sf {}
-
-  const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
-    XXMRGLW_4SI vsx_xxmrglw_v4si {}
-
   const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>);
     XXPERMDI_16QI vsx_xxpermdi_v16qi {}
 
@@ -1958,42 +1946,12 @@
   const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<2>);
     XXPERMDI_8HI vsx_xxpermdi_v8hi {}
 
-  const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc);
-    XXSEL_16QI vector_select_v16qi {}
-
-  const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc);
-    XXSEL_16QI_UNS vector_select_v16qi_uns {}
-
   const vsq __builtin_vsx_xxsel_1ti (vsq, vsq, vsq);
     XXSEL_1TI vector_select_v1ti {}
 
   const vsq __builtin_vsx_xxsel_1ti_uns (vsq, vsq, vsq);
     XXSEL_1TI_UNS vector_select_v1ti_uns {}
 
-  const vd __builtin_vsx_xxsel_2df (vd, vd, vd);
-    XXSEL_2DF vector_select_v2df {}
-
-  const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll);
-    XXSEL_2DI vector_select_v2di {}
-
-  const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull);
-    XXSEL_2DI_UNS vector_select_v2di_uns {}
-
-  const vf __builtin_vsx_xxsel_4sf (vf, vf, vf);
-    XXSEL_4SF vector_select_v4sf {}
-
-  const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi);
-    XXSEL_4SI vector_select_v4si {}
-
-  const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui);
-    XXSEL_4SI_UNS vector_select_v4si_uns {}
-
-  const vss __builtin_vsx_xxsel_8hi (vss, vss, vss);
-    XXSEL_8HI vector_select_v8hi {}
-
-  const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus);
-    XXSEL_8HI_UNS vector_select_v8hi_uns {}
-
   const vsc __builtin_vsx_xxsldwi_16qi (vsc, vsc, const int<2>);
     XXSLDWI_16QI vsx_xxsldwi_v16qi {}
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
index ff875c55304..10bf39b89ed 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
@@ -61,12 +61,6 @@ int do_sel(void)
 {
   int i = 0;
 
-  si[i][0] = __builtin_vsx_xxsel_4si (si[i][1], si[i][2], si[i][3]); i++;
-  ss[i][0] = __builtin_vsx_xxsel_8hi (ss[i][1], ss[i][2], ss[i][3]); i++;
-  sc[i][0] = __builtin_vsx_xxsel_16qi (sc[i][1], sc[i][2], sc[i][3]); i++;
-  f[i][0] = __builtin_vsx_xxsel_4sf (f[i][1], f[i][2], f[i][3]); i++;
-  d[i][0] = __builtin_vsx_xxsel_2df (d[i][1], d[i][2], d[i][3]); i++;
-
   si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], bi[i][3]); i++;
   ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], bs[i][3]); i++;
   sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], bc[i][3]); i++;
-- 
2.43.0

[PATCH 04/11] rs6000, Update comment for the __builtin_vsx_vper*, built-ins.

[Carl Love]

GCC maintainers:

The patch expands an existing comment to document that the duplicates are covered by an overloaded built-in.  I am wondering if we should just go ahead and remove the duplicates?

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 

-----------------------------------------------------
rs6000, Update comment for the __builtin_vsx_vper* built-ins.

There is a comment about the __builtin_vsx_vper* built-ins being
duplicates of the __builtin_altivec_* built-ins.  The note says we
should consider deprecation/removeal of the __builtin_vsx_vper*.  Add a
note that the _builtin_vsx_vper* built-ins are covered by the overloaded
vec_perm built-ins which use the __builtin_altivec_* built-in definitions.

gcc/ChangeLog:
	* config/rs6000/rs6000-builtins.def ( __builtin_vsx_vperm_*):
	Add comment to existing comment about the built-ins.
---
 gcc/config/rs6000/rs6000-builtins.def | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 96d095da2cb..4c95429f137 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -1556,6 +1556,14 @@
 ; These are duplicates of __builtin_altivec_* counterparts, and are being
 ; kept for backwards compatibility.  The reason for their existence is
 ; unclear.  TODO: Consider deprecation/removal at some point.
+; Note, __builtin_vsx_vperm_16qi, __builtin_vsx_vperm_16qi_uns,
+; __builtin_vsx_vperm_1ti, __builtin_vsx_vperm_v1ti_uns,
+; __builtin_vsx_vperm_2df, __builtin_vsx_vperm_2di, __builtin_vsx_vperm_2di,
+; __builtin_vsx_vperm_2di_uns, __builtin_vsx_vperm_4sf,
+; __builtin_vsx_vperm_4si, __builtin_vsx_vperm_4si_uns,
+; __builtin_vsx_vperm_8hi, __builtin_altivec_vperm_8hi_uns
+; are all covered by the overloaded vec_perm built-in which uses the
+; __builtin_altivec_* built-in definitions.
   const vsc __builtin_vsx_vperm_16qi (vsc, vsc, vuc);
     VPERM_16QI_X altivec_vperm_v16qi {}
 
-- 
2.43.0

[PATCH 05/11] rs6000, __builtin_vsx_xvneg[sp,dp] add documentation, and test cases

[Carl Love]

GCC maintainers:

The patch adds documentation and test cases for the __builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp built-ins.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 
------------------------------------------------------------
rs6000, __builtin_vsx_xvneg[sp,dp] add documentation and test cases

Add documentation to the extend.texi file for the two built-ins
__builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp.

Add test cases for the two built-ins.

gcc/ChangeLog:
	* doc/extend.texi (__builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp):
	Add documentation.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vsx-builtin-runnable-2.c: New test case.
---
 gcc/doc/extend.texi                           | 13 +++++
 .../powerpc/vsx-builtin-runnable-2.c          | 51 +++++++++++++++++++
 2 files changed, 64 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 583b1d890bf..83eed9e334b 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21495,6 +21495,19 @@ The @code{__builtin_vsx_xvcvuxwdp} converts single precision unsigned integer
 value to a double precision floating point value.  Input element at index 2*i
 is stored in the destination element i.
 
+@smallexample
+vector float __builtin_vsx_xvnegsp (vector float);
+vector double __builtin_vsx_xvnegdp (vector double);
+@end smallexample
+
+The  @code{__builtin_vsx_xvnegsp} and @code{__builtin_vsx_xvnegdp} negate each
+vector element.
+
+@smallexample
+vector __int128  __builtin_vsx_xxpermdi_1ti (vector __int128, vector __int128,
+const int);
+
+@end smallexample
 @node Basic PowerPC Built-in Functions Available on ISA 2.07
 @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c
new file mode 100644
index 00000000000..7906a8e01d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c
@@ -0,0 +1,51 @@
+/* { dg-do run { target { lp64 } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power7" } */
+
+#define DEBUG 0
+
+#if DEBUG
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+void abort (void);
+
+int main ()
+{
+  int i;
+  vector double vd_arg1, vd_result, vd_expected_result;
+  vector float vf_arg1, vf_result, vf_expected_result;
+
+  /* VSX Vector Negate Single-Precision.  */
+
+  vf_arg1 = (vector float) {-1.0, 12345.98, -2.1234, 238.9};
+  vf_result = __builtin_vsx_xvnegsp (vf_arg1);
+  vf_expected_result = (vector float) {1.0, -12345.98, 2.1234, -238.9};
+
+  for (i = 0; i < 4; i++)
+    if (vf_result[i] != vf_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvnegsp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
+	     i, vf_result[i], i, vf_expected_result[i]);
+#else
+      abort();
+#endif
+
+  /* VSX Vector Negate Double-Precision.  */
+
+  vd_arg1 = (vector double) {12345.98, -2.1234};
+  vd_result = __builtin_vsx_xvnegdp (vd_arg1);
+  vd_expected_result = (vector double) {-12345.98, 2.1234};
+
+  for (i = 0; i < 2; i++)
+    if (vd_result[i] != vd_expected_result[i])
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvnegdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n",
+	     i, vd_result[i], i, vd_expected_result[i]);
+#else
+      abort();
+#endif
+
+  return 0;
+}
-- 
2.43.0

[PATCH 06/11] rs6000, __builtin_vsx_xxpermdi_1ti add documentation, and test case

[Carl Love]

GCC maintainers:

The patch adds documentation and test case for the __builtin_vsx_xxpermdi_1ti built-in.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 
------------------------------------------------------------

rs6000, __builtin_vsx_xxpermdi_1ti add documentation and test case

Add documentation to the extend.texi file for the
__builtin_vsx_xxpermdi_1ti built-in.

Add test cases for the __builtin_vsx_xxpermdi_1ti built-in.

gcc/ChangeLog:
	* doc/extend.texi (__builtin_vsx_xxpermdi_1ti): Add documentation.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vsx-builtin-runnable-3.c: New test case.
---
 gcc/doc/extend.texi                           |  7 +++
 .../powerpc/vsx-builtin-runnable-3.c          | 48 +++++++++++++++++++
 2 files changed, 55 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 83eed9e334b..22f67ebab31 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -21508,6 +21508,13 @@ vector __int128  __builtin_vsx_xxpermdi_1ti (vector __int128, vector __int128,
 const int);
 
 @end smallexample
+
+The  @code{__builtin_vsx_xxpermdi_1ti} Let srcA[127:0] be the 128-bit first
+argument and srcB[127:0] be the 128-bit second argument.  Let sel[1:0] be the
+least significant bits of the const int argument (third input argument).  The
+result bits [127:64] is srcB[127:64] if  sel[1] = 0, srcB[63:0] otherwise.  The
+result bits [63:0] is srcA[127:64] if  sel[0] = 0, srcA[63:0] otherwise.
+
 @node Basic PowerPC Built-in Functions Available on ISA 2.07
 @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07
 
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c
new file mode 100644
index 00000000000..ba287597cec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c
@@ -0,0 +1,48 @@
+/* { dg-do run { target { lp64 } } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power7" } */
+
+#include <altivec.h>
+
+#define DEBUG 0
+
+#if DEBUG
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+void abort (void);
+
+int main ()
+{
+  int i;
+
+  vector signed __int128 vsq_arg1, vsq_arg2, vsq_result, vsq_expected_result;
+
+  vsq_arg1[0] = (__int128) 0xFFFF0000FFFF0000;
+  vsq_arg1[0] = vsq_arg1[0] << 64 | (__int128) 0xFFFF0000FFFF;
+  vsq_arg2[0] = (__int128) 0x1100110011001100;
+  vsq_arg2[0] = (vsq_arg2[0]  << 64) | (__int128) 0x1111000011110000;
+
+  vsq_expected_result[0] = (__int128) 0x1111000011110000;
+  vsq_expected_result[0] = (vsq_expected_result[0] << 64)
+    | (__int128) 0xFFFF0000FFFF0000;
+
+  vsq_result = __builtin_vsx_xxpermdi_1ti (vsq_arg1, vsq_arg2, 2);
+
+  if (vsq_result[0] != vsq_expected_result[0])
+    {
+#if DEBUG
+       printf("ERROR, __builtin_vsx_xxpermdi_1ti: vsq_result = 0x%016llx %016llx\n",
+	      (unsigned long long) (vsq_result[0] >> 64),
+	      (unsigned long long) vsq_result[0]);
+       printf("                         vsq_expected_resultd = 0x%016llx %016llx\n",
+	      (unsigned long long)(vsq_expected_result[0] >> 64),
+	      (unsigned long long) vsq_expected_result[0]);
+#else
+      abort();
+#endif
+     }
+
+  return 0;
+}
-- 
2.43.0

[PATCH 07/11] rs6000, __builtin_vsx_xvcmpeq[sp, dp, sp_p] add, documentation and test case

[Carl Love]

 GCC maintainers:

The patch adds documentation and test case for the  __builtin_vsx_xvcmpeq[sp, dp, sp_p] built-ins.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 
------------------------------------------------------------

rs6000, __builtin_vsx_xvcmpeq[sp, dp, sp_p] add documentation and test case

Add a test case for the __builtin_vsx_xvcmpeqsp_p built-in.

Add documentation for the __builtin_vsx_xvcmpeqsp_p,
__builtin_vsx_xvcmpeqdp, and __builtin_vsx_xvcmpeqsp builtins.

gcc/ChangeLog:
	* doc/extend.texi (__builtin_vsx_xvcmpeqsp_p,
	__builtin_vsx_xvcmpeqdp, __builtin_vsx_xvcmpeqsp): Add
	documentation.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vsx-builtin-runnable-4.c: New test case.
---
 gcc/doc/extend.texi                           |  23 +++
 .../powerpc/vsx-builtin-runnable-4.c          | 135 ++++++++++++++++++
 2 files changed, 158 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 22f67ebab31..87fd30bfa9e 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22700,6 +22700,18 @@ vectors of their defined type.  The corresponding result element is set to
 all ones if the two argument elements are less than or equal and all zeros
 otherwise.
 
+@smallexample
+const vf __builtin_vsx_xvcmpeqsp (vf, vf);
+const vd __builtin_vsx_xvcmpeqdp (vd, vd);
+@end smallexample
+
+The builti-ins @code{__builtin_vsx_xvcmpeqdp} and
+@code{__builtin_vsx_xvcmpeqdp} compare two floating point vectors and return
+a vector.  If the corresponding elements are equal then the corresponding
+vector element of the result is set to all ones, it is set to all zeros
+otherwise.
+
+
 @node PowerPC AltiVec Built-in Functions Available on ISA 2.07
 @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07
 
@@ -23989,6 +24001,17 @@ is larger than 128 bits, the result is undefined.
 The result is the modulo result of dividing the first input  by the second
 input.
 
+@smallexample
+const signed int __builtin_vsx_xvcmpeqdp_p (signed int, vd, vd);
+@end smallexample
+
+The first argument of the builti-in @code{__builtin_vsx_xvcmpeqdp_p} is an
+integer in the range of 0 to 1.  The second and third arguments are floating
+point vectors to be compared.  The result is 1 if the first argument is a 1
+and one or more of the corresponding vector elements are equal.  The result is
+1 if the first argument is 0 and all of the corresponding vector elements are
+not equal.  The result is zero otherwise.
+
 The following builtins perform 128-bit vector comparisons.  The
 @code{vec_all_xx}, @code{vec_any_xx}, and @code{vec_cmpxx}, where @code{xx} is
 one of the operations @code{eq, ne, gt, lt, ge, le} perform pairwise
diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c
new file mode 100644
index 00000000000..8ac07c7c807
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c
@@ -0,0 +1,135 @@
+/* { dg-do run { target { power10_hw } } } */
+/* { dg-do link { target { ! power10_hw } } } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -save-temps" } */
+/* { dg-require-effective-target power10_ok } */
+
+#define DEBUG 0
+
+#if DEBUG
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+void abort (void);
+
+int main ()
+{
+  int i;
+  int result;
+  vector float vf_arg1, vf_arg2;
+  vector double d_arg1, d_arg2;
+
+  /* Compare vectors with one equal element, check
+     for all elements unequal, i.e. first arg is 1.  */
+  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
+  vf_arg2 = (vector float) {1.0, 3.0, 2.0, 8.0};
+  result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2);
+
+#if DEBUG
+  printf("result = 0x%x\n", (unsigned int) result);
+#endif
+
+  if (result != 1)
+    for (i = 0; i < 4; i++)
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 1: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n",
+	     i, vf_arg1[i], i, vf_arg2[i]);
+#else
+      abort();
+#endif
+  /* Compare vectors with one equal element, check
+     for all elements unequal, i.e. first arg is 0.  */
+  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
+  vf_arg2 = (vector float) {1.0, 3.0, 2.0, 8.0};
+  result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2);
+
+#if DEBUG
+  printf("result = 0x%x\n", (unsigned int) result);
+#endif
+
+  if (result != 0)
+    for (i = 0; i < 4; i++)
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 2: arg 1 = 0, varg3[%d] = %f, varg3[%d] = %f\n",
+	     i, vf_arg1[i], i, vf_arg2[i]);
+#else
+      abort();
+#endif
+
+  /* Compare vectors with all unequal elements, check
+     for all elements unequal, i.e. first arg is 1.  */
+  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
+  vf_arg2 = (vector float) {8.0, 3.0, 2.0, 8.0};
+  result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2);
+
+#if DEBUG
+  printf("result = 0x%x\n", (unsigned int) result);
+#endif
+
+  if (result != 0)
+    for (i = 0; i < 4; i++)
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 3: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n",
+	     i, vf_arg1[i], i, vf_arg2[i]);
+#else
+      abort();
+#endif
+
+  /* Compare vectors with all unequal elements, check
+     for all elements unequal, i.e. first arg is 0.  */
+  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
+  vf_arg2 = (vector float) {8.0, 3.0, 2.0, 8.0};
+  result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2);
+
+#if DEBUG
+  printf("result = 0x%x\n", (unsigned int) result);
+#endif
+
+  if (result != 1)
+    for (i = 0; i < 4; i++)
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 4: arg 1 = 0, varg3[%d] = %f, varg3[%d] = %f\n",
+	     i, vf_arg1[i], i, vf_arg2[i]);
+#else
+      abort();
+#endif
+
+  /* Compare vectors with all equal elements, check
+     for all elements equal, i.e. first arg is 1.  */
+  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
+  vf_arg2 = (vector float) {1.0, 2.0, 3.0, 4.0};
+  result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2);
+
+#if DEBUG
+  printf("result = 0x%x\n", (unsigned int) result);
+#endif
+
+  if (result != 1)
+    for (i = 0; i < 4; i++)
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 5: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n",
+	     i, vf_arg1[i], i, vf_arg2[i]);
+#else
+      abort();
+#endif
+
+  /* Compare vectors with all equal elements, check
+     for all elements unequal, i.e. first arg is 0.  */
+  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
+  vf_arg2 = (vector float) {1.0, 2.0, 3.0, 4.0};
+  result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2);
+
+#if DEBUG
+  printf("result = 0x%x\n", (unsigned int) result);
+#endif
+
+  if (result != 0)
+    for (i = 0; i < 4; i++)
+#if DEBUG
+      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 6: arg 0 = 1, varg3[%d] = %f, varg3[%d] = %f\n",
+	     i, vf_arg1[i], i, vf_arg2[i]);
+#else
+      abort();
+#endif
+  return 0;
+}
-- 
2.43.0

[PATCH 08/11] rs6000, add tests and documentation for various, built-ins

[Carl Love]

 
 GCC maintainers:

The patch adds documentation a number of built-ins.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 
------------------------------------------------------------
 rs6000, add tests and documentation for various built-ins

This patch adds a test case and documentation in extend.texi for the
following built-ins:

__builtin_altivec_fix_sfsi
__builtin_altivec_fixuns_sfsi
__builtin_altivec_float_sisf
__builtin_altivec_uns_float_sisf
__builtin_altivec_vrsqrtfp
__builtin_altivec_mask_for_load
__builtin_altivec_vsel_1ti
__builtin_altivec_vsel_1ti_uns
__builtin_vec_init_v16qi
__builtin_vec_init_v4sf
__builtin_vec_init_v4si
__builtin_vec_init_v8hi
__builtin_vec_set_v16qi
__builtin_vec_set_v4sf
__builtin_vec_set_v4si
__builtin_vec_set_v8hi

gcc/ChangeLog:
	* doc/extend.texi (__builtin_altivec_fix_sfsi,
	__builtin_altivec_fixuns_sfsi, __builtin_altivec_float_sisf,
	__builtin_altivec_uns_float_sisf, __builtin_altivec_vrsqrtfp,
	__builtin_altivec_mask_for_load, __builtin_altivec_vsel_1ti,
	__builtin_altivec_vsel_1ti_uns, __builtin_vec_init_v16qi,
	__builtin_vec_init_v4sf, __builtin_vec_init_v4si,
	__builtin_vec_init_v8hi, __builtin_vec_set_v16qi,
	__builtin_vec_set_v4sf, __builtin_vec_set_v4si,
	__builtin_vec_set_v8hi): Add documentation.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/altivec-38.c: New test case.
---
 gcc/doc/extend.texi                           |  98 ++++
 gcc/testsuite/gcc.target/powerpc/altivec-38.c | 503 ++++++++++++++++++
 2 files changed, 601 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-38.c

diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 87fd30bfa9e..89d0a1f77b0 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -22678,6 +22678,104 @@ if the VSX instruction set is available.  The @samp{vec_vsx_ld} and
 @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
 
 
+@smallexample
+vector signed int __builtin_altivec_fix_sfsi (vector float);
+vector signed int __builtin_altivec_fixuns_sfsi (vector float);
+vector float __builtin_altivec_float_sisf (vector int);
+vector float __builtin_altivec_uns_float_sisf (vector int);
+vector float __builtin_altivec_vrsqrtfp (vector float);
+@end smallexample
+
+The @code{__builtin_altivec_fix_sfsi} converts a vector of single precision
+floating point values to a vector of signed integers with round to zero.
+
+The @code{__builtin_altivec_fixuns_sfsi} converts a vector of single precision
+floating point values to a vector of unsigned integers with round to zero.  If
+the rounded floating point value is less then 0 the result is 0 and VXCVI
+is set to 1.
+
+The @code{__builtin_altivec_float_sisf} converts a vector of single precision
+signed integers to a vector of floating point values using the rounding mode
+specified by RN.
+
+The @code{__builtin_altivec_uns_float_sisf} converts a vector of single
+precision unsigned integers to a vector of floating point values using the
+rounding mode specified by RN.
+
+The @code{__builtin_altivec_vrsqrtfp} returns a vector of floating point
+estimates of the reciprical square root of each floating point source vector
+element.
+
+@smallexample
+vector signed char test_altivec_mask_for_load (const void *);
+@end smallexample
+
+The @code{__builtin_altivec_vrsqrtfp} returns a vector mask based on the
+bottom four bits of the argument.  Let X be the 32-byte value:
+0x00 || 0x01 || 0x02 || ... || 0x1D || 0x1E || 0x1F.
+Bytes sh to sh+15 are returned where sh is given by the least significant 4
+bit of the argument. See description of lvsl, lvsr instructions.
+
+@smallexample
+vector signed __int128 __builtin_altivec_vsel_1ti (vector signed __int128,
+                                                   vector signed __int128,
+                                                   vector unsigned __int128);
+vector unsigned __int128
+  __builtin_altivec_vsel_1ti_uns (vector unsigned __int128,
+                                  vector unsigned __int128,
+                                  vector unsigned __int128)
+@end smallexample
+
+Let the arguments of @code{__builtin_altivec_vsel_1ti} and
+@code{__builtin_altivec_vsel_1ti_uns} be src1, src2, mask.  The result is
+given by (src1 & ~mask) | (src2 & mask).
+
+@smallexample
+vector signed char
+__builtin_vec_init_v16qi (signed char, signed char, signed char, signed char,
+                          signed char, signed char, signed char, signed char,
+                          signed char, signed char, signed char, signed char,
+                          signed char, signed char, signed char, signed char);
+
+vector short int __builtin_vec_init_v8hi (short int, short int, short int,
+                                          short int, short int, short int,
+                                          short int, short int);
+vector signed int __builtin_vec_init_v4si (signed int, signed int, signed int,
+                                           signed int);
+vector float __builtin_vec_init_v4sf (float, float, float, float);
+vector __int128 __builtin_vec_init_v1ti (signed __int128);
+vector double __builtin_vec_init_v2df (double, double);
+vector signed long long __builtin_vec_init_v2di (signed long long,
+                                                 signed long long);
+@end smallexample
+
+The builti-ins @code{__builtin_vec_init_v16qi}, @code{__builtin_vec_init_v8hi},
+@code{__builtin_vec_init_v4si}, @code{__builtin_vec_init_v4sf},
+@code{__builtin_vec_init_v1ti}, @code{__builtin_vec_init_v2df} and
+@code{__builtin_vec_init_v2di} return a
+vector corresponding to the argument type initialized with the value of the
+arguments.
+
+@smallexample
+vector signed char __builtin_vec_set_v16qi (vector signed char, signed char,
+                                            const int);
+vector short int __builtin_vec_set_v8hi (vector short int, short int,
+                                         const int);
+vector signed int __builtin_vec_set_v4si (vector signed int, signed int,
+                                          const int);
+vector float __builtin_vec_set_v4sf (vector float, float, const int);
+vector __int128 __builtin_vec_set_v1ti (vector __int128, __int128, const int);
+vector double __builtin_vec_set_v2dfi (vector double, double, const int);
+vector signed long long __builtin_vec_set_v2dfi (vector signed long long,
+                                                 signed long long, const int);
+@end smallexample
+
+The builti-ins @code{__builtin_vec_set_v16qi}, @code{__builtin_vec_set_v8hi},
+@code{__builtin_vec_set_v4si}, @code{__builtin_vec_set_v4sf},
+@code{__builtin_vec_set_v1ti},  @code{__builtin_vec_set_v2dfi} and
+@code{__builtin_vec_set_v2dfi} return the input source vector with the element
+indexed by the const int replaced by the scalar argument.
+
 @smallexample
 vector signed char __builtin_vsx_cmple_16qi (vector signed char,
                                              vector signed char);
diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-38.c b/gcc/testsuite/gcc.target/powerpc/altivec-38.c
new file mode 100644
index 00000000000..01330e67110
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/altivec-38.c
@@ -0,0 +1,503 @@
+/* { dg-do run { target powerpc*-*-* } } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-O2 -save-temps" } */
+
+#define DEBUG 0
+
+#include <altivec.h>
+#include <stddef.h>
+
+#if DEBUG
+#include <stdio.h>
+#include <stdlib.h>
+#endif
+
+void abort (void);
+
+void test_altivec_fix_sfsi (vector float vf_arg,
+			    vector int vsi_expected_result)
+{
+  int i;
+  vector signed int vsi_result;
+
+  vsi_result = __builtin_altivec_fix_sfsi (vf_arg);
+
+  for (i = 0; i < 4; i++)
+    if (vsi_expected_result[i] != vsi_result[i])
+#if DEBUG
+      printf ("test_altivec_fix_sfsi: vsi_result[%d] = %i, vsi_expected_result[%d] = %d\n",
+	      i, vsi_result[i], i, vsi_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_altivec_fixuns_sfsi (vector float vf_arg,
+			       vector unsigned int vui_expected_result)
+{
+  int i;
+  vector unsigned int vui_result;
+
+  vui_result = __builtin_altivec_fixuns_sfsi (vf_arg);
+
+  for (i = 0; i < 4; i++)
+    if (vui_expected_result[i] != vui_result[i])
+#if DEBUG
+      printf ("test_altivec_fixuns_sfsi: vui_result[%d] = %i, vsi_expected_result[%d] = %d\n",
+		i, vui_result[i], i, vui_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_altivec_float_sisf (vector signed int vsi_arg,
+			      vector float vf_expected_result)
+{
+  int i;
+  vector float vf_result;
+
+  vf_result = __builtin_altivec_float_sisf (vsi_arg);
+
+  for (i = 0; i < 4; i++)
+    if (vf_expected_result[i] != vf_result[i])
+#if DEBUG
+      printf ("test_altivec_float_sisf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
+		i, vf_result[i], i, vf_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_altivec_uns_float_sisf (vector unsigned int vui_arg,
+				  vector float vf_expected_result)
+{
+  int i;
+  vector float vf_result;
+
+  vf_result = __builtin_altivec_uns_float_sisf (vui_arg);
+
+  for (i = 0; i < 4; i++)
+    if (vf_expected_result[i] != vf_result[i])
+#if DEBUG
+      printf ("test_altivec_uns_float_sisf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
+	      i, vf_result[i], i, vf_expected_result[i]);
+#else
+    abort();
+#endif
+}
+
+void test_altivec_vrsqrtfp (vector float vf_arg,
+			    vector float vf_expected_result)
+{
+  /* Compute the reciprical of the square root of each vector element.  */
+  int i;
+  vector float vf_result;
+
+  vf_result = __builtin_altivec_vrsqrtfp (vf_arg);
+
+  for (i = 0; i < 4; i++)
+    if (vf_expected_result[i] != vf_result[i])
+#if DEBUG
+      printf ("test_altivec_vrsqrtfp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
+	      i, vf_result[i], i, vf_expected_result[i]);
+#else
+    abort();
+#endif
+}
+
+void test_altivec_mask_for_load (const double *sh,
+				 vector signed char vsc_expected_result)
+{
+  int i;
+  vector signed char vsc_result;
+
+  vsc_result = __builtin_altivec_mask_for_load (sh);
+
+  for (i = 0; i < 16; i++)
+    if (vsc_expected_result[i] != vsc_result[i])
+#if DEBUG
+      printf ("test_altivec_mask_for_load: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n",
+	      i, vsc_result[i], i, vsc_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_altivec_vsel_1ti(vector signed __int128 vsq_arg1,
+			   vector signed __int128 vsq_arg2,
+			   vector unsigned __int128 vuq_arg3,
+			   vector signed __int128 vsc_expected_result)
+{
+  vector signed __int128 vsc_result;
+
+  vsc_result = __builtin_altivec_vsel_1ti (vsq_arg1, vsq_arg2, vuq_arg3);
+
+  if (vsc_expected_result[0] != vsc_result[0])
+    {  
+#if DEBUG
+       printf ("test_altivec_vsel_1ti: vsc_result = ");
+       printf(" (0x%llx%llx)",
+	      (unsigned long long)(vsc_result[0] >> 64),
+	      (unsigned long long)(vsc_result[0] & 0xFFFFFFFFFFFFFFFF));
+
+       printf (",  vsc_expected_result = ");
+       printf(" (0x%llx%llx)\n",
+	      (unsigned long long)(vsc_expected_result[0] >> 64),
+	      (unsigned long long)(vsc_expected_result[0]
+				   & 0xFFFFFFFFFFFFFFFF));
+#else
+	abort();
+#endif
+      }
+}
+
+void test_altivec_vsel_1ti_uns (vector unsigned __int128 vuq_arg1,
+				vector unsigned __int128 vuq_arg2,
+				vector unsigned __int128 vuq_arg3,
+				vector unsigned __int128 vuc_expected_result)
+{
+  vector unsigned __int128 vuc_result;
+
+  vuc_result = __builtin_altivec_vsel_1ti_uns (vuq_arg1, vuq_arg2, vuq_arg3);
+
+  if (vuc_expected_result[0] != vuc_result[0])
+    {
+#if DEBUG
+       printf ("test_altivec_vsel_1ti_uns: vuc_result = ");
+       printf(" (0x%llx%llx)",
+	      (unsigned long long)(vuc_result[0] >> 64),
+	      (unsigned long long)(vuc_result[0] & 0xFFFFFFFFFFFFFFFF));
+
+       printf (",  vuc_expected_result = ");
+       printf(" (0x%llx%llx)\n",
+	      (unsigned long long)(vuc_expected_result[0] >> 64),
+	      (unsigned long long)(vuc_expected_result[0]
+				   & 0xFFFFFFFFFFFFFFFF));
+#else
+	abort();
+#endif
+      }
+}
+
+void test_vec_init_v16qi (signed char sc_arg1, signed char sc_arg2,
+			  signed char sc_arg3, signed char sc_arg4,
+			  signed char sc_arg5, signed char sc_arg6,
+			  signed char sc_arg7, signed char sc_arg8,
+			  signed char sc_arg9, signed char sc_arg10,
+			  signed char sc_arg11, signed char sc_arg12,
+			  signed char sc_arg13, signed char sc_arg14,
+			  signed char sc_arg15, signed char sc_arg16,
+			  vector signed char vsc_expected_result)
+{
+  vector signed char vsc_result;
+  int i;
+
+  vsc_result = __builtin_vec_init_v16qi (sc_arg1, sc_arg2, sc_arg3, sc_arg4,
+					 sc_arg5, sc_arg6, sc_arg7, sc_arg8,
+					 sc_arg9, sc_arg10, sc_arg11, sc_arg12,
+					 sc_arg13, sc_arg14, sc_arg15,
+					 sc_arg16);
+
+  for (i = 0; i < 16; i++)
+    if (vsc_expected_result[i] != vsc_result[i])
+#if DEBUG
+      printf ("test_vec_init_v16qi: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n",
+	      i, vsc_result[i], i, vsc_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_vec_init_v4sf (float sf_arg1, float sf_arg2,
+			 float sf_arg3, float sf_arg4,
+			 vector float vf_expected_result)
+{
+  vector float vf_result;
+  int i;
+
+  vf_result = __builtin_vec_init_v4sf (sf_arg1, sf_arg2, sf_arg3, sf_arg4);
+
+  for (i = 0; i < 4; i++)
+    if (vf_expected_result[i] != vf_result[i])
+#if DEBUG
+      printf ("test_vec_init_v4sf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
+	      i, vf_result[i], i, vf_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_vec_init_v4si (int si_arg1, int si_arg2,
+			 int si_arg3, int si_arg4,
+			 vector signed int vsi_expected_result)
+{
+  vector signed int vsi_result;
+  int i;
+
+  vsi_result = __builtin_vec_init_v4si (si_arg1, si_arg2, si_arg3, si_arg4);
+
+  for (i = 0; i < 4; i++)
+    if (vsi_expected_result[i] != vsi_result[i])
+#if DEBUG
+      printf ("test_vec_init_v4si: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n",
+	      i, vsi_result[i], i, vsi_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_vec_init_v8hi (short int ss_arg1, short int ss_arg2,
+			 short int ss_arg3, short int ss_arg4,
+			 short int ss_arg5, short int ss_arg6,
+			 short int ss_arg7, short int ss_arg8,
+			 vector signed short int vss_expected_result)
+{
+  vector signed short int vss_result;
+  int i;
+
+  vss_result = __builtin_vec_init_v8hi (ss_arg1, ss_arg2, ss_arg3, ss_arg4,
+					ss_arg5, ss_arg6, ss_arg7, ss_arg8);
+
+  for (i = 0; i < 8; i++)
+    if (vss_expected_result[i] != vss_result[i])
+#if DEBUG
+      printf ("test_vec_init_v8hi: vss_result[%d] = %d, vss_expected_result[%d] = %d\n",
+	      i, vss_result[i], i, vss_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_vec_set_v16qi (vector signed char vsc_arg1,
+			 signed char sc_arg1,
+			 vector signed char vsc_expected_result)
+{
+  vector signed char vsc_result;
+  int i;
+
+  vsc_result = __builtin_vec_set_v16qi (vsc_arg1, sc_arg1, 3);
+
+  for (i = 0; i < 16; i++)
+    if (vsc_expected_result[i] != vsc_result[i])
+#if DEBUG
+      printf ("test_vec_set_v16qi: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n",
+	      i, vsc_result[i], i, vsc_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_vec_set_v4sf (vector float vsf_arg, float sf_arg1,
+			vector float vf_expected_result)
+{
+  vector float vf_result;
+  int i;
+
+  vf_result = __builtin_vec_set_v4sf (vsf_arg, sf_arg1, 0);
+
+  for (i = 0; i < 4; i++)
+    if (vf_expected_result[i] != vf_result[i])
+#if DEBUG
+      printf ("test_vec_init_v4sf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
+	      i, vf_result[i], i, vf_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_vec_set_v4si (vector int vsi_arg, int si_arg1,
+				 vector signed int vsi_expected_result)
+{
+  vector signed int vsi_result;
+  int i;
+
+  vsi_result = __builtin_vec_set_v4si (vsi_arg, si_arg1, 1);
+
+  for (i = 0; i < 4; i++)
+    if (vsi_expected_result[i] != vsi_result[i])
+#if DEBUG
+      printf ("test_vec_init_v4si: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n",
+	      i, vsi_result[i], i, vsi_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+void test_vec_set_v8hi (vector short int vss_arg, short int ss_arg,
+				 vector signed short int vss_expected_result)
+{
+  vector signed short int vss_result;
+  int i;
+
+  vss_result = __builtin_vec_set_v8hi (vss_arg, ss_arg, 2);
+
+  for (i = 0; i < 8; i++)
+    if (vss_expected_result[i] != vss_result[i])
+#if DEBUG
+      printf ("test_vec_init_v8hi: vss_result[%d] = %d, vss_expected_result[%d] = %d\n",
+	      i, vss_result[i], i, vss_expected_result[i]);
+#else
+      abort();
+#endif
+}
+
+int main ()
+{
+  signed int si_arg1, si_arg2, si_arg3, si_arg4;
+  vector signed int vsi_arg, vsi_expected_result;
+  vector unsigned int vui_arg, vui_expected_result;
+  vector float vf_arg, vf_expected_result;
+  vector signed char vsc_arg, vsc_expected_result;
+  vector signed __int128 vsq_arg1, vsq_arg2, vsq_expected_result;
+  vector unsigned __int128 vuq_arg1, vuq_arg2, vuq_arg3, vuq_expected_result;
+
+  signed char sc_arg1, sc_arg2, sc_arg3, sc_arg4, sc_arg5, sc_arg6, sc_arg7;
+  signed char sc_arg8, sc_arg9, sc_arg10, sc_arg11, sc_arg12, sc_arg13;
+  signed char sc_arg14, sc_arg15, sc_arg16;
+
+  signed short int ss_arg1, ss_arg2, ss_arg3, ss_arg4, ss_arg5, ss_arg6;
+  signed short int ss_arg7, ss_arg8;
+  vector signed short int vss_arg, vss_expected_result;
+  
+  float sf_arg1, sf_arg2, sf_arg3, sf_arg4;
+  
+  vf_arg = (vector float) {1.1, -2.2, 4.6, -6.9};
+
+  vsi_expected_result = (vector int) {1, -2, 4, -6};
+  test_altivec_fix_sfsi (vf_arg, vsi_expected_result);
+
+  vui_expected_result = (vector unsigned int) {1, 0, 4, 0};
+  test_altivec_fixuns_sfsi (vf_arg, vui_expected_result);
+
+  vsi_arg = (vector int) {-27, 33, 293, -123};
+  vf_expected_result = (vector float) {-27.0, 33.0, 293.0, -123.0};
+  test_altivec_float_sisf (vsi_arg, vf_expected_result);
+
+  vui_arg = (vector unsigned int) {27, 33, 293, 123};
+  vf_expected_result = (vector float) {27.0, 33.0, 293.0, 123.0};
+  test_altivec_uns_float_sisf (vui_arg, vf_expected_result);
+
+  vf_arg = (vector float) { 0.25, 0.01, 1.0, 64.0 };
+  vf_expected_result = (vector float) {2.0, 10.0, 1.0, 0.125};
+  test_altivec_vrsqrtfp (vf_arg, vf_expected_result);
+
+  vsc_expected_result = (vector signed char) {0x0F, 0x0E, 0x0D, 0x0C,
+					      0x0B, 0x0A, 0x09, 0x08,
+					      0x07, 0x06, 0x05, 0x04,
+					      0x03, 0x02, 0x01, 0x00};
+  /* NULL, Lower bits are zero so result will be case 0x0 of the lvsl inst. */
+  test_altivec_mask_for_load (NULL, vsc_expected_result);
+
+  vsq_arg1 = (vector signed __int128) {0x0123456789ABCDEF};
+  vsq_arg1 = (vsq_arg1 << 64) | (vector signed __int128) {0x0123456789ABCDEF};
+  vsq_arg2 = (vector signed __int128) {0xFEDCBA9876543210};
+  vsq_arg2 = (vsq_arg2 << 64) | (vector signed __int128) {0xFEDCBA9876543210};
+  vuq_arg3 = (vector unsigned __int128) {0xFFFF00000000FFFF};
+  vuq_arg3 = (vuq_arg3 << 64) |
+    (vector unsigned __int128) {0x0000FFFFFFFF0000};
+  vsq_expected_result = (vector signed __int128) {0xFEDC456789AB3210};
+  vsq_expected_result = (vsq_expected_result << 64)
+    | (vector signed __int128) {0x0123ba987654cdef};
+
+  test_altivec_vsel_1ti (vsq_arg1, vsq_arg2, vuq_arg3, vsq_expected_result);
+
+  vuq_arg1 = (vector unsigned __int128) {0x0123456789ABCDEF};
+  vuq_arg1 = (vuq_arg1 << 64)
+    | (vector unsigned __int128) {0x0123456789ABCDEF};
+  vuq_arg2 = (vector unsigned __int128) {0xFEDCBA9876543210};
+  vuq_arg2 = (vuq_arg2 << 64)
+    | (vector unsigned __int128) {0xFEDCBA9876543210};
+  vuq_arg3 = (vector unsigned __int128) {0xFFFF00000000FFFF};
+  vuq_arg3 = (vuq_arg3 << 64)
+    | (vector unsigned __int128) {0x0000FFFFFFFF0000};
+  vuq_expected_result = (vector unsigned __int128) {0xFEDC456789AB3210};
+  vuq_expected_result = (vuq_expected_result << 64)
+    | (vector unsigned __int128) {0x0123ba987654cdef};
+
+  test_altivec_vsel_1ti_uns (vuq_arg1, vuq_arg2, vuq_arg3,
+			     vuq_expected_result);
+
+  sc_arg1 = 1;
+  sc_arg2 = 2;
+  sc_arg3 = 3;
+  sc_arg4 = 4;
+  sc_arg5 = 5;
+  sc_arg6 = 6;
+  sc_arg7 = 7;
+  sc_arg8 = 8;
+  sc_arg9 = 9;
+  sc_arg10 = 10;
+  sc_arg11 = 11;
+  sc_arg12 = 12;
+  sc_arg13 = 13;
+  sc_arg14 = 14;
+  sc_arg15 = 15;
+  sc_arg16 = 16;
+  vsc_expected_result = (vector signed char) {0x1, 0x2, 0x3, 0x4, 0x5, 0x6,
+					      0x7, 0x8, 0x9, 0xA, 0xB, 0xC,
+					      0xD, 0xE, 0xf, 0x10};
+
+  test_vec_init_v16qi (sc_arg1, sc_arg2, sc_arg3, sc_arg4, sc_arg5,
+		       sc_arg6, sc_arg7, sc_arg8, sc_arg9, sc_arg10,
+		       sc_arg11, sc_arg12, sc_arg13, sc_arg14,
+		       sc_arg15, sc_arg16, vsc_expected_result);
+
+  sf_arg1 = 1.0;
+  sf_arg2 = 2.0;
+  sf_arg3 = 3.0;
+  sf_arg4 = 4.0;
+  vf_expected_result = (vector float) {1.0, 2.0, 3.0, 4.0};
+  test_vec_init_v4sf (sf_arg1, sf_arg2, sf_arg3, sf_arg4,
+		      vf_expected_result);
+
+  si_arg1 = 1;
+  si_arg2 = 2;
+  si_arg3 = 3;
+  si_arg4 = 4;
+  vsi_expected_result = (vector signed int) {1, 2, 3, 4};
+  test_vec_init_v4si (si_arg1, si_arg2, si_arg3, si_arg4,
+		      vsi_expected_result);
+
+  ss_arg1 = 1;
+  ss_arg2 = 2;
+  ss_arg3 = 3;
+  ss_arg4 = 4;
+  ss_arg5 = 5;
+  ss_arg6 = 6;
+  ss_arg7 = 7;
+  ss_arg8 = 8;
+  vss_expected_result = (vector signed short int) {1, 2, 3, 4, 5, 6, 7, 8};
+  test_vec_init_v8hi (ss_arg1, ss_arg2, ss_arg3, ss_arg4,
+		      ss_arg5, ss_arg6, ss_arg7, ss_arg8,
+		      vss_expected_result);
+
+  vsc_arg = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
+				  14, 15, 16};
+  sc_arg1 = 40;
+  vsc_expected_result = (vector signed char) {1, 2, 3, 40, 5, 6, 7, 8, 9,
+					      10, 11, 12, 13, 14, 15, 16};
+  test_vec_set_v16qi (vsc_arg, sc_arg1, vsc_expected_result);
+
+  vf_arg = (vector float) {1.0, 2.0, 3.0, 4.0};
+  sf_arg1 = 10.0;
+  vf_expected_result = (vector float) {10.0, 2.0, 3.0, 4.0};
+  test_vec_set_v4sf (vf_arg, sf_arg1, vf_expected_result);
+
+  vsi_arg = (vector signed int) {1, 2, 3, 4};
+  si_arg1 = 20;
+  vsi_expected_result = (vector signed int) {1, 20, 3, 4}; 
+  test_vec_set_v4si (vsi_arg, si_arg1, vsi_expected_result);
+
+  vss_arg = (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8};
+  ss_arg1 = 30;
+  vss_expected_result = (vector signed short) {1, 2, 30, 4, 5, 6, 7, 8}; 
+  test_vec_set_v8hi (vss_arg, ss_arg1, vss_expected_result);
+}
+
+/* { dg-final { scan-assembler-times "xvcvspsxws" 1 } } */
+/* { dg-final { scan-assembler-times "xvcvspuxws" 1 } } */
+/* { dg-final { scan-assembler-times "xvcvsxwsp" 1 } } */
+/* { dg-final { scan-assembler-times "xvcvuxwsp" 1 } } */
+/* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */
+/* { dg-final { scan-assembler-times "lvsl" 1 } } */
+/* { dg-final { scan-assembler-times "xxsel" 4 } } */
-- 
2.43.0

[PATCH 09/11] rs6000, add test cases for the vec_cmpne built-ins

[Carl Love]

GCC maintainers:

The patch adds test cases for the vec_cmpne of built-ins.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 
------------------------------------------------------------
rs6000, add test cases for the vec_cmpne built-ins

Add test cases for the signed int, unsigned it, signed short, unsigned
short, signed char and unsigned char built-ins.

Note, the built-ins are documented in the Power Vector Instrinsic
Programing reference manual.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vec-cmple.c: New test case.
	* gcc.target/powerpc/vec-cmple.h: New test case include file.
---
 gcc/testsuite/gcc.target/powerpc/vec-cmple.c | 35 ++++++++
 gcc/testsuite/gcc.target/powerpc/vec-cmple.h | 84 ++++++++++++++++++++
 2 files changed, 119 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-cmple.c
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-cmple.h

diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmple.c b/gcc/testsuite/gcc.target/powerpc/vec-cmple.c
new file mode 100644
index 00000000000..766a1c770e2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-cmple.c
@@ -0,0 +1,35 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+/* Test that the vec_cmpne builtin generates the expected Altivec
+   instructions.  */
+
+#include "vec-cmple.h"
+
+int main ()
+{
+  /* Note macro expansions for "signed long long int" and
+     "unsigned long long int" do not work for the vec_vsx_ld builtin.  */
+  define_test_functions (int, signed int, signed int, si);
+  define_test_functions (int, unsigned int, unsigned int, ui);
+  define_test_functions (short, signed short, signed short, ss);
+  define_test_functions (short, unsigned short, unsigned short, us);
+  define_test_functions (char, signed char, signed char, sc);
+  define_test_functions (char, unsigned char, unsigned char, uc);
+
+  define_init_verify_functions (int, signed int, signed int, si);
+  define_init_verify_functions (int, unsigned int, unsigned int, ui);
+  define_init_verify_functions (short, signed short, signed short, ss);
+  define_init_verify_functions (short, unsigned short, unsigned short, us);
+  define_init_verify_functions (char, signed char, signed char, sc);
+  define_init_verify_functions (char, unsigned char, unsigned char, uc);
+
+  execute_test_functions (int, signed int, signed int, si);
+  execute_test_functions (int, unsigned int, unsigned int, ui);
+  execute_test_functions (short, signed short, signed short, ss);
+  execute_test_functions (short, unsigned short, unsigned short, us);
+  execute_test_functions (char, signed char, signed char, sc);
+  execute_test_functions (char, unsigned char, unsigned char, uc);
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmple.h b/gcc/testsuite/gcc.target/powerpc/vec-cmple.h
new file mode 100644
index 00000000000..4126706b99a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-cmple.h
@@ -0,0 +1,84 @@
+#include "altivec.h"
+
+#define N 4096
+
+#include <stdio.h>
+void abort ();
+
+#define PRAGMA(X) _Pragma (#X)
+#define UNROLL0 PRAGMA (GCC unroll 0)
+
+#define define_test_functions(VBTYPE, RTYPE, STYPE, NAME)	\
+\
+RTYPE result_le_##NAME[N] __attribute__((aligned(16))); \
+STYPE operand1_##NAME[N] __attribute__((aligned(16))); \
+STYPE operand2_##NAME[N] __attribute__((aligned(16))); \
+RTYPE expected_##NAME[N] __attribute__((aligned(16))); \
+\
+__attribute__((noinline)) void vector_tests_##NAME () \
+{ \
+  vector STYPE v1_##NAME, v2_##NAME; \
+  vector bool VBTYPE tmp_##NAME; \
+  int i; \
+  UNROLL0 \
+  for (i = 0; i < N; i+=16/sizeof (STYPE))	\
+    { \
+      /* result_le = operand1!=operand2.  */ \
+      v1_##NAME = vec_vsx_ld (0, (const vector STYPE*)&operand1_##NAME[i]); \
+      v2_##NAME = vec_vsx_ld (0, (const vector STYPE*)&operand2_##NAME[i]); \
+\
+      tmp_##NAME = vec_cmple (v1_##NAME, v2_##NAME); \
+      vec_vsx_st (tmp_##NAME, 0, &result_le_##NAME[i]); \
+    } \
+}
+
+#define define_init_verify_functions(VBTYPE, RTYPE, STYPE, NAME)	\
+__attribute__((noinline)) void init_##NAME () \
+{ \
+  int i; \
+  for (i = 0; i < N; ++i) \
+    { \
+      result_le_##NAME[i] = 7; \
+      if (i%3 == 0) \
+	{ \
+	  /* op1 < op2.  */ \
+	  operand1_##NAME[i] = 1; \
+	  operand2_##NAME[i] = 2; \
+	} \
+      else if (i%3 == 1) \
+	{ \
+	  /* op1 > op2.  */ \
+	  operand1_##NAME[i] = 2; \
+	  operand2_##NAME[i] = 1; \
+	} \
+      else if (i%3 == 2) \
+	{ \
+	  /* op1 == op2.  */ \
+	  operand1_##NAME[i] = 3; \
+	  operand2_##NAME[i] = 3; \
+	} \
+      /* For vector comparisons: "For each element of the result_le, the \
+	  value of each bit is 1 if the corresponding elements of ARG1 and \
+	  ARG2 are equal." {or whatever the comparison is} "Otherwise, the \
+	  value of each bit is 0."  */ \
+    expected_##NAME[i] = -1 * (RTYPE)(operand1_##NAME[i] <= operand2_##NAME[i]); \
+  } \
+} \
+\
+__attribute__((noinline)) void verify_results_##NAME () \
+{ \
+  int i; \
+  for (i = 0; i < N; ++i) \
+    { \
+      if ( (result_le_##NAME[i] != expected_##NAME[i]) )		\
+	abort();							\
+    } \
+}
+
+#define execute_test_functions(VBTYPE, RTYPE, STYPE, NAME) \
+{ \
+  init_##NAME (); \
+  vector_tests_##NAME (); \
+  verify_results_##NAME (); \
+}
+
-- 
2.43.0

PATCH 10/11] rs6000, add test cases for __builtin_vec_init* and, __builtin_vec_set*

[Carl Love]

GCC maintainers:

The patch adds test cases for the __builtin_vec_init* and __builtin_vec_set* built-ins.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 
------------------------------------------------------------

rs6000, add test cases for __builtin_vec_init* and __builtin_vec_set*

Add test cases for the following built-ins:

__builtin_vec_init_v1ti
__builtin_vec_init_v2df
__builtin_vec_init_v2di
__builtin_vec_set_v1ti
__builtin_vec_set_v2df
__builtin_vec_set_v2di

Note, the above built-ins are documented in extend.texi.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vsx-builtin-21.c: New test file.
---
 .../gcc.target/powerpc/vsx-builtin-21.c       | 181 ++++++++++++++++++
 1 file changed, 181 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-21.c

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-21.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-21.c
new file mode 100644
index 00000000000..b7e1201f37e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-21.c
@@ -0,0 +1,181 @@
+/* { dg-do run { target int128 } } */
+/* { dg-require-effective-target vsx_hw } */
+/* { dg-options "-mvsx" } */
+
+/* This test should run the same on any target that supports vsx
+   instructions.  Intentionally not specifying cpu in order to test
+   all code generation paths.  */
+
+#define DEBUG 0
+
+#include <altivec.h>
+
+#if DEBUG
+#include <stdio.h>
+#include <stdlib.h>
+
+void print_i128 (__int128_t val)
+{
+  printf(" %lld %llu (0x%llx %llx)",
+	 (signed long long)(val >> 64),
+	 (unsigned long long)(val & 0xFFFFFFFFFFFFFFFF),
+	 (unsigned long long)(val >> 64),
+	 (unsigned long long)(val & 0xFFFFFFFFFFFFFFFF));
+}
+#endif
+
+void abort (void);
+
+void test_vec_init_v1ti (__int128_t ti_arg,
+			 vector __int128_t v1ti_expected_result)
+{
+  vector __int128_t v1ti_result;
+
+  v1ti_result = __builtin_vec_init_v1ti (ti_arg);
+  if (v1ti_result[0] != v1ti_expected_result[0])
+    {
+#if DEBUG
+       printf ("test_vec_init_v1ti: v1ti_result[0] = ");
+       print_i128 (v1ti_result[0]);
+       printf( "vf_expected_result[0] = ");
+       print_i128 (v1ti_expected_result[0]);
+       printf("\n");
+#else
+       abort();
+#endif
+    }
+}
+
+void test_vec_init_v2df (double d_arg1, double d_arg2,
+			 vector double v2df_expected_result)
+{
+  vector double v2df_result;
+  int i;
+
+  v2df_result = __builtin_vec_init_v2df (d_arg1, d_arg2);
+
+  for ( i= 0; i < 2; i++)
+    if (v2df_result[i] != v2df_expected_result[i])
+#if DEBUG
+      printf ("test_vec_init_v2df: v2df_result[%d] = %f, v2df_expected_result[%d] = %f\n",
+	      i, v2df_result[i], i, v2df_expected_result[i]);
+#else
+       abort();
+#endif
+}
+
+void test_vec_init_v2di (signed long long sl_arg1, signed long long sl_arg2,
+			 vector signed long long v2di_expected_result)
+{
+  vector signed long long v2di_result;
+  int i;
+
+  v2di_result = __builtin_vec_init_v2di (sl_arg1, sl_arg2);
+
+  for ( i= 0; i < 2; i++)
+    if (v2di_result[i] != v2di_expected_result[i])
+#if DEBUG
+      printf ("test_vec_init_v2di: v2di_result[%d] = %lld, v2df_expected_result[%d] = %lld\n",
+	      i, v2di_result[i], i, v2di_expected_result[i]);
+#else
+       abort();
+#endif
+}
+
+void test_vec_set_v1ti (vector __int128_t v1ti_arg, __int128_t ti_arg,
+			vector __int128_t v1ti_expected_result)
+{
+  vector __int128_t v1ti_result;
+
+  v1ti_result = __builtin_vec_set_v1ti (v1ti_arg, ti_arg, 0);
+  if (v1ti_result[0] != v1ti_expected_result[0])
+    {
+#if DEBUG
+       printf ("test_vec_set_v1ti: v1ti_result[0] = ");
+       print_i128 (v1ti_result[0]);
+       printf( "vf_expected_result[0] = ");
+       print_i128 (v1ti_expected_result[0]);
+       printf("\n");
+#else
+       abort();
+#endif
+    }
+}
+
+void test_vec_set_v2df (vector double v2df_arg, double d_arg,
+			vector double v2df_expected_result)
+{
+  vector double v2df_result;
+  int i;
+
+  v2df_result = __builtin_vec_set_v2df (v2df_arg, d_arg, 0);
+
+  for ( i= 0; i < 2; i++)
+    if (v2df_result[i] != v2df_expected_result[i])
+#if DEBUG
+      printf ("test_vec_set_v2df: v2df_result[%d] = %f, v2df_expected_result[%d] = %f\n",
+	      i, v2df_result[i], i, v2df_expected_result[i]);
+#else
+       abort();
+#endif
+}
+
+void test_vec_set_v2di (vector signed long long v2di_arg, signed long long sl_arg,
+			vector signed long long v2di_expected_result)
+{
+  vector signed long long v2di_result;
+  int i;
+
+  v2di_result = __builtin_vec_set_v2di (v2di_arg, sl_arg, 1);
+
+  for ( i= 0; i < 2; i++)
+    if (v2di_result[i] != v2di_expected_result[i])
+#if DEBUG
+      printf ("test_vec_set_v2di: v2di_result[%d] = %lld, v2df_expected_result[%d] = %lld\n",
+	      i, v2di_result[i], i, v2di_expected_result[i]);
+#else
+       abort();
+#endif
+}
+
+int main ()
+{
+  __int128_t ti_arg1;
+  vector __int128_t v1ti_arg1, v1ti_expected_result;
+  double d_arg1, d_arg2;
+  vector double v2df_arg1, v2df_expected_result;
+  signed long long sl_arg1, sl_arg2;
+  vector signed long long v2di_arg1, v2di_expected_result;
+
+  ti_arg1 = 123456789123456789;
+  ti_arg1 = (ti_arg1 << 64) | 123456789123456789;
+  v1ti_expected_result = (vector __int128_t) ti_arg1;
+  test_vec_init_v1ti (ti_arg1, v1ti_expected_result);
+
+  d_arg1 = 123456.2;
+  d_arg2 = 987654.4;
+  v2df_expected_result = (vector double) {123456.2, 987654.4};
+  test_vec_init_v2df (d_arg1, d_arg2, v2df_expected_result);
+  
+  sl_arg1 = 1234560;
+  sl_arg2 = 9876540;
+  v2di_expected_result = (vector signed long long) {1234560, 9876540};
+  test_vec_init_v2di (sl_arg1, sl_arg2, v2di_expected_result);
+
+  v1ti_arg1 = (vector __int128_t) {987654321987654321};
+  ti_arg1 = 12345678;
+  v1ti_expected_result = (vector __int128_t) {12345678};
+  test_vec_set_v1ti (v1ti_arg1, ti_arg1, v1ti_expected_result);
+
+  d_arg1 = 123.123;
+  v2df_arg1 = (vector double) {12345678.2, 987654.4};
+  v2df_expected_result = (vector double) {123.123, 987654.4};
+  test_vec_set_v2df (v2df_arg1, d_arg1, v2df_expected_result);
+  
+  sl_arg1 = 1234560;
+  v2di_arg1 = (vector signed long long) {123, 456};
+  v2di_expected_result = (vector signed long long) {123, 1234560};
+  test_vec_set_v2di (v2di_arg1, sl_arg1, v2di_expected_result);
+
+  return 0;
+}
-- 
2.43.0

PATCH 11/11] rs6000, make test vec-cmpne.c a runnable test

[Carl Love]

 GCC maintainers:

The patch changes the  vec-cmpne.c from a compile only test to a runnable test.  The macros to create the functions needed to test the built-ins and verify the restults are all there in the include file.  The .c file just needed to have the macro definitions inserted and change the header from compile to run.  The test can now do functional verification of the results in addition to verifying the expected instructions are generated.

The patch has been tested on Power 10 with no regressions.

Please let me know if this patch is acceptable for mainline.  Thanks.

                      Carl 
------------------------------------------------------------
rs6000, make test vec-cmpne.c a runnable test

The macros in vec-cmpne.h define test functions.  They also setup
test value functions, verification functions and execute test functions.
The test is setup as a compile only test so none of the verification and
execute functions are being used.

The patch adds the macro definitions to create the intialization,
verfiy and execute functions to a main program so not only can the
test verify the correct instructions are generated but also run the
tests and verify the results.  The test is then changed from a compile
to a run test.

gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/vec-cmple.c (main): Add main function with
	macro calls to define the test functions, create the verify
	functions and execute functions.
	Update scan-assembler-times (vcmpequ): Updated count to include
	instructions used to generate expected test results.
	* gcc.target/powerpc/vec-cmple.h (vector_tests_##NAME): Remove
	line continuation after closing bracket.  Remove extra blank line.
---
 gcc/testsuite/gcc.target/powerpc/vec-cmpne.c | 41 +++++++++++++++-----
 gcc/testsuite/gcc.target/powerpc/vec-cmpne.h |  3 +-
 2 files changed, 32 insertions(+), 12 deletions(-)

diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmpne.c b/gcc/testsuite/gcc.target/powerpc/vec-cmpne.c
index b57e0ac8638..2c369976a44 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-cmpne.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-cmpne.c
@@ -1,20 +1,41 @@
-/* { dg-do compile } */
+/* { dg-do run } */
 /* { dg-require-effective-target powerpc_altivec_ok } */
-/* { dg-options "-maltivec -O2" } */
+/* { dg-options "-maltivec -O2 -save-temps" } */
 
 /* Test that the vec_cmpne builtin generates the expected Altivec
    instructions.  */
 
 #include "vec-cmpne.h"
 
-define_test_functions (int, signed int, signed int, si);
-define_test_functions (int, unsigned int, unsigned int, ui);
-define_test_functions (short, signed short, signed short, ss);
-define_test_functions (short, unsigned short, unsigned short, us);
-define_test_functions (char, signed char, signed char, sc);
-define_test_functions (char, unsigned char, unsigned char, uc);
-define_test_functions (int, signed int, float, ff);
+int main ()
+{
+  define_test_functions (int, signed int, signed int, si);
+  define_test_functions (int, unsigned int, unsigned int, ui);
+  define_test_functions (short, signed short, signed short, ss);
+  define_test_functions (short, unsigned short, unsigned short, us);
+  define_test_functions (char, signed char, signed char, sc);
+  define_test_functions (char, unsigned char, unsigned char, uc);
+  define_test_functions (int, signed int, float, ff);
+
+  define_init_verify_functions (int, signed int, signed int, si);
+  define_init_verify_functions (int, unsigned int, unsigned int, ui);
+  define_init_verify_functions (short, signed short, signed short, ss);
+  define_init_verify_functions (short, unsigned short, unsigned short, us);
+  define_init_verify_functions (char, signed char, signed char, sc);
+  define_init_verify_functions (char, unsigned char, unsigned char, uc);
+  define_init_verify_functions (int, signed int, float, ff);
+
+  execute_test_functions (int, signed int, signed int, si);
+  execute_test_functions (int, unsigned int, unsigned int, ui);
+  execute_test_functions (short, signed short, signed short, ss);
+  execute_test_functions (short, unsigned short, unsigned short, us);
+  execute_test_functions (char, signed char, signed char, sc);
+  execute_test_functions (char, unsigned char, unsigned char, uc);
+  execute_test_functions (int, signed int, float, ff);
+
+  return 0;
+}
 
 /* { dg-final { scan-assembler-times {\mvcmpequb\M}  2 } } */
 /* { dg-final { scan-assembler-times {\mvcmpequh\M}  2 } } */
-/* { dg-final { scan-assembler-times {\mvcmpequw\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mvcmpequw\M}  32 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmpne.h b/gcc/testsuite/gcc.target/powerpc/vec-cmpne.h
index a304de01d86..374cca360b3 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-cmpne.h
+++ b/gcc/testsuite/gcc.target/powerpc/vec-cmpne.h
@@ -33,7 +33,7 @@ __attribute__((noinline)) void vector_tests_##NAME () \
       tmp_##NAME = vec_cmpne (v1_##NAME, v2_##NAME); \
       vec_vsx_st (tmp_##NAME, 0, &result_ne_##NAME[i]); \
     } \
-} \
+}
 
 #define define_init_verify_functions(VBTYPE, RTYPE, STYPE, NAME) \
 __attribute__((noinline)) void init_##NAME () \
@@ -80,7 +80,6 @@ __attribute__((noinline)) void verify_results_##NAME () \
     } \
 }
 
-
 #define execute_test_functions(VBTYPE, RTYPE, STYPE, NAME) \
 { \
   init_##NAME (); \
-- 
2.43.0

Re: [PATCH 01/11] rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins

[Kewen.Lin]

Hi,

on 2024/2/21 01:55, Carl Love wrote:
> 
> GCC maintainers:
> 
> This patch fixes the arguments and return type for the various __builtin_vsx_cmple* built-ins.  They were defined as signed but should have been defined as unsigned.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> 
> -----------------------------------------------------
> 
> rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins
> 
> The built-ins __builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u2di,
> __builtin_vsx_cmple_u4si and __builtin_vsx_cmple_u8hi should take
> unsigned arguments and return an unsigned result.  This patch changes
> the arguments and return type from signed to unsigned.

Apparently the types mismatch the corresponding bif names, but I wonder
if these __builtin_vsx_cmple* actually provide some value?

Users can just use vec_cmple as PVIPR defines, as altivec.h shows,
vec_cmple gets redefined with vec_cmpge, these are not for the underlying
implementation.  I also checked the documentation of openXL (xl compiler),
they don't support these either (these are not for compability).

So can we just remove these bifs?

> 
> The documentation for the signed and unsigned versions of
> __builtin_vsx_cmple is missing from extend.texi.  This patch adds the
> missing documentation.
> 
> Test cases are added for each of the signed and unsigned built-ins.
> 
> gcc/ChangeLog:
> 	* config/rs6000/rs6000-builtins.def (__builtin_vsx_cmple_u16qi,
> 	__builtin_vsx_cmple_u2di, __builtin_vsx_cmple_u4si): Change
> 	arguments and return from signed to unsigned.
> 	* doc/extend.texi (__builtin_vsx_cmple_16qi,
> 	__builtin_vsx_cmple_8hi, __builtin_vsx_cmple_4si,
> 	__builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u8hi,
> 	__builtin_vsx_cmple_u4si): Add documentation.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vsx-cmple.c: New test file.
> ---
>  gcc/config/rs6000/rs6000-builtins.def        |  10 +-
>  gcc/doc/extend.texi                          |  23 ++++
>  gcc/testsuite/gcc.target/powerpc/vsx-cmple.c | 127 +++++++++++++++++++
>  3 files changed, 155 insertions(+), 5 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> 
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index 3bc7fed6956..d66a53a0fab 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -1349,16 +1349,16 @@
>    const vss __builtin_vsx_cmple_8hi (vss, vss);
>      CMPLE_8HI vector_ngtv8hi {}
>  
> -  const vsc __builtin_vsx_cmple_u16qi (vsc, vsc);
> +  const vuc __builtin_vsx_cmple_u16qi (vuc, vuc);
>      CMPLE_U16QI vector_ngtuv16qi {}
>  
> -  const vsll __builtin_vsx_cmple_u2di (vsll, vsll);
> +  const vull __builtin_vsx_cmple_u2di (vull, vull);
>      CMPLE_U2DI vector_ngtuv2di {}
>  
> -  const vsi __builtin_vsx_cmple_u4si (vsi, vsi);
> +  const vui __builtin_vsx_cmple_u4si (vui, vui);
>      CMPLE_U4SI vector_ngtuv4si {}
>  
> -  const vss __builtin_vsx_cmple_u8hi (vss, vss);
> +  const vus __builtin_vsx_cmple_u8hi (vus, vus);
>      CMPLE_U8HI vector_ngtuv8hi {}
>  
>    const vd __builtin_vsx_concat_2df (double, double);
> @@ -1769,7 +1769,7 @@
>    const vf __builtin_vsx_xvcvuxdsp (vull);
>      XVCVUXDSP vsx_xvcvuxdsp {}
>  
> -  const vd __builtin_vsx_xvcvuxwdp (vsi);
> +  const vd __builtin_vsx_xvcvuxwdp (vui);
>      XVCVUXWDP vsx_xvcvuxwdp {}

This change is unexpected, it should not be in this sub-patch. :)

>  
>    const vf __builtin_vsx_xvcvuxwsp (vsi);
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 2b8ba1949bf..4d8610f6aa8 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -22522,6 +22522,29 @@ if the VSX instruction set is available.  The @samp{vec_vsx_ld} and
>  @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X},
>  @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
>  
> +
> +@smallexample
> +vector signed char __builtin_vsx_cmple_16qi (vector signed char,
> +                                             vector signed char);
> +vector signed short __builtin_vsx_cmple_8hi (vector signed short,
> +                                             vector signed short);
> +vector signed int __builtin_vsx_cmple_4si (vector signed int,
> +                                             vector signed int);
> +vector unsigned char __builtin_vsx_cmple_u16qi (vector unsigned char,
> +                                                vector unsigned char);
> +vector unsigned short __builtin_vsx_cmple_u8hi (vector unsigned short,
> +                                                vector unsigned short);
> +vector unsigned int __builtin_vsx_cmple_u4si (vector unsigned int,
> +                                              vector unsigned int);
> +@end smallexample

We don't document any vsx_cmp*, that's why I thought they acts as internal
implementation for the external interfaces vec_cmp*, but as mentioned above
these eight (missing 2 DI, so 6 here) ones are useless.

BR,
Kewen

> +
> +The builti-ins @code{__builtin_vsx_cmple_16qi}, @code{__builtin_vsx_cmple_8hi},
> +@code{__builtin_vsx_cmple_4si}, @code{__builtin_vsx_cmple_u16qi},
> +@code{__builtin_vsx_cmple_u8hi} and @code{__builtin_vsx_cmple_u4si} compare
> +vectors of their defined type.  The corresponding result element is set to
> +all ones if the two argument elements are less than or equal and all zeros
> +otherwise.
> +
>  @node PowerPC AltiVec Built-in Functions Available on ISA 2.07
>  @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07
>  
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> new file mode 100644
> index 00000000000..081817b4ba3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> @@ -0,0 +1,127 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-maltivec -O2 -save-temps" } */
> +
> +#define DEBUG 0
> +
> +#include <altivec.h>
> +
> +#if DEBUG
> +#include <stdio.h>
> +#include <stdlib.h>
> +#endif
> +
> +void abort (void);
> +
> +#if DEBUG
> +  #define ACTION(NAME, TYPE_NAME)                                         \
> +  printf ("test_vsx_cmple_%s: result_%s[%d] = 0x%x, expected_result_%s[%d] = 0x%x\n", \
> +  	  #NAME, #TYPE_NAME, i, result_##TYPE_NAME[i],                    \
> +  	  #TYPE_NAME, i, (int)expected_result_##TYPE_NAME[i]);
> +#else
> +  #define ACTION(NAME, TYPE_NAME)                                         \
> +  abort();
> +#endif
> +
> +#define TEST(NAME, TYPE, TYPE_NAME)					\
> +void test_vsx_cmple_##NAME (vector TYPE arg1_##TYPE_NAME,               \
> +			    vector TYPE arg2_##TYPE_NAME,               \
> +			    vector TYPE expected_result_##TYPE_NAME)    \
> +{                                                                       \
> +  vector TYPE result_##TYPE_NAME;					\
> +  int i, len = 16/sizeof(TYPE);						\
> +                                                                        \
> +  result_##TYPE_NAME = __builtin_vsx_cmple_##NAME (arg1_##TYPE_NAME,    \
> +						   arg2_##TYPE_NAME);   \
> +  for (i = 0; i < len; i++)                                             \
> +    if (result_##TYPE_NAME[i] != expected_result_##TYPE_NAME[i])        \
> +      ACTION(TYPE, TYPE_NAME)                                           \
> +}
> +
> +int main ()
> +{
> +
> +  vector signed char vsc_arg1, vsc_arg2, vsc_expected_result;
> +  vector signed short vsh_arg1, vsh_arg2, vsh_expected_result;
> +  vector signed int vsi_arg1, vsi_arg2, vsi_expected_result;
> +  vector signed long long vsll_arg1, vsll_arg2, vsll_expected_result;
> +  vector unsigned char vuc_arg1, vuc_arg2, vuc_expected_result;
> +  vector unsigned short vuh_arg1, vuh_arg2, vuh_expected_result;
> +  vector unsigned int vui_arg1, vui_arg2, vui_expected_result;
> +  vector unsigned long long vull_arg1, vull_arg2, vull_expected_result;
> +
> +  vsc_arg1 = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> +				   14, 15, 16};
> +  vsc_arg2 = (vector signed char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
> +				   21, 22, 23, 24, 25, 26};
> +  vsc_expected_result = (vector signed char) {0xFF, 0xFF, 0xFF, 0xFF,
> +					      0xFF, 0xFF, 0xFF, 0xFF,
> +					      0xFF, 0xFF, 0xFF, 0xFF,
> +					      0xFF, 0xFF, 0xFF, 0xFF};
> +  /* Test for __builtin_vsx_cmple_16qi */
> +  TEST (16qi, signed char, vsc)
> +  test_vsx_cmple_16qi (vsc_arg1, vsc_arg2, vsc_expected_result);
> +
> +  vsh_arg1 = (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8};
> +  vsh_arg2 = (vector signed short) {11, 12, 13, 14, 15, 16, 17, 18};
> +  vsh_expected_result = (vector signed short) {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
> +					       0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
> +  /* Test for __builtin_vsx_cmple_8hi */
> +  TEST (8hi, signed short, vsh)
> +  test_vsx_cmple_8hi (vsh_arg1, vsh_arg2, vsh_expected_result);
> +
> +  vsi_arg1 = (vector signed int) {1, 2, 3, 4};
> +  vsi_arg2 = (vector signed int) {11, 12, 13, 14};
> +  vsi_expected_result = (vector signed int) {0xFFFFFFFF, 0xFFFFFFFF,
> +					     0xFFFFFFFF, 0xFFFFFFFF};
> +  /* Test for __builtin_vsx_cmple_4si */
> +  TEST (4si, signed int, vsi)
> +  test_vsx_cmple_4si (vsi_arg1, vsi_arg2, vsi_expected_result);
> +
> +  vsll_arg1 = (vector signed long long) {1, 2};
> +  vsll_arg2 = (vector signed long long) {11, 12};
> +  vsll_expected_result = (vector signed long long) {0xFFFFFFFFFFFFFFFF,
> +						    0xFFFFFFFFFFFFFFFF};
> +  /* Test for __builtin_vsx_cmple_2di */
> +  TEST (2di, signed long long, vsll)
> +  test_vsx_cmple_2di (vsll_arg1, vsll_arg2, vsll_expected_result);
> +
> +  vuc_arg1 = (vector unsigned char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> +				     14, 15, 16};
> +  vuc_arg2 = (vector unsigned char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
> +				     22, 23, 24, 25, 26};
> +  vuc_expected_result = (vector unsigned char) {0xFF, 0xFF, 0xFF, 0xFF,
> +						0xFF, 0xFF, 0xFF, 0xFF,
> +						0xFF, 0xFF, 0xFF, 0xFF,
> +						0xFF, 0xFF, 0xFF, 0xFF};
> +  /* Test for __builtin_vsx_cmple_u16qi */
> +  TEST (u16qi, unsigned char, vuc)
> +  test_vsx_cmple_u16qi (vuc_arg1, vuc_arg2, vuc_expected_result);
> +
> +  vuh_arg1 = (vector unsigned short) {1, 2, 3, 4, 5, 6, 7, 8};
> +  vuh_arg2 = (vector unsigned short) {11, 12, 13, 14, 15, 16, 17, 18};
> +  vuh_expected_result = (vector unsigned short) {0xFFFF, 0xFFFF,
> +						 0xFFFF, 0xFFFF,
> +						 0xFFFF, 0xFFFF,
> +						 0xFFFF, 0xFFFF};
> +  /* Test for __builtin_vsx_cmple_u8hi */
> +  TEST (u8hi, unsigned short, vuh)
> +  test_vsx_cmple_u8hi (vuh_arg1, vuh_arg2, vuh_expected_result);
> +
> +  vui_arg1 = (vector unsigned int) {1, 2, 3, 4};
> +  vui_arg2 = (vector unsigned int) {11, 12, 13, 14};
> +  vui_expected_result = (vector unsigned int) {0xFFFFFFFF, 0xFFFFFFFF,
> +					       0xFFFFFFFF, 0xFFFFFFFF};
> +  /* Test for __builtin_vsx_cmple_u4si */
> +  TEST (u4si, unsigned int, vui)
> +  test_vsx_cmple_u4si (vui_arg1, vui_arg2, vui_expected_result);
> +
> +  vull_arg1 = (vector unsigned long long) {1, 2};
> +  vull_arg2 = (vector unsigned long long) {11, 12};
> +  vull_expected_result = (vector unsigned long long) {0xFFFFFFFFFFFFFFFF,
> +						      0xFFFFFFFFFFFFFFFF};
> +  /* Test for __builtin_vsx_cmple_u2di */
> +  TEST (u2di, unsigned long long, vull)
> +  test_vsx_cmple_u2di (vull_arg1, vull_arg2, vull_expected_result);
> +  return 0;
> +}

Re: [PATCH 02/11] rs6000, fix arguments, add documentation for vector, element conversions

[Kewen.Lin]

Hi,

on 2024/2/21 01:56, Carl Love wrote:
> 
> GCC maintainers:
> 
> This patch fixes the  return type for the __builtin_vsx_xvcvdpuxws and __builtin_vsx_xvcvspuxds built-ins.  They were defined as signed but should have been defined as unsigned.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> 
> -----------------------------------------------------
> rs6000, fix arguments, add documentation for vector element conversions
> 
> The return type for the __builtin_vsx_xvcvdpuxws, __builtin_vsx_xvcvspuxds,
> __builtin_vsx_xvcvspuxws built-ins should be unsigned.  This patch changes
> the return values from signed to unsigned.
> 
> The documentation for the vector element conversion built-ins:
> 
> __builtin_vsx_xvcvspsxws
> __builtin_vsx_xvcvspsxds
> __builtin_vsx_xvcvspuxds
> __builtin_vsx_xvcvdpsxws
> __builtin_vsx_xvcvdpuxws
> __builtin_vsx_xvcvdpuxds_uns
> __builtin_vsx_xvcvspdp
> __builtin_vsx_xvcvdpsp
> __builtin_vsx_xvcvspuxws
> __builtin_vsx_xvcvsxwdp
> __builtin_vsx_xvcvuxddp_uns
> __builtin_vsx_xvcvuxwdp
> 
> is missing from extend.texi.  This patch adds the missing documentation.

I think we should recommend users to adopt the recommended built-ins in
PVIPR, by checking the corresponding mnemonic in PVIPR, I got:

__builtin_vsx_xvcvspsxws -> vec_signed
__builtin_vsx_xvcvspsxds -> N/A
__builtin_vsx_xvcvspuxds -> N/A
__builtin_vsx_xvcvdpsxws -> vec_signed{e,o}
__builtin_vsx_xvcvdpuxws -> vec_unsigned{e,o}
__builtin_vsx_xvcvdpuxds_uns -> vec_unsigned
__builtin_vsx_xvcvspdp   -> vec_double{e,o}
__builtin_vsx_xvcvdpsp   -> vec_float{e,o}
__builtin_vsx_xvcvspuxws -> vec_unsigned
__builtin_vsx_xvcvsxwdp  -> vec_double{e,o}
__builtin_vsx_xvcvuxddp_uns> vec_double

For __builtin_vsx_xvcvspsxds and __builtin_vsx_xvcvspuxds which don't have
the according PVIPR built-ins, we can extend the current vec_{un,}signed{e,o}
to cover them and document them following the section mentioning PVIPR.

BR,
Kewen

> 
> This patch also adds runnable test cases for each of the built-ins.
> 
> gcc/ChangeLog:
> 	* config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvdpuxws,
> 	__builtin_vsx_xvcvspuxds, __builtin_vsx_xvcvspuxws): Change
> 	return type from signed to unsigned.
> 	* doc/extend.texi (__builtin_vsx_xvcvspsxws,
> 	__builtin_vsx_xvcvspsxds, __builtin_vsx_xvcvspuxds,
> 	__builtin_vsx_xvcvdpsxws, __builtin_vsx_xvcvdpuxws,
> 	__builtin_vsx_xvcvdpuxds_uns, __builtin_vsx_xvcvspdp,
> 	__builtin_vsx_xvcvdpsp, __builtin_vsx_xvcvspuxws,
> 	__builtin_vsx_xvcvsxwdp, __builtin_vsx_xvcvuxddp_uns,
> 	__builtin_vsx_xvcvuxwdp): Add documentation for builtins.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vsx-builtin-runnable-1.c: New test file.
> ---
>  gcc/config/rs6000/rs6000-builtins.def         |   6 +-
>  gcc/doc/extend.texi                           | 135 ++++++++++
>  .../powerpc/vsx-builtin-runnable-1.c          | 233 ++++++++++++++++++
>  3 files changed, 371 insertions(+), 3 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c
> 
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index d66a53a0fab..fd316f629e5 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -1724,7 +1724,7 @@
>    const vull __builtin_vsx_xvcvdpuxds_uns (vd);
>      XVCVDPUXDS_UNS vsx_fixuns_truncv2dfv2di2 {}
>  
> -  const vsi __builtin_vsx_xvcvdpuxws (vd);
> +  const vui __builtin_vsx_xvcvdpuxws (vd);
>      XVCVDPUXWS vsx_xvcvdpuxws {}
>  
>    const vd __builtin_vsx_xvcvspdp (vf);
> @@ -1736,10 +1736,10 @@
>    const vsi __builtin_vsx_xvcvspsxws (vf);
>      XVCVSPSXWS vsx_fix_truncv4sfv4si2 {}
>  
> -  const vsll __builtin_vsx_xvcvspuxds (vf);
> +  const vull __builtin_vsx_xvcvspuxds (vf);
>      XVCVSPUXDS vsx_xvcvspuxds {}
>  
> -  const vsi __builtin_vsx_xvcvspuxws (vf);
> +  const vui __builtin_vsx_xvcvspuxws (vf);
>      XVCVSPUXWS vsx_fixuns_truncv4sfv4si2 {}
>  
>    const vd __builtin_vsx_xvcvsxddp (vsll);
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 4d8610f6aa8..583b1d890bf 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -21360,6 +21360,141 @@ __float128 __builtin_sqrtf128 (__float128);
>  __float128 __builtin_fmaf128 (__float128, __float128, __float128);
>  @end smallexample
>  
> +@smallexample
> +vector int __builtin_vsx_xvcvspsxws (vector float);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvspsxws} converts the single precision floating
> +point vector element i to a signed single-precision integer value using
> +round to zero storing the result in element i.  If the source element is NaN
> +the result is set to 0x80000000 and VXCI is set to 1.  If the source
> +element is SNaN then VXSNAN is also set to 1.  If the rounded value is greater
> +than 2^31 - 1 the result is 0x7FFFFFFF and VXCVI is set to 1.  If the
> +rounded value is less than -2^31, the result is set to 0x80000000 and
> +VXCVI is set to 1. If the rounded result is inexact then XX is set to 1.
>> +@smallexample
> +vector signed long long int __builtin_vsx_xvcvspsxds (vector float);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvspsxds} converts the single precision floating
> +point vector element to a double precision signed integer value using the
> +round to zero rounding mode.  If the source element is NaN the result
> +is set to 0x8000000000000000 and VXCI is set to 1.  If the source element is
> +SNaN then VXSNAN is also set to 1.  If the rounded value is greater than
> +2^63 - 1 the result is 0x7FFFFFFFFFFFFFFF and VXCVI is set to 1.  If the
> +rounded value is less than zero, the result is set to 0x8000000000000000 and
> +VXCVI is set to 1.  If the rounded result is inexact then XX is set to 1.
> +
> +@smallexample
> +vector unsigned long long __builtin_vsx_xvcvspuxds (vector float);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvspuxds} converts the single precision floating
> +point vector element 2*i to an unsigned double-precision integer value using
> +round to zero storing the result in element i.  If the source element is NaN
> +the result is set to 0x0000000000000000 and VXCI is set to 1.  If the source
> +element is SNaN then VXSNAN is also set to 1.  If the rounded value is greater
> +than 2^63 - 1 the result is 0xFFFFFFFFFFFFFFFF and VXCVI is set to 1.  If the
> +rounded value is less than -2^63, the result is set to 0x0000000000000000 and
> +VXCVI is set to 1.  If the rounded result is inexact then XX is set to 1.
> +
> +@smallexample
> +vector signed int __builtin_vsx_xvcvdpsxws (vector double);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvdpsxws} converts the ith double precision floating
> +point vector element to a single-precision integer value using the round to
> +zero rounding mode.  The single precision integer value is placed into vector
> +elements j and j+1 where j = i*2.  If the source element is NaN the result
> +is set to 0x80000000 and VXCI is set to 1.  If the source element is SNaN then
> +VXSNAN is also set to 1.  If the rounded value is greater than 2^31 - 1 the
> +result is 0x7FFFFFFF and VXCVI is set to 1.  If the rounded value is less than
> +-2^31, the result is set to 0x80000000 and VXCVI is set to 1.  If the rounded
> +result is inexact then XX is set to 1.
> +
> +@smallexample
> +vector unsigned int __builtin_vsx_xvcvdpuxws (vector double);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvdpuxws} converts the ith double precision floating
> +point vector element to a unsigned single-precision integer value using the
> +round to zero rounding mode.  The single precision integer value is placed into
> +vector elements j and j+1 where j = i*2.  If the source element is NaN the
> +result is set to 0x00000000 and VXCI is set to 1.  If the source element is
> +SNaN then VXSNAN is also set to 1.  If the rounded value is greater than
> +2^31 - 1 the result is 0xFFFFFFFF and VXCVI is set to 1.  If the rounded value
> +is less than zero, the result is set to 0x00000000 and VXCVI is set to 1.  If
> +the rounded result is inexact then XX is set to 1.
> +
> +@smallexample
> +vector unsigned long long int __builtin_vsx_xvcvdpuxds_uns (vector double);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvdpuxds_uns} converts the double precision floating
> +point vector element to a double precision unsigned integer value using the
> +round to zero rounding mode.  If the source element is NaN the result is set
> +to 0x0000000000000000 and VXCI is set to 1.  If the source element is SNaN
> +then VXSNAN is also set to 1.  If the rounded value is greater than 2^63 - 1
> +the result is 0xFFFFFFFFFFFFFFFF and VXCVI is set to 1.  If the rounded value
> +is less than zero, the result is set to 0x0000000000000000 and VXCVI is set to
> +1.  If the rounded result is inexact then XX is set to 1.
> +
> +@smallexample
> +vector double __builtin_vsx_xvcvspdp (vector float);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvspdp} converts single precision floating
> +point vector element to a double precision floating point value.  Input element
> +at index 2*i is stored in the destination element i.
> +
> +@smallexample
> +vector float __builtin_vsx_xvcvdpsp (vector double);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvdpsp} converts the ith double precision floating
> +point vector element to a single-precision floating point value using the
> +rounding mode specified by RN.  The single precision value is placed into
> +vector elements j and j+1 where j = i*2.  The rounding mode, RN, is specified
> +by bits [62:63] of the FPSCR.
> +
> +@smallexample
> +vector unsigned int __builtin_vsx_xvcvspuxws (vector float);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvspuxws} converts the single precision floating
> +point vector element i to an unsigned single-precision integer value using
> +round to zero storing the result in element i.  If the source element is NaN
> +the result is set to 0x00000000 and VXCI is set to 1.  If the source element
> +is SNaN then VXSNAN is also set to 1.  If the rounded value is greater than
> +2^31 - 1 the result is 0xFFFFFFFF and VXCVI is set to 1.  If the rounded
> +value is less than -2^31, the result is set to 0x00000000 and VXCVI is set
> +to 1. If the rounded result is inexact then XX is set to 1.
> +
> +@smallexample
> +vector double __builtin_vsx_xvcvsxwdp (vector signed int);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvsxwdp} converts single precision integer value
> +to a double precision floating point value.  Input element at index 2*i is
> +stored in the destination element i.
> +
> +@smallexample
> +vector double __builtin_vsx_xvcvuxddp_uns (vector unsigned long long);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvuxddp_uns} converts unsigned double-precision
> +integer value to a double precision floating point value.  Input element
> +at index i is stored in the destination element i.
> +
> +@smallexample
> +vector double __builtin_vsx_xvcvuxwdp (vector unsigned int);
> +@end smallexample
> +
> +The @code{__builtin_vsx_xvcvuxwdp} converts single precision unsigned integer
> +value to a double precision floating point value.  Input element at index 2*i
> +is stored in the destination element i.
> +
>  @node Basic PowerPC Built-in Functions Available on ISA 2.07
>  @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07
>  
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c
> new file mode 100644
> index 00000000000..91d16c3ba72
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-1.c
> @@ -0,0 +1,233 @@
> +/* { dg-do run { target { lp64 } } } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power7" } */
> +
> +#define DEBUG 0
> +
> +#if DEBUG
> +#include <stdio.h>
> +#include <stdlib.h>
> +#endif
> +
> +void abort (void);
> +
> +int main ()
> +{
> +  int i;
> +  vector double vd_arg1, vd_result, vd_expected_result;
> +  vector float vf_arg1, vf_result, vf_expected_result;
> +  vector int vsi_arg1;
> +  vector unsigned int vui_arg1;
> +  vector int vsi_result, vsi_expected_result;
> +  vector unsigned int vui_result, vui_expected_result;
> +  vector signed long long int vsll_result, vsll_expected_result;
> +  vector unsigned long long int vull_arg1;
> +  vector unsigned long long int vull_result, vull_expected_result;
> +
> +  /* VSX Vector Convert with round to zero Single-Precision floating point to
> +     Single-Precision signed integer format using the round to zero mode.  */
> +
> +  vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234,
> +			    9999999999956789012345678.9};
> +  vsi_result = __builtin_vsx_xvcvspsxws (vf_arg1);
> +  vsi_expected_result = (vector signed int) {12345, 7654, -2, 0x7fffffff};
> +
> +  for (i = 0; i < 4; i++)
> +    if (vsi_result[i] != vsi_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvspsxws: vsi_result[%d] = 0x%x, vsi_expected_result[%d] = 0x%x\n",
> +	     i, vsi_result[i], i, vsi_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert with round Single-Precision floating point to
> +     Double-Precision signed integer format using the round to zero mode.  */
> +
> +  vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234,
> +			    9999999999956789012345678.9};
> +  vsll_result = __builtin_vsx_xvcvspsxds (vf_arg1);
> +  vsll_expected_result = (vector signed long long) {7654, 0x7fffffffffffffff};
> +
> +  for (i = 0; i < 2; i++)
> +    if (vsll_result[i] != vsll_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvspsxds: vsll_result[%d] = 0x%llx, vsll_expected_result[%d] = 0x%llx\n",
> +	     i, vsll_result[i], i, vsll_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert with round Single-Precision floating point to
> +     Double-Precision unsigned integer format using the round to zero mode.  */
> +
> +  vf_arg1 = (vector float) {12345.98, 764.321, -2.1234,
> +			    9999999999956789012345678.9};
> +  vull_result = __builtin_vsx_xvcvspuxds (vf_arg1);
> +  vull_expected_result = (vector unsigned long long) {764, 0xffffffffffffffff};
> +
> +  for (i = 0; i < 2; i++)
> +    if (vull_result[i] != vull_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvspuxds: vull_result[%d] = 0x%llx, vull_expected_result[%d] = 0x%llx\n",
> +	     i, vull_result[i], i, vull_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert with round Double-Precision floating point to
> +     signed Single-Precision integer format using the round to zero mode.  */
> +
> +  vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789};
> +  /* Each double-precision value, i, is converted to single precision integer
> +     and placed in vector elements j and j+1 where j = i*2.  The round to
> +     zero rounding mode is used.  */
> +  vsi_result = __builtin_vsx_xvcvdpsxws (vd_arg1);
> +  vsi_expected_result = (vector int) {12345, 12345, -2, -2};
> +
> +  for (i = 0; i < 4; i++)
> +    if (vsi_result[i] != vsi_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvdpsxws: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n",
> +	     i, vsi_result[i], i, vsi_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert with round Double-Precision floating point to
> +     unsigned Single-Precision integer format using the round to zero mode.  */
> +
> +  vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789};
> +  /* Each double-precision value, i, is converted to single precision integer
> +     and placed in vector elements j and j+1 where j = i*2.  The round to
> +     zero rounding mode is used.  */
> +  vui_result = __builtin_vsx_xvcvdpuxws (vd_arg1);
> +  vui_expected_result = (vector unsigned int) {12345, 12345, 0, 0};
> +
> +  for (i = 0; i < 4; i++)
> +    if (vui_result[i] != vui_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvdpuxws: vui_result[%d] = %d, vui_expected_result[%d] = %d\n",
> +	     i, vui_result[i], i, vui_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert with round Double-Precision floating point to
> +     Double-Precision unsigned integer format using the round to zero mode.  */
> +
> +  vd_arg1 = (vector double) {12345.987654321, -2.1234567890123456789};
> +  vull_result = __builtin_vsx_xvcvdpuxds_uns (vd_arg1);
> +  vull_expected_result = (vector unsigned long long) {12345, 0};
> +
> +  for (i = 0; i < 2; i++)
> +    if (vull_result[i] != vull_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvdpuxds_uns: vull_result[%d] = %lld, vull_expected_result[%d] = %lld\n",
> +	     i, vull_result[i], i, vull_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert Single-Precision floating point to Double-Precision
> +     floating point  */
> +
> +  vf_arg1 = (vector float) {12345.98, -2.0, 31.11, -55.5};
> +  vd_result = __builtin_vsx_xvcvspdp (vf_arg1);
> +  vd_expected_result = (vector double) {-2.0, -55.5};
> +
> +  for (i = 0; i < 2; i++)
> +    if (vd_result[i] != vd_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvspdp: vd_result[%d] = %f, vf_expected_result[%d] = %f\n",
> +	     i, vd_result[i], i, vd_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert with round Double-Precision float point format to
> +     Single-Precision floating point format using the rounding mode specified
> +     by the RN field of the FPSCR.  */
> +
> +  vd_arg1 = (vector double) {12345.12345, -0.1234567890123456789};
> +  /* Each double-precision value, i, is converted to single precision and
> +     placed in vector elements j and j+1 where j = i*2.  */
> +  vf_result = __builtin_vsx_xvcvdpsp (vd_arg1);
> +  vf_expected_result = (vector float) {12345.12345, 12345.12345,
> +				       -0.1234567890, -0.1234567890};
> +
> +  for (i = 0; i < 4; i++)
> +    if (vf_result[i] != vf_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvdpsp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
> +	     i, vf_result[i], i, vf_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert with round Single-Precision floating point to
> +     Single-Precision unsigned integer format using the round to zero mode.  */
> +
> +  vf_arg1 = (vector float) {12345.98, 7654.321, -2.1234,
> +			    9999999999956789012345678.9};
> +  vui_result = __builtin_vsx_xvcvspuxws (vf_arg1);
> +  vui_expected_result = (vector unsigned int) {12345, 7654, 0x0, 0xffffffff};
> +
> +  for (i = 0; i < 4; i++)
> +    if (vui_result[i] != vui_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvspuxws: vui_result[%d] = 0x%x, vui_expected_result[%d] = 0x%x\n",
> +	     i, vui_result[i], i, vui_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert Signed integer word to Double-Precision floating point
> +     format. */
> +
> +  vsi_arg1 = (vector int) {2345, 98, -2, -55};
> +  vd_result = __builtin_vsx_xvcvsxwdp (vsi_arg1);
> +  vd_expected_result = (vector double) {98.0, -55.0};
> +
> +  for (i = 0; i < 2; i++)
> +    if (vd_result[i] != vd_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvsxwdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n",
> +	     i, vd_result[i], i, vd_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert with round unsigned Double-Word integer to
> +     Double-Precision floating point format.  */
> +
> +  vull_arg1 = (vector unsigned long long) {12398, 22255};
> +  vd_result = __builtin_vsx_xvcvuxddp_uns (vull_arg1);
> +  vd_expected_result = (vector double) {12398.0, 22255.0};
> +
> +  for (i = 0; i < 2; i++)
> +    if (vd_result[i] != vd_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvuxddp_uns: vd_result[%d] = %f, vd_expected_result[%d] = %f\n",
> +	     i, vd_result[i], i, vd_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Convert unsigned Single-Precision integer to Double-Precision
> +     floating point format.  */
> +
> +  vui_arg1 = (vector unsigned int) {12398, 22255, 345, 87};
> +  vd_result = __builtin_vsx_xvcvuxwdp (vui_arg1);
> +  vd_expected_result = (vector double) {22255.0, 87.0};
> +
> +  for (i = 0; i < 2; i++)
> +    if (vd_result[i] != vd_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcvuxwdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n",
> +	     i, vd_result[i], i, vd_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +  return 0;
> +}

Re: [PATCH 03/11] rs6000, remove duplicated built-ins

[Kewen.Lin]

on 2024/2/21 01:56, Carl Love wrote:
> GCC maintainers:
> 
> There are a number of undocumented built-ins that are duplicates of other documented built-ins.  This patch removes the duplicates so users will only use the documented built-in.
> 
> The patch has been tested on Power 10 with no regressions.

Can you also test this on at least one BE machine?  The behaviors of some
built-ins may also depend on endianness.

> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> 
> -----------------------------------------------------
> 
> rs6000, remove duplicated built-ins
> 
> The following undocumented built-ins are same as existing documented
> overloaded builtins.
> 
>   const vf __builtin_vsx_xxmrghw (vf, vf);
> same as  vf __builtin_vec_mergeh (vf, vf);      (overloaded vec_mergeh)
> 
>   const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi);
> same as vsi __builtin_vec_mergeh (vsi, vsi);   (overloaded vec_mergeh)
> 
>   const vf __builtin_vsx_xxmrglw (vf, vf);
> same as vf __builtin_vec_mergel (vf, vf);      (overloaded vec_mergel)
> 
>   const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
> same as vsi __builtin_vec_mergel (vsi, vsi);   (overloaded vec_mergel)
> 

With these builtin definitions removed, the according expanders
vsx_xxmrg{h,l}w_v4s{f,i} look useless then, please have a check, if so,
they should be removed together, and put this part of changes into a
separated patch (mainly vec merge) ...


>   const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc);
> same as vsc __builtin_vec_sel (vsc, vsc, vuc);  (overloaded vec_sel)
> 
>   const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc);
> same as vuc __builtin_vec_sel (vuc, vuc, vuc);  (overloaded vec_sel)
> 
>   const vd __builtin_vsx_xxsel_2df (vd, vd, vd);
> same as  vd __builtin_vec_sel (vd, vd, vull);   (overloaded vec_sel)
> 
>   const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll);
> same as vsll __builtin_vec_sel (vsll, vsll, vsll);  (overloaded vec_sel)
> 
>   const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull);
> same as vull __builtin_vec_sel (vull, vull, vsll);  (overloaded vec_sel)
> 
>   const vf __builtin_vsx_xxsel_4sf (vf, vf, vf);
> same as vf __builtin_vec_sel (vf, vf, vsi)          (overloaded vec_sel)
> 
>   const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi);
> same as vsi __builtin_vec_sel (vsi, vsi, vbi);      (overloaded vec_sel)
> 
>   const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui);
> same as vui __builtin_vec_sel (vui, vui, vui);      (overloaded vec_sel)
> 
>   const vss __builtin_vsx_xxsel_8hi (vss, vss, vss);
> same as vss __builtin_vec_sel (vss, vss, vbs);      (overloaded vec_sel)
> 
>   const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus);
> same as vus __builtin_vec_sel (vus, vus, vus);      (overloaded vec_sel)

... and adopt another one for this part (vec_sel).

> 
> This patch removed the duplicate built-in definitions so only the
> documented built-ins will be available for use.  The case statements in
> rs6000_gimple_fold_builtin that ar no longer needed are also removed.
> 
> gcc/ChangeLog:
> 	* config/rs6000/rs6000-builtins.def (__builtin_vsx_xxmrghw,
> 	__builtin_vsx_xxmrghw_4si, __builtin_vsx_xxmrglw,
> 	__builtin_vsx_xxmrglw_4si, __builtin_vsx_xxsel_16qi,
> 	__builtin_vsx_xxsel_16qi_uns, __builtin_vsx_xxsel_2df,
> 	__builtin_vsx_xxsel_2di, __builtin_vsx_xxsel_2di_uns,
> 	__builtin_vsx_xxsel_4sf, __builtin_vsx_xxsel_4si,
> 	__builtin_vsx_xxsel_4si_uns, __builtin_vsx_xxsel_8hi,
> 	__builtin_vsx_xxsel_8hi_uns): Removed built-in definition.

Nit: s/Removed/Remove/

> 	* config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin):
> 	remove case entries RS6000_BIF_XXMRGLW_4SI,
> 	RS6000_BIF_XXMRGLW_4SF, RS6000_BIF_XXMRGHW_4SI,
> 	RS6000_BIF_XXMRGHW_4SF.

Nit: s/remove/Remove/

> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vsx-builtin-3.c (__builtin_vsx_xxsel_4si,
> 	__builtin_vsx_xxsel_8hi, __builtin_vsx_xxsel_16qi,
> 	__builtin_vsx_xxsel_4sf, __builtin_vsx_xxsel_2df): Remove test
> 	cases for removed built-ins.
> ---
>  gcc/config/rs6000/rs6000-builtin.cc           |  4 --
>  gcc/config/rs6000/rs6000-builtins.def         | 42 -------------------
>  .../gcc.target/powerpc/vsx-builtin-3.c        |  6 ---
>  3 files changed, 52 deletions(-)
> 
> diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
> index 6698274031b..e436cbe4935 100644
> --- a/gcc/config/rs6000/rs6000-builtin.cc
> +++ b/gcc/config/rs6000/rs6000-builtin.cc
> @@ -2110,20 +2110,16 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
>      /* vec_mergel (integrals).  */
>      case RS6000_BIF_VMRGLH:
>      case RS6000_BIF_VMRGLW:
> -    case RS6000_BIF_XXMRGLW_4SI:
>      case RS6000_BIF_VMRGLB:
>      case RS6000_BIF_VEC_MERGEL_V2DI:
> -    case RS6000_BIF_XXMRGLW_4SF:
>      case RS6000_BIF_VEC_MERGEL_V2DF:
>        fold_mergehl_helper (gsi, stmt, 1);
>        return true;
>      /* vec_mergeh (integrals).  */
>      case RS6000_BIF_VMRGHH:
>      case RS6000_BIF_VMRGHW:
> -    case RS6000_BIF_XXMRGHW_4SI:
>      case RS6000_BIF_VMRGHB:
>      case RS6000_BIF_VEC_MERGEH_V2DI:
> -    case RS6000_BIF_XXMRGHW_4SF:
>      case RS6000_BIF_VEC_MERGEH_V2DF:
>        fold_mergehl_helper (gsi, stmt, 0);
>        return true;
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index fd316f629e5..96d095da2cb 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -1925,18 +1925,6 @@
>    const signed int __builtin_vsx_xvtsqrtsp_fg (vf);
>      XVTSQRTSP_FG vsx_tsqrtv4sf2_fg {}
>  
> -  const vf __builtin_vsx_xxmrghw (vf, vf);
> -    XXMRGHW_4SF vsx_xxmrghw_v4sf {}
> -
> -  const vsi __builtin_vsx_xxmrghw_4si (vsi, vsi);
> -    XXMRGHW_4SI vsx_xxmrghw_v4si {}
> -
> -  const vf __builtin_vsx_xxmrglw (vf, vf);
> -    XXMRGLW_4SF vsx_xxmrglw_v4sf {}
> -
> -  const vsi __builtin_vsx_xxmrglw_4si (vsi, vsi);
> -    XXMRGLW_4SI vsx_xxmrglw_v4si {}
> -
>    const vsc __builtin_vsx_xxpermdi_16qi (vsc, vsc, const int<2>);
>      XXPERMDI_16QI vsx_xxpermdi_v16qi {}
>  
> @@ -1958,42 +1946,12 @@
>    const vss __builtin_vsx_xxpermdi_8hi (vss, vss, const int<2>);
>      XXPERMDI_8HI vsx_xxpermdi_v8hi {}
>  
> -  const vsc __builtin_vsx_xxsel_16qi (vsc, vsc, vsc);
> -    XXSEL_16QI vector_select_v16qi {}
> -
> -  const vuc __builtin_vsx_xxsel_16qi_uns (vuc, vuc, vuc);
> -    XXSEL_16QI_UNS vector_select_v16qi_uns {}
> -
>    const vsq __builtin_vsx_xxsel_1ti (vsq, vsq, vsq);
>      XXSEL_1TI vector_select_v1ti {}
>  
>    const vsq __builtin_vsx_xxsel_1ti_uns (vsq, vsq, vsq);
>      XXSEL_1TI_UNS vector_select_v1ti_uns {}
>  
> -  const vd __builtin_vsx_xxsel_2df (vd, vd, vd);
> -    XXSEL_2DF vector_select_v2df {}
> -
> -  const vsll __builtin_vsx_xxsel_2di (vsll, vsll, vsll);
> -    XXSEL_2DI vector_select_v2di {}
> -
> -  const vull __builtin_vsx_xxsel_2di_uns (vull, vull, vull);
> -    XXSEL_2DI_UNS vector_select_v2di_uns {}
> -
> -  const vf __builtin_vsx_xxsel_4sf (vf, vf, vf);
> -    XXSEL_4SF vector_select_v4sf {}
> -
> -  const vsi __builtin_vsx_xxsel_4si (vsi, vsi, vsi);
> -    XXSEL_4SI vector_select_v4si {}
> -
> -  const vui __builtin_vsx_xxsel_4si_uns (vui, vui, vui);
> -    XXSEL_4SI_UNS vector_select_v4si_uns {}
> -
> -  const vss __builtin_vsx_xxsel_8hi (vss, vss, vss);
> -    XXSEL_8HI vector_select_v8hi {}
> -
> -  const vus __builtin_vsx_xxsel_8hi_uns (vus, vus, vus);
> -    XXSEL_8HI_UNS vector_select_v8hi_uns {}
> -
>    const vsc __builtin_vsx_xxsldwi_16qi (vsc, vsc, const int<2>);
>      XXSLDWI_16QI vsx_xxsldwi_v16qi {}
>  
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
> index ff875c55304..10bf39b89ed 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c
> @@ -61,12 +61,6 @@ int do_sel(void)
>  {
>    int i = 0;
>  
> -  si[i][0] = __builtin_vsx_xxsel_4si (si[i][1], si[i][2], si[i][3]); i++;
> -  ss[i][0] = __builtin_vsx_xxsel_8hi (ss[i][1], ss[i][2], ss[i][3]); i++;
> -  sc[i][0] = __builtin_vsx_xxsel_16qi (sc[i][1], sc[i][2], sc[i][3]); i++;
> -  f[i][0] = __builtin_vsx_xxsel_4sf (f[i][1], f[i][2], f[i][3]); i++;
> -  d[i][0] = __builtin_vsx_xxsel_2df (d[i][1], d[i][2], d[i][3]); i++;
> -
>    si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], bi[i][3]); i++;
>    ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], bs[i][3]); i++;
>    sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], bc[i][3]); i++;

BR,
Kewen

Re: [PATCH 04/11] rs6000, Update comment for the __builtin_vsx_vper*, built-ins.

[Kewen.Lin]

Hi,

on 2024/2/21 01:56, Carl Love wrote:
> GCC maintainers:
> 
> The patch expands an existing comment to document that the duplicates are covered by an overloaded built-in.  I am wondering if we should just go ahead and remove the duplicates?

As the below comments Bill placed before, I think we should remove them, since
users should use the standard interface vec_perm which is defined by PVIPR.

They are not undocumented at all, in case some users are still using such builtins
they should switch to use vec_perm instead, so even if it's stage 4 now, it looks
still fine to drop them IMHO.

Segher & Peter, what do you think of this?

BR,
Kewen

> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> 
> -----------------------------------------------------
> rs6000, Update comment for the __builtin_vsx_vper* built-ins.
> 
> There is a comment about the __builtin_vsx_vper* built-ins being
> duplicates of the __builtin_altivec_* built-ins.  The note says we
> should consider deprecation/removeal of the __builtin_vsx_vper*.  Add a
> note that the _builtin_vsx_vper* built-ins are covered by the overloaded
> vec_perm built-ins which use the __builtin_altivec_* built-in definitions.
> 
> gcc/ChangeLog:
> 	* config/rs6000/rs6000-builtins.def ( __builtin_vsx_vperm_*):
> 	Add comment to existing comment about the built-ins.
> ---
>  gcc/config/rs6000/rs6000-builtins.def | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index 96d095da2cb..4c95429f137 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -1556,6 +1556,14 @@
>  ; These are duplicates of __builtin_altivec_* counterparts, and are being
>  ; kept for backwards compatibility.  The reason for their existence is
>  ; unclear.  TODO: Consider deprecation/removal at some point.
> +; Note, __builtin_vsx_vperm_16qi, __builtin_vsx_vperm_16qi_uns,
> +; __builtin_vsx_vperm_1ti, __builtin_vsx_vperm_v1ti_uns,
> +; __builtin_vsx_vperm_2df, __builtin_vsx_vperm_2di, __builtin_vsx_vperm_2di,
> +; __builtin_vsx_vperm_2di_uns, __builtin_vsx_vperm_4sf,
> +; __builtin_vsx_vperm_4si, __builtin_vsx_vperm_4si_uns,
> +; __builtin_vsx_vperm_8hi, __builtin_altivec_vperm_8hi_uns
> +; are all covered by the overloaded vec_perm built-in which uses the
> +; __builtin_altivec_* built-in definitions.
>    const vsc __builtin_vsx_vperm_16qi (vsc, vsc, vuc);
>      VPERM_16QI_X altivec_vperm_v16qi {}
>  

Re: [PATCH 05/11] rs6000, __builtin_vsx_xvneg[sp,dp] add documentation, and test cases

[Kewen.Lin]

Hi,

on 2024/2/21 01:56, Carl Love wrote:
> GCC maintainers:
> 
> The patch adds documentation and test cases for the __builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp built-ins.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> ------------------------------------------------------------
> rs6000, __builtin_vsx_xvneg[sp,dp] add documentation and test cases
> 
> Add documentation to the extend.texi file for the two built-ins
> __builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp.

I think these two are useless, the functionality has been covered by vec_neg
in PVIPR, so instead we should get rid of these definitions (bif def table,
test cases if there are some).

BR,
Kewen

> 
> Add test cases for the two built-ins.
> 
> gcc/ChangeLog:
> 	* doc/extend.texi (__builtin_vsx_xvnegsp, __builtin_vsx_xvnegdp):
> 	Add documentation.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vsx-builtin-runnable-2.c: New test case.
> ---
>  gcc/doc/extend.texi                           | 13 +++++
>  .../powerpc/vsx-builtin-runnable-2.c          | 51 +++++++++++++++++++
>  2 files changed, 64 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c
> 
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 583b1d890bf..83eed9e334b 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -21495,6 +21495,19 @@ The @code{__builtin_vsx_xvcvuxwdp} converts single precision unsigned integer
>  value to a double precision floating point value.  Input element at index 2*i
>  is stored in the destination element i.
>  
> +@smallexample
> +vector float __builtin_vsx_xvnegsp (vector float);
> +vector double __builtin_vsx_xvnegdp (vector double);
> +@end smallexample
> +
> +The  @code{__builtin_vsx_xvnegsp} and @code{__builtin_vsx_xvnegdp} negate each
> +vector element.
> +
> +@smallexample
> +vector __int128  __builtin_vsx_xxpermdi_1ti (vector __int128, vector __int128,
> +const int);
> +
> +@end smallexample
>  @node Basic PowerPC Built-in Functions Available on ISA 2.07
>  @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07
>  
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c
> new file mode 100644
> index 00000000000..7906a8e01d7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-2.c
> @@ -0,0 +1,51 @@
> +/* { dg-do run { target { lp64 } } } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power7" } */
> +
> +#define DEBUG 0
> +
> +#if DEBUG
> +#include <stdio.h>
> +#include <stdlib.h>
> +#endif
> +
> +void abort (void);
> +
> +int main ()
> +{
> +  int i;
> +  vector double vd_arg1, vd_result, vd_expected_result;
> +  vector float vf_arg1, vf_result, vf_expected_result;
> +
> +  /* VSX Vector Negate Single-Precision.  */
> +
> +  vf_arg1 = (vector float) {-1.0, 12345.98, -2.1234, 238.9};
> +  vf_result = __builtin_vsx_xvnegsp (vf_arg1);
> +  vf_expected_result = (vector float) {1.0, -12345.98, 2.1234, -238.9};
> +
> +  for (i = 0; i < 4; i++)
> +    if (vf_result[i] != vf_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvnegsp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
> +	     i, vf_result[i], i, vf_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* VSX Vector Negate Double-Precision.  */
> +
> +  vd_arg1 = (vector double) {12345.98, -2.1234};
> +  vd_result = __builtin_vsx_xvnegdp (vd_arg1);
> +  vd_expected_result = (vector double) {-12345.98, 2.1234};
> +
> +  for (i = 0; i < 2; i++)
> +    if (vd_result[i] != vd_expected_result[i])
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvnegdp: vd_result[%d] = %f, vd_expected_result[%d] = %f\n",
> +	     i, vd_result[i], i, vd_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +
> +  return 0;
> +}

Re: [PATCH 06/11] rs6000, __builtin_vsx_xxpermdi_1ti add documentation, and test case

[Kewen.Lin]

Hi Carl,

on 2024/2/21 01:57, Carl Love wrote:
> GCC maintainers:
> 
> The patch adds documentation and test case for the __builtin_vsx_xxpermdi_1ti built-in.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> ------------------------------------------------------------
> 
> rs6000, __builtin_vsx_xxpermdi_1ti add documentation and test case
> 
> Add documentation to the extend.texi file for the
> __builtin_vsx_xxpermdi_1ti built-in.

I think this one should be part of vec_xxpermdi (overload.def), we can
extend vec_xxpermdi by one more instance with type vsq, also update the
documentation on vec_xxpermdi for this newly introduced.

BR,
Kewen

> 
> Add test cases for the __builtin_vsx_xxpermdi_1ti built-in.
> 
> gcc/ChangeLog:
> 	* doc/extend.texi (__builtin_vsx_xxpermdi_1ti): Add documentation.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vsx-builtin-runnable-3.c: New test case.
> ---
>  gcc/doc/extend.texi                           |  7 +++
>  .../powerpc/vsx-builtin-runnable-3.c          | 48 +++++++++++++++++++
>  2 files changed, 55 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c
> 
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 83eed9e334b..22f67ebab31 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -21508,6 +21508,13 @@ vector __int128  __builtin_vsx_xxpermdi_1ti (vector __int128, vector __int128,
>  const int);
>  
>  @end smallexample
> +
> +The  @code{__builtin_vsx_xxpermdi_1ti} Let srcA[127:0] be the 128-bit first
> +argument and srcB[127:0] be the 128-bit second argument.  Let sel[1:0] be the
> +least significant bits of the const int argument (third input argument).  The
> +result bits [127:64] is srcB[127:64] if  sel[1] = 0, srcB[63:0] otherwise.  The
> +result bits [63:0] is srcA[127:64] if  sel[0] = 0, srcA[63:0] otherwise.
> +
>  @node Basic PowerPC Built-in Functions Available on ISA 2.07
>  @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.07
>  
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c
> new file mode 100644
> index 00000000000..ba287597cec
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-3.c
> @@ -0,0 +1,48 @@
> +/* { dg-do run { target { lp64 } } } */
> +/* { dg-require-effective-target powerpc_vsx_ok } */
> +/* { dg-options "-O2 -mdejagnu-cpu=power7" } */
> +
> +#include <altivec.h>
> +
> +#define DEBUG 0
> +
> +#if DEBUG
> +#include <stdio.h>
> +#include <stdlib.h>
> +#endif
> +
> +void abort (void);
> +
> +int main ()
> +{
> +  int i;
> +
> +  vector signed __int128 vsq_arg1, vsq_arg2, vsq_result, vsq_expected_result;
> +
> +  vsq_arg1[0] = (__int128) 0xFFFF0000FFFF0000;
> +  vsq_arg1[0] = vsq_arg1[0] << 64 | (__int128) 0xFFFF0000FFFF;
> +  vsq_arg2[0] = (__int128) 0x1100110011001100;
> +  vsq_arg2[0] = (vsq_arg2[0]  << 64) | (__int128) 0x1111000011110000;
> +
> +  vsq_expected_result[0] = (__int128) 0x1111000011110000;
> +  vsq_expected_result[0] = (vsq_expected_result[0] << 64)
> +    | (__int128) 0xFFFF0000FFFF0000;
> +
> +  vsq_result = __builtin_vsx_xxpermdi_1ti (vsq_arg1, vsq_arg2, 2);
> +
> +  if (vsq_result[0] != vsq_expected_result[0])
> +    {
> +#if DEBUG
> +       printf("ERROR, __builtin_vsx_xxpermdi_1ti: vsq_result = 0x%016llx %016llx\n",
> +	      (unsigned long long) (vsq_result[0] >> 64),
> +	      (unsigned long long) vsq_result[0]);
> +       printf("                         vsq_expected_resultd = 0x%016llx %016llx\n",
> +	      (unsigned long long)(vsq_expected_result[0] >> 64),
> +	      (unsigned long long) vsq_expected_result[0]);
> +#else
> +      abort();
> +#endif
> +     }
> +
> +  return 0;
> +}

Re: [PATCH 07/11] rs6000, __builtin_vsx_xvcmpeq[sp, dp, sp_p] add, documentation and test case

[Kewen.Lin]

Hi Carl,

on 2024/2/21 01:57, Carl Love wrote:
> 
>  GCC maintainers:
> 
> The patch adds documentation and test case for the  __builtin_vsx_xvcmpeq[sp, dp, sp_p] built-ins.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> ------------------------------------------------------------
> 
> rs6000, __builtin_vsx_xvcmpeq[sp, dp, sp_p] add documentation and test case
> 
> Add a test case for the __builtin_vsx_xvcmpeqsp_p built-in.
> 
> Add documentation for the __builtin_vsx_xvcmpeqsp_p,
> __builtin_vsx_xvcmpeqdp, and __builtin_vsx_xvcmpeqsp builtins.

1) for __builtin_vsx_xvcmpeqsp_p, its functionality has been already covered
by __builtin_altivec_vcmpeqfp_p which is a instance of __builtin_vec_vcmpeq_p,
so it's useless and removable.

2) for __builtin_vsx_xvcmpeqdp, it's a instance for overloaded PVIPR function
vec_cmpeq, it's unexpected to use it directly, so we don't need to document it.

3) for __builtin_vsx_xvcmpeqsp, it's duplicated of existing vec_cmpeq instance
__builtin_altivec_vcmpeqfp, so it's useless and removable.

BR,
Kewen

> 
> gcc/ChangeLog:
> 	* doc/extend.texi (__builtin_vsx_xvcmpeqsp_p,
> 	__builtin_vsx_xvcmpeqdp, __builtin_vsx_xvcmpeqsp): Add
> 	documentation.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vsx-builtin-runnable-4.c: New test case.
> ---
>  gcc/doc/extend.texi                           |  23 +++
>  .../powerpc/vsx-builtin-runnable-4.c          | 135 ++++++++++++++++++
>  2 files changed, 158 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c
> 
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 22f67ebab31..87fd30bfa9e 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -22700,6 +22700,18 @@ vectors of their defined type.  The corresponding result element is set to
>  all ones if the two argument elements are less than or equal and all zeros
>  otherwise.
>  
> +@smallexample
> +const vf __builtin_vsx_xvcmpeqsp (vf, vf);
> +const vd __builtin_vsx_xvcmpeqdp (vd, vd);
> +@end smallexample
> +
> +The builti-ins @code{__builtin_vsx_xvcmpeqdp} and
> +@code{__builtin_vsx_xvcmpeqdp} compare two floating point vectors and return
> +a vector.  If the corresponding elements are equal then the corresponding
> +vector element of the result is set to all ones, it is set to all zeros
> +otherwise.
> +
> +
>  @node PowerPC AltiVec Built-in Functions Available on ISA 2.07
>  @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07
>  
> @@ -23989,6 +24001,17 @@ is larger than 128 bits, the result is undefined.
>  The result is the modulo result of dividing the first input  by the second
>  input.
>  
> +@smallexample
> +const signed int __builtin_vsx_xvcmpeqdp_p (signed int, vd, vd);
> +@end smallexample
> +
> +The first argument of the builti-in @code{__builtin_vsx_xvcmpeqdp_p} is an
> +integer in the range of 0 to 1.  The second and third arguments are floating
> +point vectors to be compared.  The result is 1 if the first argument is a 1
> +and one or more of the corresponding vector elements are equal.  The result is
> +1 if the first argument is 0 and all of the corresponding vector elements are
> +not equal.  The result is zero otherwise.
> +
>  The following builtins perform 128-bit vector comparisons.  The
>  @code{vec_all_xx}, @code{vec_any_xx}, and @code{vec_cmpxx}, where @code{xx} is
>  one of the operations @code{eq, ne, gt, lt, ge, le} perform pairwise
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c
> new file mode 100644
> index 00000000000..8ac07c7c807
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-runnable-4.c
> @@ -0,0 +1,135 @@
> +/* { dg-do run { target { power10_hw } } } */
> +/* { dg-do link { target { ! power10_hw } } } */
> +/* { dg-options "-mdejagnu-cpu=power10 -O2 -save-temps" } */
> +/* { dg-require-effective-target power10_ok } */
> +
> +#define DEBUG 0
> +
> +#if DEBUG
> +#include <stdio.h>
> +#include <stdlib.h>
> +#endif
> +
> +void abort (void);
> +
> +int main ()
> +{
> +  int i;
> +  int result;
> +  vector float vf_arg1, vf_arg2;
> +  vector double d_arg1, d_arg2;
> +
> +  /* Compare vectors with one equal element, check
> +     for all elements unequal, i.e. first arg is 1.  */
> +  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  vf_arg2 = (vector float) {1.0, 3.0, 2.0, 8.0};
> +  result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2);
> +
> +#if DEBUG
> +  printf("result = 0x%x\n", (unsigned int) result);
> +#endif
> +
> +  if (result != 1)
> +    for (i = 0; i < 4; i++)
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 1: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n",
> +	     i, vf_arg1[i], i, vf_arg2[i]);
> +#else
> +      abort();
> +#endif
> +  /* Compare vectors with one equal element, check
> +     for all elements unequal, i.e. first arg is 0.  */
> +  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  vf_arg2 = (vector float) {1.0, 3.0, 2.0, 8.0};
> +  result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2);
> +
> +#if DEBUG
> +  printf("result = 0x%x\n", (unsigned int) result);
> +#endif
> +
> +  if (result != 0)
> +    for (i = 0; i < 4; i++)
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 2: arg 1 = 0, varg3[%d] = %f, varg3[%d] = %f\n",
> +	     i, vf_arg1[i], i, vf_arg2[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* Compare vectors with all unequal elements, check
> +     for all elements unequal, i.e. first arg is 1.  */
> +  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  vf_arg2 = (vector float) {8.0, 3.0, 2.0, 8.0};
> +  result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2);
> +
> +#if DEBUG
> +  printf("result = 0x%x\n", (unsigned int) result);
> +#endif
> +
> +  if (result != 0)
> +    for (i = 0; i < 4; i++)
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 3: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n",
> +	     i, vf_arg1[i], i, vf_arg2[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* Compare vectors with all unequal elements, check
> +     for all elements unequal, i.e. first arg is 0.  */
> +  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  vf_arg2 = (vector float) {8.0, 3.0, 2.0, 8.0};
> +  result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2);
> +
> +#if DEBUG
> +  printf("result = 0x%x\n", (unsigned int) result);
> +#endif
> +
> +  if (result != 1)
> +    for (i = 0; i < 4; i++)
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 4: arg 1 = 0, varg3[%d] = %f, varg3[%d] = %f\n",
> +	     i, vf_arg1[i], i, vf_arg2[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* Compare vectors with all equal elements, check
> +     for all elements equal, i.e. first arg is 1.  */
> +  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  vf_arg2 = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  result = __builtin_vsx_xvcmpeqsp_p (1, vf_arg1, vf_arg2);
> +
> +#if DEBUG
> +  printf("result = 0x%x\n", (unsigned int) result);
> +#endif
> +
> +  if (result != 1)
> +    for (i = 0; i < 4; i++)
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 5: arg 1 = 1, varg3[%d] = %f, varg3[%d] = %f\n",
> +	     i, vf_arg1[i], i, vf_arg2[i]);
> +#else
> +      abort();
> +#endif
> +
> +  /* Compare vectors with all equal elements, check
> +     for all elements unequal, i.e. first arg is 0.  */
> +  vf_arg1 = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  vf_arg2 = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  result = __builtin_vsx_xvcmpeqsp_p (0, vf_arg1, vf_arg2);
> +
> +#if DEBUG
> +  printf("result = 0x%x\n", (unsigned int) result);
> +#endif
> +
> +  if (result != 0)
> +    for (i = 0; i < 4; i++)
> +#if DEBUG
> +      printf("ERROR, __builtin_vsx_xvcmpeqsp_p 6: arg 0 = 1, varg3[%d] = %f, varg3[%d] = %f\n",
> +	     i, vf_arg1[i], i, vf_arg2[i]);
> +#else
> +      abort();
> +#endif
> +  return 0;
> +}

Re: [PATCH 09/11] rs6000, add test cases for the vec_cmpne built-ins

[Kewen.Lin]

Hi,

on 2024/2/21 01:57, Carl Love wrote:
> GCC maintainers:
> 
> The patch adds test cases for the vec_cmpne of built-ins.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> ------------------------------------------------------------
> rs6000, add test cases for the vec_cmpne built-ins

The subject and this subject line are saying "vec_cmpne" ...

> 
> Add test cases for the signed int, unsigned it, signed short, unsigned
> short, signed char and unsigned char built-ins.
> 
> Note, the built-ins are documented in the Power Vector Instrinsic
> Programing reference manual.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vec-cmple.c: New test case.
> 	* gcc.target/powerpc/vec-cmple.h: New test case include file.


... But I think you meant "vec_cmple".

> ---
>  gcc/testsuite/gcc.target/powerpc/vec-cmple.c | 35 ++++++++
>  gcc/testsuite/gcc.target/powerpc/vec-cmple.h | 84 ++++++++++++++++++++
>  2 files changed, 119 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-cmple.c
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-cmple.h
> 
> diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmple.c b/gcc/testsuite/gcc.target/powerpc/vec-cmple.c
> new file mode 100644
> index 00000000000..766a1c770e2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmple.c
> @@ -0,0 +1,35 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */

Should be "vmx_hw" for run test.

> +/* { dg-options "-maltivec -O2" } */
> +
> +/* Test that the vec_cmpne builtin generates the expected Altivec
> +   instructions.  */

It seems this file was copied from vec-cmpne.c?  As we have 
vec-cmpne-runnable.c, maybe we can rename it to vec-cmple-runnable.c.

And previously since we have vec-cmpne-runnable.c and vec-cmpne.c
to use vec-cmpne.h, so a header was introduced.  If you just want to
add one runnable test case, maybe just inline vec-cmple.h since
it's not used by others at all.

BR,
Kewen

> +
> +#include "vec-cmple.h"
> +
> +int main ()
> +{
> +  /* Note macro expansions for "signed long long int" and
> +     "unsigned long long int" do not work for the vec_vsx_ld builtin.  */
> +  define_test_functions (int, signed int, signed int, si);
> +  define_test_functions (int, unsigned int, unsigned int, ui);
> +  define_test_functions (short, signed short, signed short, ss);
> +  define_test_functions (short, unsigned short, unsigned short, us);
> +  define_test_functions (char, signed char, signed char, sc);
> +  define_test_functions (char, unsigned char, unsigned char, uc);
> +
> +  define_init_verify_functions (int, signed int, signed int, si);
> +  define_init_verify_functions (int, unsigned int, unsigned int, ui);
> +  define_init_verify_functions (short, signed short, signed short, ss);
> +  define_init_verify_functions (short, unsigned short, unsigned short, us);
> +  define_init_verify_functions (char, signed char, signed char, sc);
> +  define_init_verify_functions (char, unsigned char, unsigned char, uc);
> +
> +  execute_test_functions (int, signed int, signed int, si);
> +  execute_test_functions (int, unsigned int, unsigned int, ui);
> +  execute_test_functions (short, signed short, signed short, ss);
> +  execute_test_functions (short, unsigned short, unsigned short, us);
> +  execute_test_functions (char, signed char, signed char, sc);
> +  execute_test_functions (char, unsigned char, unsigned char, uc);
> +  return 0;
> +}
> diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmple.h b/gcc/testsuite/gcc.target/powerpc/vec-cmple.h
> new file mode 100644
> index 00000000000..4126706b99a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmple.h
> @@ -0,0 +1,84 @@
> +#include "altivec.h"
> +
> +#define N 4096
> +
> +#include <stdio.h>
> +void abort ();
> +
> +#define PRAGMA(X) _Pragma (#X)
> +#define UNROLL0 PRAGMA (GCC unroll 0)
> +
> +#define define_test_functions(VBTYPE, RTYPE, STYPE, NAME)	\
> +\
> +RTYPE result_le_##NAME[N] __attribute__((aligned(16))); \
> +STYPE operand1_##NAME[N] __attribute__((aligned(16))); \
> +STYPE operand2_##NAME[N] __attribute__((aligned(16))); \
> +RTYPE expected_##NAME[N] __attribute__((aligned(16))); \
> +\
> +__attribute__((noinline)) void vector_tests_##NAME () \
> +{ \
> +  vector STYPE v1_##NAME, v2_##NAME; \
> +  vector bool VBTYPE tmp_##NAME; \
> +  int i; \
> +  UNROLL0 \
> +  for (i = 0; i < N; i+=16/sizeof (STYPE))	\
> +    { \
> +      /* result_le = operand1!=operand2.  */ \
> +      v1_##NAME = vec_vsx_ld (0, (const vector STYPE*)&operand1_##NAME[i]); \
> +      v2_##NAME = vec_vsx_ld (0, (const vector STYPE*)&operand2_##NAME[i]); \
> +\
> +      tmp_##NAME = vec_cmple (v1_##NAME, v2_##NAME); \
> +      vec_vsx_st (tmp_##NAME, 0, &result_le_##NAME[i]); \
> +    } \
> +}
> +
> +#define define_init_verify_functions(VBTYPE, RTYPE, STYPE, NAME)	\
> +__attribute__((noinline)) void init_##NAME () \
> +{ \
> +  int i; \
> +  for (i = 0; i < N; ++i) \
> +    { \
> +      result_le_##NAME[i] = 7; \
> +      if (i%3 == 0) \
> +	{ \
> +	  /* op1 < op2.  */ \
> +	  operand1_##NAME[i] = 1; \
> +	  operand2_##NAME[i] = 2; \
> +	} \
> +      else if (i%3 == 1) \
> +	{ \
> +	  /* op1 > op2.  */ \
> +	  operand1_##NAME[i] = 2; \
> +	  operand2_##NAME[i] = 1; \
> +	} \
> +      else if (i%3 == 2) \
> +	{ \
> +	  /* op1 == op2.  */ \
> +	  operand1_##NAME[i] = 3; \
> +	  operand2_##NAME[i] = 3; \
> +	} \
> +      /* For vector comparisons: "For each element of the result_le, the \
> +	  value of each bit is 1 if the corresponding elements of ARG1 and \
> +	  ARG2 are equal." {or whatever the comparison is} "Otherwise, the \
> +	  value of each bit is 0."  */ \
> +    expected_##NAME[i] = -1 * (RTYPE)(operand1_##NAME[i] <= operand2_##NAME[i]); \
> +  } \
> +} \
> +\
> +__attribute__((noinline)) void verify_results_##NAME () \
> +{ \
> +  int i; \
> +  for (i = 0; i < N; ++i) \
> +    { \
> +      if ( (result_le_##NAME[i] != expected_##NAME[i]) )		\
> +	abort();							\
> +    } \
> +}
> +
> +#define execute_test_functions(VBTYPE, RTYPE, STYPE, NAME) \
> +{ \
> +  init_##NAME (); \
> +  vector_tests_##NAME (); \
> +  verify_results_##NAME (); \
> +}
> +

Re: PATCH 11/11] rs6000, make test vec-cmpne.c a runnable test

[Kewen.Lin]

Hi,

on 2024/2/21 01:58, Carl Love wrote:
>  GCC maintainers:
> 
> The patch changes the  vec-cmpne.c from a compile only test to a runnable test.  The macros to create the functions needed to test the built-ins and verify the restults are all there in the include file.  The .c file just needed to have the macro definitions inserted and change the header from compile to run.  The test can now do functional verification of the results in addition to verifying the expected instructions are generated.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> ------------------------------------------------------------
> rs6000, make test vec-cmpne.c a runnable test
> 
> The macros in vec-cmpne.h define test functions.  They also setup
> test value functions, verification functions and execute test functions.
> The test is setup as a compile only test so none of the verification and
> execute functions are being used.

But there is a test gcc/testsuite/gcc.target/powerpc/vec-cmpne-runnable.c
which aims to do the runtime verification.

BR,
Kewen

> 
> The patch adds the macro definitions to create the intialization,
> verfiy and execute functions to a main program so not only can the
> test verify the correct instructions are generated but also run the
> tests and verify the results.  The test is then changed from a compile
> to a run test.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vec-cmple.c (main): Add main function with
> 	macro calls to define the test functions, create the verify
> 	functions and execute functions.
> 	Update scan-assembler-times (vcmpequ): Updated count to include
> 	instructions used to generate expected test results.
> 	* gcc.target/powerpc/vec-cmple.h (vector_tests_##NAME): Remove
> 	line continuation after closing bracket.  Remove extra blank line.
> ---
>  gcc/testsuite/gcc.target/powerpc/vec-cmpne.c | 41 +++++++++++++++-----
>  gcc/testsuite/gcc.target/powerpc/vec-cmpne.h |  3 +-
>  2 files changed, 32 insertions(+), 12 deletions(-)
> 
> diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmpne.c b/gcc/testsuite/gcc.target/powerpc/vec-cmpne.c
> index b57e0ac8638..2c369976a44 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vec-cmpne.c
> +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmpne.c
> @@ -1,20 +1,41 @@
> -/* { dg-do compile } */
> +/* { dg-do run } */
>  /* { dg-require-effective-target powerpc_altivec_ok } */
> -/* { dg-options "-maltivec -O2" } */
> +/* { dg-options "-maltivec -O2 -save-temps" } */
>  
>  /* Test that the vec_cmpne builtin generates the expected Altivec
>     instructions.  */
>  
>  #include "vec-cmpne.h"
>  
> -define_test_functions (int, signed int, signed int, si);
> -define_test_functions (int, unsigned int, unsigned int, ui);
> -define_test_functions (short, signed short, signed short, ss);
> -define_test_functions (short, unsigned short, unsigned short, us);
> -define_test_functions (char, signed char, signed char, sc);
> -define_test_functions (char, unsigned char, unsigned char, uc);
> -define_test_functions (int, signed int, float, ff);
> +int main ()
> +{
> +  define_test_functions (int, signed int, signed int, si);
> +  define_test_functions (int, unsigned int, unsigned int, ui);
> +  define_test_functions (short, signed short, signed short, ss);
> +  define_test_functions (short, unsigned short, unsigned short, us);
> +  define_test_functions (char, signed char, signed char, sc);
> +  define_test_functions (char, unsigned char, unsigned char, uc);
> +  define_test_functions (int, signed int, float, ff);
> +
> +  define_init_verify_functions (int, signed int, signed int, si);
> +  define_init_verify_functions (int, unsigned int, unsigned int, ui);
> +  define_init_verify_functions (short, signed short, signed short, ss);
> +  define_init_verify_functions (short, unsigned short, unsigned short, us);
> +  define_init_verify_functions (char, signed char, signed char, sc);
> +  define_init_verify_functions (char, unsigned char, unsigned char, uc);
> +  define_init_verify_functions (int, signed int, float, ff);
> +
> +  execute_test_functions (int, signed int, signed int, si);
> +  execute_test_functions (int, unsigned int, unsigned int, ui);
> +  execute_test_functions (short, signed short, signed short, ss);
> +  execute_test_functions (short, unsigned short, unsigned short, us);
> +  execute_test_functions (char, signed char, signed char, sc);
> +  execute_test_functions (char, unsigned char, unsigned char, uc);
> +  execute_test_functions (int, signed int, float, ff);
> +
> +  return 0;
> +}
>  
>  /* { dg-final { scan-assembler-times {\mvcmpequb\M}  2 } } */
>  /* { dg-final { scan-assembler-times {\mvcmpequh\M}  2 } } */
> -/* { dg-final { scan-assembler-times {\mvcmpequw\M}  2 } } */
> +/* { dg-final { scan-assembler-times {\mvcmpequw\M}  32 } } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/vec-cmpne.h b/gcc/testsuite/gcc.target/powerpc/vec-cmpne.h
> index a304de01d86..374cca360b3 100644
> --- a/gcc/testsuite/gcc.target/powerpc/vec-cmpne.h
> +++ b/gcc/testsuite/gcc.target/powerpc/vec-cmpne.h
> @@ -33,7 +33,7 @@ __attribute__((noinline)) void vector_tests_##NAME () \
>        tmp_##NAME = vec_cmpne (v1_##NAME, v2_##NAME); \
>        vec_vsx_st (tmp_##NAME, 0, &result_ne_##NAME[i]); \
>      } \
> -} \
> +}
>  
>  #define define_init_verify_functions(VBTYPE, RTYPE, STYPE, NAME) \
>  __attribute__((noinline)) void init_##NAME () \
> @@ -80,7 +80,6 @@ __attribute__((noinline)) void verify_results_##NAME () \
>      } \
>  }
>  
> -
>  #define execute_test_functions(VBTYPE, RTYPE, STYPE, NAME) \
>  { \
>    init_##NAME (); \

Re: [PATCH 01/11] rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins

[Carl Love]

Kewen:

Thanks for the review.  From the review, it looks like a few of the built-ins just need to be replaced with an overloaded version of an existing PVPIR documented buit-in.  Most of the rest can just be removed.  I will work on redoing the patch set accordingly.  We can then look at the new patch set after stage 4 is over.

                       Carl 

On 2/20/24 09:55, Carl Love wrote:
> 
> GCC maintainers:
> 
> This patch fixes the arguments and return type for the various __builtin_vsx_cmple* built-ins.  They were defined as signed but should have been defined as unsigned.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> 
> -----------------------------------------------------
> 
> rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins
> 
> The built-ins __builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u2di,
> __builtin_vsx_cmple_u4si and __builtin_vsx_cmple_u8hi should take
> unsigned arguments and return an unsigned result.  This patch changes
> the arguments and return type from signed to unsigned.
> 
> The documentation for the signed and unsigned versions of
> __builtin_vsx_cmple is missing from extend.texi.  This patch adds the
> missing documentation.
> 
> Test cases are added for each of the signed and unsigned built-ins.
> 
> gcc/ChangeLog:
> 	* config/rs6000/rs6000-builtins.def (__builtin_vsx_cmple_u16qi,
> 	__builtin_vsx_cmple_u2di, __builtin_vsx_cmple_u4si): Change
> 	arguments and return from signed to unsigned.
> 	* doc/extend.texi (__builtin_vsx_cmple_16qi,
> 	__builtin_vsx_cmple_8hi, __builtin_vsx_cmple_4si,
> 	__builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u8hi,
> 	__builtin_vsx_cmple_u4si): Add documentation.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/vsx-cmple.c: New test file.
> ---
>  gcc/config/rs6000/rs6000-builtins.def        |  10 +-
>  gcc/doc/extend.texi                          |  23 ++++
>  gcc/testsuite/gcc.target/powerpc/vsx-cmple.c | 127 +++++++++++++++++++
>  3 files changed, 155 insertions(+), 5 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> 
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index 3bc7fed6956..d66a53a0fab 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -1349,16 +1349,16 @@
>    const vss __builtin_vsx_cmple_8hi (vss, vss);
>      CMPLE_8HI vector_ngtv8hi {}
>  
> -  const vsc __builtin_vsx_cmple_u16qi (vsc, vsc);
> +  const vuc __builtin_vsx_cmple_u16qi (vuc, vuc);
>      CMPLE_U16QI vector_ngtuv16qi {}
>  
> -  const vsll __builtin_vsx_cmple_u2di (vsll, vsll);
> +  const vull __builtin_vsx_cmple_u2di (vull, vull);
>      CMPLE_U2DI vector_ngtuv2di {}
>  
> -  const vsi __builtin_vsx_cmple_u4si (vsi, vsi);
> +  const vui __builtin_vsx_cmple_u4si (vui, vui);
>      CMPLE_U4SI vector_ngtuv4si {}
>  
> -  const vss __builtin_vsx_cmple_u8hi (vss, vss);
> +  const vus __builtin_vsx_cmple_u8hi (vus, vus);
>      CMPLE_U8HI vector_ngtuv8hi {}
>  
>    const vd __builtin_vsx_concat_2df (double, double);
> @@ -1769,7 +1769,7 @@
>    const vf __builtin_vsx_xvcvuxdsp (vull);
>      XVCVUXDSP vsx_xvcvuxdsp {}
>  
> -  const vd __builtin_vsx_xvcvuxwdp (vsi);
> +  const vd __builtin_vsx_xvcvuxwdp (vui);
>      XVCVUXWDP vsx_xvcvuxwdp {}
>  
>    const vf __builtin_vsx_xvcvuxwsp (vsi);
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 2b8ba1949bf..4d8610f6aa8 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -22522,6 +22522,29 @@ if the VSX instruction set is available.  The @samp{vec_vsx_ld} and
>  @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X},
>  @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
>  
> +
> +@smallexample
> +vector signed char __builtin_vsx_cmple_16qi (vector signed char,
> +                                             vector signed char);
> +vector signed short __builtin_vsx_cmple_8hi (vector signed short,
> +                                             vector signed short);
> +vector signed int __builtin_vsx_cmple_4si (vector signed int,
> +                                             vector signed int);
> +vector unsigned char __builtin_vsx_cmple_u16qi (vector unsigned char,
> +                                                vector unsigned char);
> +vector unsigned short __builtin_vsx_cmple_u8hi (vector unsigned short,
> +                                                vector unsigned short);
> +vector unsigned int __builtin_vsx_cmple_u4si (vector unsigned int,
> +                                              vector unsigned int);
> +@end smallexample
> +
> +The builti-ins @code{__builtin_vsx_cmple_16qi}, @code{__builtin_vsx_cmple_8hi},
> +@code{__builtin_vsx_cmple_4si}, @code{__builtin_vsx_cmple_u16qi},
> +@code{__builtin_vsx_cmple_u8hi} and @code{__builtin_vsx_cmple_u4si} compare
> +vectors of their defined type.  The corresponding result element is set to
> +all ones if the two argument elements are less than or equal and all zeros
> +otherwise.
> +
>  @node PowerPC AltiVec Built-in Functions Available on ISA 2.07
>  @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07
>  
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> new file mode 100644
> index 00000000000..081817b4ba3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> @@ -0,0 +1,127 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-maltivec -O2 -save-temps" } */
> +
> +#define DEBUG 0
> +
> +#include <altivec.h>
> +
> +#if DEBUG
> +#include <stdio.h>
> +#include <stdlib.h>
> +#endif
> +
> +void abort (void);
> +
> +#if DEBUG
> +  #define ACTION(NAME, TYPE_NAME)                                         \
> +  printf ("test_vsx_cmple_%s: result_%s[%d] = 0x%x, expected_result_%s[%d] = 0x%x\n", \
> +  	  #NAME, #TYPE_NAME, i, result_##TYPE_NAME[i],                    \
> +  	  #TYPE_NAME, i, (int)expected_result_##TYPE_NAME[i]);
> +#else
> +  #define ACTION(NAME, TYPE_NAME)                                         \
> +  abort();
> +#endif
> +
> +#define TEST(NAME, TYPE, TYPE_NAME)					\
> +void test_vsx_cmple_##NAME (vector TYPE arg1_##TYPE_NAME,               \
> +			    vector TYPE arg2_##TYPE_NAME,               \
> +			    vector TYPE expected_result_##TYPE_NAME)    \
> +{                                                                       \
> +  vector TYPE result_##TYPE_NAME;					\
> +  int i, len = 16/sizeof(TYPE);						\
> +                                                                        \
> +  result_##TYPE_NAME = __builtin_vsx_cmple_##NAME (arg1_##TYPE_NAME,    \
> +						   arg2_##TYPE_NAME);   \
> +  for (i = 0; i < len; i++)                                             \
> +    if (result_##TYPE_NAME[i] != expected_result_##TYPE_NAME[i])        \
> +      ACTION(TYPE, TYPE_NAME)                                           \
> +}
> +
> +int main ()
> +{
> +
> +  vector signed char vsc_arg1, vsc_arg2, vsc_expected_result;
> +  vector signed short vsh_arg1, vsh_arg2, vsh_expected_result;
> +  vector signed int vsi_arg1, vsi_arg2, vsi_expected_result;
> +  vector signed long long vsll_arg1, vsll_arg2, vsll_expected_result;
> +  vector unsigned char vuc_arg1, vuc_arg2, vuc_expected_result;
> +  vector unsigned short vuh_arg1, vuh_arg2, vuh_expected_result;
> +  vector unsigned int vui_arg1, vui_arg2, vui_expected_result;
> +  vector unsigned long long vull_arg1, vull_arg2, vull_expected_result;
> +
> +  vsc_arg1 = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> +				   14, 15, 16};
> +  vsc_arg2 = (vector signed char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
> +				   21, 22, 23, 24, 25, 26};
> +  vsc_expected_result = (vector signed char) {0xFF, 0xFF, 0xFF, 0xFF,
> +					      0xFF, 0xFF, 0xFF, 0xFF,
> +					      0xFF, 0xFF, 0xFF, 0xFF,
> +					      0xFF, 0xFF, 0xFF, 0xFF};
> +  /* Test for __builtin_vsx_cmple_16qi */
> +  TEST (16qi, signed char, vsc)
> +  test_vsx_cmple_16qi (vsc_arg1, vsc_arg2, vsc_expected_result);
> +
> +  vsh_arg1 = (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8};
> +  vsh_arg2 = (vector signed short) {11, 12, 13, 14, 15, 16, 17, 18};
> +  vsh_expected_result = (vector signed short) {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF,
> +					       0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
> +  /* Test for __builtin_vsx_cmple_8hi */
> +  TEST (8hi, signed short, vsh)
> +  test_vsx_cmple_8hi (vsh_arg1, vsh_arg2, vsh_expected_result);
> +
> +  vsi_arg1 = (vector signed int) {1, 2, 3, 4};
> +  vsi_arg2 = (vector signed int) {11, 12, 13, 14};
> +  vsi_expected_result = (vector signed int) {0xFFFFFFFF, 0xFFFFFFFF,
> +					     0xFFFFFFFF, 0xFFFFFFFF};
> +  /* Test for __builtin_vsx_cmple_4si */
> +  TEST (4si, signed int, vsi)
> +  test_vsx_cmple_4si (vsi_arg1, vsi_arg2, vsi_expected_result);
> +
> +  vsll_arg1 = (vector signed long long) {1, 2};
> +  vsll_arg2 = (vector signed long long) {11, 12};
> +  vsll_expected_result = (vector signed long long) {0xFFFFFFFFFFFFFFFF,
> +						    0xFFFFFFFFFFFFFFFF};
> +  /* Test for __builtin_vsx_cmple_2di */
> +  TEST (2di, signed long long, vsll)
> +  test_vsx_cmple_2di (vsll_arg1, vsll_arg2, vsll_expected_result);
> +
> +  vuc_arg1 = (vector unsigned char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> +				     14, 15, 16};
> +  vuc_arg2 = (vector unsigned char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21,
> +				     22, 23, 24, 25, 26};
> +  vuc_expected_result = (vector unsigned char) {0xFF, 0xFF, 0xFF, 0xFF,
> +						0xFF, 0xFF, 0xFF, 0xFF,
> +						0xFF, 0xFF, 0xFF, 0xFF,
> +						0xFF, 0xFF, 0xFF, 0xFF};
> +  /* Test for __builtin_vsx_cmple_u16qi */
> +  TEST (u16qi, unsigned char, vuc)
> +  test_vsx_cmple_u16qi (vuc_arg1, vuc_arg2, vuc_expected_result);
> +
> +  vuh_arg1 = (vector unsigned short) {1, 2, 3, 4, 5, 6, 7, 8};
> +  vuh_arg2 = (vector unsigned short) {11, 12, 13, 14, 15, 16, 17, 18};
> +  vuh_expected_result = (vector unsigned short) {0xFFFF, 0xFFFF,
> +						 0xFFFF, 0xFFFF,
> +						 0xFFFF, 0xFFFF,
> +						 0xFFFF, 0xFFFF};
> +  /* Test for __builtin_vsx_cmple_u8hi */
> +  TEST (u8hi, unsigned short, vuh)
> +  test_vsx_cmple_u8hi (vuh_arg1, vuh_arg2, vuh_expected_result);
> +
> +  vui_arg1 = (vector unsigned int) {1, 2, 3, 4};
> +  vui_arg2 = (vector unsigned int) {11, 12, 13, 14};
> +  vui_expected_result = (vector unsigned int) {0xFFFFFFFF, 0xFFFFFFFF,
> +					       0xFFFFFFFF, 0xFFFFFFFF};
> +  /* Test for __builtin_vsx_cmple_u4si */
> +  TEST (u4si, unsigned int, vui)
> +  test_vsx_cmple_u4si (vui_arg1, vui_arg2, vui_expected_result);
> +
> +  vull_arg1 = (vector unsigned long long) {1, 2};
> +  vull_arg2 = (vector unsigned long long) {11, 12};
> +  vull_expected_result = (vector unsigned long long) {0xFFFFFFFFFFFFFFFF,
> +						      0xFFFFFFFFFFFFFFFF};
> +  /* Test for __builtin_vsx_cmple_u2di */
> +  TEST (u2di, unsigned long long, vull)
> +  test_vsx_cmple_u2di (vull_arg1, vull_arg2, vull_expected_result);
> +  return 0;
> +}

Re: [PATCH 08/11] rs6000, add tests and documentation for various, built-ins

[Kewen.Lin]

Hi,

on 2024/2/21 01:57, Carl Love wrote:
>  
>  GCC maintainers:
> 
> The patch adds documentation a number of built-ins.
> 
> The patch has been tested on Power 10 with no regressions.
> 
> Please let me know if this patch is acceptable for mainline.  Thanks.
> 
>                       Carl 
> ------------------------------------------------------------
>  rs6000, add tests and documentation for various built-ins
> 
> This patch adds a test case and documentation in extend.texi for the
> following built-ins:
> 
> __builtin_altivec_fix_sfsi
> __builtin_altivec_fixuns_sfsi
> __builtin_altivec_float_sisf
> __builtin_altivec_uns_float_sisf

I think these are covered by vec_{unsigned,signed,float}, could you
have a check?

> __builtin_altivec_vrsqrtfp

Similar to that __builtin_altivec_vrsqrtefp is covered by vec_rsqrte,
this is already covered by vec_rsqrt, which has the vf instance
__builtin_vsx_xvrsqrtsp, so this one is useless and removable.


> __builtin_altivec_mask_for_load

This one is for internal use, I don't think we want to document it in
user manual.

> __builtin_altivec_vsel_1ti
> __builtin_altivec_vsel_1ti_uns

I think we can extend the existing vec_sel for vsq and vuq, also update
the documentation.

> __builtin_vec_init_v16qi
> __builtin_vec_init_v4sf
> __builtin_vec_init_v4si
> __builtin_vec_init_v8hi

There are more vec_init variants __builtin_vec_init_{v2df,v2di,v1ti},
any reasons not include them here? ...

> __builtin_vec_set_v16qi
> __builtin_vec_set_v4sf
> __builtin_vec_set_v4si
> __builtin_vec_set_v8hi

... and some similar variants for this one?

it seems that users can just use something like:

  vector ... = {x, y} ...

for the vector initialization and something like:

  vector ... z;
  z[0] = ...;
  z[i] = ...;

for the vector set.  Can you check if there are some
differences between the above style and builtin? (both
BE and LE).  And the historical reasons for adding them?

If we really need them, I'd like to see we just have
the according overload function like vec_init and vec_set
instead of exposing the instances with different suffixes.

BR,
Kewen

> 
> gcc/ChangeLog:
> 	* doc/extend.texi (__builtin_altivec_fix_sfsi,
> 	__builtin_altivec_fixuns_sfsi, __builtin_altivec_float_sisf,
> 	__builtin_altivec_uns_float_sisf, __builtin_altivec_vrsqrtfp,
> 	__builtin_altivec_mask_for_load, __builtin_altivec_vsel_1ti,
> 	__builtin_altivec_vsel_1ti_uns, __builtin_vec_init_v16qi,
> 	__builtin_vec_init_v4sf, __builtin_vec_init_v4si,
> 	__builtin_vec_init_v8hi, __builtin_vec_set_v16qi,
> 	__builtin_vec_set_v4sf, __builtin_vec_set_v4si,
> 	__builtin_vec_set_v8hi): Add documentation.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/powerpc/altivec-38.c: New test case.
> ---
>  gcc/doc/extend.texi                           |  98 ++++
>  gcc/testsuite/gcc.target/powerpc/altivec-38.c | 503 ++++++++++++++++++
>  2 files changed, 601 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/powerpc/altivec-38.c
> 
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 87fd30bfa9e..89d0a1f77b0 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -22678,6 +22678,104 @@ if the VSX instruction set is available.  The @samp{vec_vsx_ld} and
>  @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
>  
>  
> +@smallexample
> +vector signed int __builtin_altivec_fix_sfsi (vector float);
> +vector signed int __builtin_altivec_fixuns_sfsi (vector float);
> +vector float __builtin_altivec_float_sisf (vector int);
> +vector float __builtin_altivec_uns_float_sisf (vector int);
> +vector float __builtin_altivec_vrsqrtfp (vector float);
> +@end smallexample
> +
> +The @code{__builtin_altivec_fix_sfsi} converts a vector of single precision
> +floating point values to a vector of signed integers with round to zero.
> +
> +The @code{__builtin_altivec_fixuns_sfsi} converts a vector of single precision
> +floating point values to a vector of unsigned integers with round to zero.  If
> +the rounded floating point value is less then 0 the result is 0 and VXCVI
> +is set to 1.
> +
> +The @code{__builtin_altivec_float_sisf} converts a vector of single precision
> +signed integers to a vector of floating point values using the rounding mode
> +specified by RN.
> +
> +The @code{__builtin_altivec_uns_float_sisf} converts a vector of single
> +precision unsigned integers to a vector of floating point values using the
> +rounding mode specified by RN.
> +
> +The @code{__builtin_altivec_vrsqrtfp} returns a vector of floating point
> +estimates of the reciprical square root of each floating point source vector
> +element.
> +
> +@smallexample
> +vector signed char test_altivec_mask_for_load (const void *);
> +@end smallexample
> +
> +The @code{__builtin_altivec_vrsqrtfp} returns a vector mask based on the
> +bottom four bits of the argument.  Let X be the 32-byte value:
> +0x00 || 0x01 || 0x02 || ... || 0x1D || 0x1E || 0x1F.
> +Bytes sh to sh+15 are returned where sh is given by the least significant 4
> +bit of the argument. See description of lvsl, lvsr instructions.
> +
> +@smallexample
> +vector signed __int128 __builtin_altivec_vsel_1ti (vector signed __int128,
> +                                                   vector signed __int128,
> +                                                   vector unsigned __int128);
> +vector unsigned __int128
> +  __builtin_altivec_vsel_1ti_uns (vector unsigned __int128,
> +                                  vector unsigned __int128,
> +                                  vector unsigned __int128)
> +@end smallexample
> +
> +Let the arguments of @code{__builtin_altivec_vsel_1ti} and
> +@code{__builtin_altivec_vsel_1ti_uns} be src1, src2, mask.  The result is
> +given by (src1 & ~mask) | (src2 & mask).
> +
> +@smallexample
> +vector signed char
> +__builtin_vec_init_v16qi (signed char, signed char, signed char, signed char,
> +                          signed char, signed char, signed char, signed char,
> +                          signed char, signed char, signed char, signed char,
> +                          signed char, signed char, signed char, signed char);
> +
> +vector short int __builtin_vec_init_v8hi (short int, short int, short int,
> +                                          short int, short int, short int,
> +                                          short int, short int);
> +vector signed int __builtin_vec_init_v4si (signed int, signed int, signed int,
> +                                           signed int);
> +vector float __builtin_vec_init_v4sf (float, float, float, float);
> +vector __int128 __builtin_vec_init_v1ti (signed __int128);
> +vector double __builtin_vec_init_v2df (double, double);
> +vector signed long long __builtin_vec_init_v2di (signed long long,
> +                                                 signed long long);
> +@end smallexample
> +
> +The builti-ins @code{__builtin_vec_init_v16qi}, @code{__builtin_vec_init_v8hi},
> +@code{__builtin_vec_init_v4si}, @code{__builtin_vec_init_v4sf},
> +@code{__builtin_vec_init_v1ti}, @code{__builtin_vec_init_v2df} and
> +@code{__builtin_vec_init_v2di} return a
> +vector corresponding to the argument type initialized with the value of the
> +arguments.
> +
> +@smallexample
> +vector signed char __builtin_vec_set_v16qi (vector signed char, signed char,
> +                                            const int);
> +vector short int __builtin_vec_set_v8hi (vector short int, short int,
> +                                         const int);
> +vector signed int __builtin_vec_set_v4si (vector signed int, signed int,
> +                                          const int);
> +vector float __builtin_vec_set_v4sf (vector float, float, const int);
> +vector __int128 __builtin_vec_set_v1ti (vector __int128, __int128, const int);
> +vector double __builtin_vec_set_v2dfi (vector double, double, const int);
> +vector signed long long __builtin_vec_set_v2dfi (vector signed long long,
> +                                                 signed long long, const int);
> +@end smallexample
> +
> +The builti-ins @code{__builtin_vec_set_v16qi}, @code{__builtin_vec_set_v8hi},
> +@code{__builtin_vec_set_v4si}, @code{__builtin_vec_set_v4sf},
> +@code{__builtin_vec_set_v1ti},  @code{__builtin_vec_set_v2dfi} and
> +@code{__builtin_vec_set_v2dfi} return the input source vector with the element
> +indexed by the const int replaced by the scalar argument.
> +
>  @smallexample
>  vector signed char __builtin_vsx_cmple_16qi (vector signed char,
>                                               vector signed char);
> diff --git a/gcc/testsuite/gcc.target/powerpc/altivec-38.c b/gcc/testsuite/gcc.target/powerpc/altivec-38.c
> new file mode 100644
> index 00000000000..01330e67110
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/altivec-38.c
> @@ -0,0 +1,503 @@
> +/* { dg-do run { target powerpc*-*-* } } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-O2 -save-temps" } */
> +
> +#define DEBUG 0
> +
> +#include <altivec.h>
> +#include <stddef.h>
> +
> +#if DEBUG
> +#include <stdio.h>
> +#include <stdlib.h>
> +#endif
> +
> +void abort (void);
> +
> +void test_altivec_fix_sfsi (vector float vf_arg,
> +			    vector int vsi_expected_result)
> +{
> +  int i;
> +  vector signed int vsi_result;
> +
> +  vsi_result = __builtin_altivec_fix_sfsi (vf_arg);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vsi_expected_result[i] != vsi_result[i])
> +#if DEBUG
> +      printf ("test_altivec_fix_sfsi: vsi_result[%d] = %i, vsi_expected_result[%d] = %d\n",
> +	      i, vsi_result[i], i, vsi_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_altivec_fixuns_sfsi (vector float vf_arg,
> +			       vector unsigned int vui_expected_result)
> +{
> +  int i;
> +  vector unsigned int vui_result;
> +
> +  vui_result = __builtin_altivec_fixuns_sfsi (vf_arg);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vui_expected_result[i] != vui_result[i])
> +#if DEBUG
> +      printf ("test_altivec_fixuns_sfsi: vui_result[%d] = %i, vsi_expected_result[%d] = %d\n",
> +		i, vui_result[i], i, vui_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_altivec_float_sisf (vector signed int vsi_arg,
> +			      vector float vf_expected_result)
> +{
> +  int i;
> +  vector float vf_result;
> +
> +  vf_result = __builtin_altivec_float_sisf (vsi_arg);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vf_expected_result[i] != vf_result[i])
> +#if DEBUG
> +      printf ("test_altivec_float_sisf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
> +		i, vf_result[i], i, vf_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_altivec_uns_float_sisf (vector unsigned int vui_arg,
> +				  vector float vf_expected_result)
> +{
> +  int i;
> +  vector float vf_result;
> +
> +  vf_result = __builtin_altivec_uns_float_sisf (vui_arg);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vf_expected_result[i] != vf_result[i])
> +#if DEBUG
> +      printf ("test_altivec_uns_float_sisf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
> +	      i, vf_result[i], i, vf_expected_result[i]);
> +#else
> +    abort();
> +#endif
> +}
> +
> +void test_altivec_vrsqrtfp (vector float vf_arg,
> +			    vector float vf_expected_result)
> +{
> +  /* Compute the reciprical of the square root of each vector element.  */
> +  int i;
> +  vector float vf_result;
> +
> +  vf_result = __builtin_altivec_vrsqrtfp (vf_arg);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vf_expected_result[i] != vf_result[i])
> +#if DEBUG
> +      printf ("test_altivec_vrsqrtfp: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
> +	      i, vf_result[i], i, vf_expected_result[i]);
> +#else
> +    abort();
> +#endif
> +}
> +
> +void test_altivec_mask_for_load (const double *sh,
> +				 vector signed char vsc_expected_result)
> +{
> +  int i;
> +  vector signed char vsc_result;
> +
> +  vsc_result = __builtin_altivec_mask_for_load (sh);
> +
> +  for (i = 0; i < 16; i++)
> +    if (vsc_expected_result[i] != vsc_result[i])
> +#if DEBUG
> +      printf ("test_altivec_mask_for_load: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n",
> +	      i, vsc_result[i], i, vsc_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_altivec_vsel_1ti(vector signed __int128 vsq_arg1,
> +			   vector signed __int128 vsq_arg2,
> +			   vector unsigned __int128 vuq_arg3,
> +			   vector signed __int128 vsc_expected_result)
> +{
> +  vector signed __int128 vsc_result;
> +
> +  vsc_result = __builtin_altivec_vsel_1ti (vsq_arg1, vsq_arg2, vuq_arg3);
> +
> +  if (vsc_expected_result[0] != vsc_result[0])
> +    {  
> +#if DEBUG
> +       printf ("test_altivec_vsel_1ti: vsc_result = ");
> +       printf(" (0x%llx%llx)",
> +	      (unsigned long long)(vsc_result[0] >> 64),
> +	      (unsigned long long)(vsc_result[0] & 0xFFFFFFFFFFFFFFFF));
> +
> +       printf (",  vsc_expected_result = ");
> +       printf(" (0x%llx%llx)\n",
> +	      (unsigned long long)(vsc_expected_result[0] >> 64),
> +	      (unsigned long long)(vsc_expected_result[0]
> +				   & 0xFFFFFFFFFFFFFFFF));
> +#else
> +	abort();
> +#endif
> +      }
> +}
> +
> +void test_altivec_vsel_1ti_uns (vector unsigned __int128 vuq_arg1,
> +				vector unsigned __int128 vuq_arg2,
> +				vector unsigned __int128 vuq_arg3,
> +				vector unsigned __int128 vuc_expected_result)
> +{
> +  vector unsigned __int128 vuc_result;
> +
> +  vuc_result = __builtin_altivec_vsel_1ti_uns (vuq_arg1, vuq_arg2, vuq_arg3);
> +
> +  if (vuc_expected_result[0] != vuc_result[0])
> +    {
> +#if DEBUG
> +       printf ("test_altivec_vsel_1ti_uns: vuc_result = ");
> +       printf(" (0x%llx%llx)",
> +	      (unsigned long long)(vuc_result[0] >> 64),
> +	      (unsigned long long)(vuc_result[0] & 0xFFFFFFFFFFFFFFFF));
> +
> +       printf (",  vuc_expected_result = ");
> +       printf(" (0x%llx%llx)\n",
> +	      (unsigned long long)(vuc_expected_result[0] >> 64),
> +	      (unsigned long long)(vuc_expected_result[0]
> +				   & 0xFFFFFFFFFFFFFFFF));
> +#else
> +	abort();
> +#endif
> +      }
> +}
> +
> +void test_vec_init_v16qi (signed char sc_arg1, signed char sc_arg2,
> +			  signed char sc_arg3, signed char sc_arg4,
> +			  signed char sc_arg5, signed char sc_arg6,
> +			  signed char sc_arg7, signed char sc_arg8,
> +			  signed char sc_arg9, signed char sc_arg10,
> +			  signed char sc_arg11, signed char sc_arg12,
> +			  signed char sc_arg13, signed char sc_arg14,
> +			  signed char sc_arg15, signed char sc_arg16,
> +			  vector signed char vsc_expected_result)
> +{
> +  vector signed char vsc_result;
> +  int i;
> +
> +  vsc_result = __builtin_vec_init_v16qi (sc_arg1, sc_arg2, sc_arg3, sc_arg4,
> +					 sc_arg5, sc_arg6, sc_arg7, sc_arg8,
> +					 sc_arg9, sc_arg10, sc_arg11, sc_arg12,
> +					 sc_arg13, sc_arg14, sc_arg15,
> +					 sc_arg16);
> +
> +  for (i = 0; i < 16; i++)
> +    if (vsc_expected_result[i] != vsc_result[i])
> +#if DEBUG
> +      printf ("test_vec_init_v16qi: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n",
> +	      i, vsc_result[i], i, vsc_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_vec_init_v4sf (float sf_arg1, float sf_arg2,
> +			 float sf_arg3, float sf_arg4,
> +			 vector float vf_expected_result)
> +{
> +  vector float vf_result;
> +  int i;
> +
> +  vf_result = __builtin_vec_init_v4sf (sf_arg1, sf_arg2, sf_arg3, sf_arg4);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vf_expected_result[i] != vf_result[i])
> +#if DEBUG
> +      printf ("test_vec_init_v4sf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
> +	      i, vf_result[i], i, vf_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_vec_init_v4si (int si_arg1, int si_arg2,
> +			 int si_arg3, int si_arg4,
> +			 vector signed int vsi_expected_result)
> +{
> +  vector signed int vsi_result;
> +  int i;
> +
> +  vsi_result = __builtin_vec_init_v4si (si_arg1, si_arg2, si_arg3, si_arg4);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vsi_expected_result[i] != vsi_result[i])
> +#if DEBUG
> +      printf ("test_vec_init_v4si: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n",
> +	      i, vsi_result[i], i, vsi_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_vec_init_v8hi (short int ss_arg1, short int ss_arg2,
> +			 short int ss_arg3, short int ss_arg4,
> +			 short int ss_arg5, short int ss_arg6,
> +			 short int ss_arg7, short int ss_arg8,
> +			 vector signed short int vss_expected_result)
> +{
> +  vector signed short int vss_result;
> +  int i;
> +
> +  vss_result = __builtin_vec_init_v8hi (ss_arg1, ss_arg2, ss_arg3, ss_arg4,
> +					ss_arg5, ss_arg6, ss_arg7, ss_arg8);
> +
> +  for (i = 0; i < 8; i++)
> +    if (vss_expected_result[i] != vss_result[i])
> +#if DEBUG
> +      printf ("test_vec_init_v8hi: vss_result[%d] = %d, vss_expected_result[%d] = %d\n",
> +	      i, vss_result[i], i, vss_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_vec_set_v16qi (vector signed char vsc_arg1,
> +			 signed char sc_arg1,
> +			 vector signed char vsc_expected_result)
> +{
> +  vector signed char vsc_result;
> +  int i;
> +
> +  vsc_result = __builtin_vec_set_v16qi (vsc_arg1, sc_arg1, 3);
> +
> +  for (i = 0; i < 16; i++)
> +    if (vsc_expected_result[i] != vsc_result[i])
> +#if DEBUG
> +      printf ("test_vec_set_v16qi: vsc_result[%d] = 0x%x, vsc_expected_result[%d] = 0x%x\n",
> +	      i, vsc_result[i], i, vsc_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_vec_set_v4sf (vector float vsf_arg, float sf_arg1,
> +			vector float vf_expected_result)
> +{
> +  vector float vf_result;
> +  int i;
> +
> +  vf_result = __builtin_vec_set_v4sf (vsf_arg, sf_arg1, 0);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vf_expected_result[i] != vf_result[i])
> +#if DEBUG
> +      printf ("test_vec_init_v4sf: vf_result[%d] = %f, vf_expected_result[%d] = %f\n",
> +	      i, vf_result[i], i, vf_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_vec_set_v4si (vector int vsi_arg, int si_arg1,
> +				 vector signed int vsi_expected_result)
> +{
> +  vector signed int vsi_result;
> +  int i;
> +
> +  vsi_result = __builtin_vec_set_v4si (vsi_arg, si_arg1, 1);
> +
> +  for (i = 0; i < 4; i++)
> +    if (vsi_expected_result[i] != vsi_result[i])
> +#if DEBUG
> +      printf ("test_vec_init_v4si: vsi_result[%d] = %d, vsi_expected_result[%d] = %d\n",
> +	      i, vsi_result[i], i, vsi_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +void test_vec_set_v8hi (vector short int vss_arg, short int ss_arg,
> +				 vector signed short int vss_expected_result)
> +{
> +  vector signed short int vss_result;
> +  int i;
> +
> +  vss_result = __builtin_vec_set_v8hi (vss_arg, ss_arg, 2);
> +
> +  for (i = 0; i < 8; i++)
> +    if (vss_expected_result[i] != vss_result[i])
> +#if DEBUG
> +      printf ("test_vec_init_v8hi: vss_result[%d] = %d, vss_expected_result[%d] = %d\n",
> +	      i, vss_result[i], i, vss_expected_result[i]);
> +#else
> +      abort();
> +#endif
> +}
> +
> +int main ()
> +{
> +  signed int si_arg1, si_arg2, si_arg3, si_arg4;
> +  vector signed int vsi_arg, vsi_expected_result;
> +  vector unsigned int vui_arg, vui_expected_result;
> +  vector float vf_arg, vf_expected_result;
> +  vector signed char vsc_arg, vsc_expected_result;
> +  vector signed __int128 vsq_arg1, vsq_arg2, vsq_expected_result;
> +  vector unsigned __int128 vuq_arg1, vuq_arg2, vuq_arg3, vuq_expected_result;
> +
> +  signed char sc_arg1, sc_arg2, sc_arg3, sc_arg4, sc_arg5, sc_arg6, sc_arg7;
> +  signed char sc_arg8, sc_arg9, sc_arg10, sc_arg11, sc_arg12, sc_arg13;
> +  signed char sc_arg14, sc_arg15, sc_arg16;
> +
> +  signed short int ss_arg1, ss_arg2, ss_arg3, ss_arg4, ss_arg5, ss_arg6;
> +  signed short int ss_arg7, ss_arg8;
> +  vector signed short int vss_arg, vss_expected_result;
> +  
> +  float sf_arg1, sf_arg2, sf_arg3, sf_arg4;
> +  
> +  vf_arg = (vector float) {1.1, -2.2, 4.6, -6.9};
> +
> +  vsi_expected_result = (vector int) {1, -2, 4, -6};
> +  test_altivec_fix_sfsi (vf_arg, vsi_expected_result);
> +
> +  vui_expected_result = (vector unsigned int) {1, 0, 4, 0};
> +  test_altivec_fixuns_sfsi (vf_arg, vui_expected_result);
> +
> +  vsi_arg = (vector int) {-27, 33, 293, -123};
> +  vf_expected_result = (vector float) {-27.0, 33.0, 293.0, -123.0};
> +  test_altivec_float_sisf (vsi_arg, vf_expected_result);
> +
> +  vui_arg = (vector unsigned int) {27, 33, 293, 123};
> +  vf_expected_result = (vector float) {27.0, 33.0, 293.0, 123.0};
> +  test_altivec_uns_float_sisf (vui_arg, vf_expected_result);
> +
> +  vf_arg = (vector float) { 0.25, 0.01, 1.0, 64.0 };
> +  vf_expected_result = (vector float) {2.0, 10.0, 1.0, 0.125};
> +  test_altivec_vrsqrtfp (vf_arg, vf_expected_result);
> +
> +  vsc_expected_result = (vector signed char) {0x0F, 0x0E, 0x0D, 0x0C,
> +					      0x0B, 0x0A, 0x09, 0x08,
> +					      0x07, 0x06, 0x05, 0x04,
> +					      0x03, 0x02, 0x01, 0x00};
> +  /* NULL, Lower bits are zero so result will be case 0x0 of the lvsl inst. */
> +  test_altivec_mask_for_load (NULL, vsc_expected_result);
> +
> +  vsq_arg1 = (vector signed __int128) {0x0123456789ABCDEF};
> +  vsq_arg1 = (vsq_arg1 << 64) | (vector signed __int128) {0x0123456789ABCDEF};
> +  vsq_arg2 = (vector signed __int128) {0xFEDCBA9876543210};
> +  vsq_arg2 = (vsq_arg2 << 64) | (vector signed __int128) {0xFEDCBA9876543210};
> +  vuq_arg3 = (vector unsigned __int128) {0xFFFF00000000FFFF};
> +  vuq_arg3 = (vuq_arg3 << 64) |
> +    (vector unsigned __int128) {0x0000FFFFFFFF0000};
> +  vsq_expected_result = (vector signed __int128) {0xFEDC456789AB3210};
> +  vsq_expected_result = (vsq_expected_result << 64)
> +    | (vector signed __int128) {0x0123ba987654cdef};
> +
> +  test_altivec_vsel_1ti (vsq_arg1, vsq_arg2, vuq_arg3, vsq_expected_result);
> +
> +  vuq_arg1 = (vector unsigned __int128) {0x0123456789ABCDEF};
> +  vuq_arg1 = (vuq_arg1 << 64)
> +    | (vector unsigned __int128) {0x0123456789ABCDEF};
> +  vuq_arg2 = (vector unsigned __int128) {0xFEDCBA9876543210};
> +  vuq_arg2 = (vuq_arg2 << 64)
> +    | (vector unsigned __int128) {0xFEDCBA9876543210};
> +  vuq_arg3 = (vector unsigned __int128) {0xFFFF00000000FFFF};
> +  vuq_arg3 = (vuq_arg3 << 64)
> +    | (vector unsigned __int128) {0x0000FFFFFFFF0000};
> +  vuq_expected_result = (vector unsigned __int128) {0xFEDC456789AB3210};
> +  vuq_expected_result = (vuq_expected_result << 64)
> +    | (vector unsigned __int128) {0x0123ba987654cdef};
> +
> +  test_altivec_vsel_1ti_uns (vuq_arg1, vuq_arg2, vuq_arg3,
> +			     vuq_expected_result);
> +
> +  sc_arg1 = 1;
> +  sc_arg2 = 2;
> +  sc_arg3 = 3;
> +  sc_arg4 = 4;
> +  sc_arg5 = 5;
> +  sc_arg6 = 6;
> +  sc_arg7 = 7;
> +  sc_arg8 = 8;
> +  sc_arg9 = 9;
> +  sc_arg10 = 10;
> +  sc_arg11 = 11;
> +  sc_arg12 = 12;
> +  sc_arg13 = 13;
> +  sc_arg14 = 14;
> +  sc_arg15 = 15;
> +  sc_arg16 = 16;
> +  vsc_expected_result = (vector signed char) {0x1, 0x2, 0x3, 0x4, 0x5, 0x6,
> +					      0x7, 0x8, 0x9, 0xA, 0xB, 0xC,
> +					      0xD, 0xE, 0xf, 0x10};
> +
> +  test_vec_init_v16qi (sc_arg1, sc_arg2, sc_arg3, sc_arg4, sc_arg5,
> +		       sc_arg6, sc_arg7, sc_arg8, sc_arg9, sc_arg10,
> +		       sc_arg11, sc_arg12, sc_arg13, sc_arg14,
> +		       sc_arg15, sc_arg16, vsc_expected_result);
> +
> +  sf_arg1 = 1.0;
> +  sf_arg2 = 2.0;
> +  sf_arg3 = 3.0;
> +  sf_arg4 = 4.0;
> +  vf_expected_result = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  test_vec_init_v4sf (sf_arg1, sf_arg2, sf_arg3, sf_arg4,
> +		      vf_expected_result);
> +
> +  si_arg1 = 1;
> +  si_arg2 = 2;
> +  si_arg3 = 3;
> +  si_arg4 = 4;
> +  vsi_expected_result = (vector signed int) {1, 2, 3, 4};
> +  test_vec_init_v4si (si_arg1, si_arg2, si_arg3, si_arg4,
> +		      vsi_expected_result);
> +
> +  ss_arg1 = 1;
> +  ss_arg2 = 2;
> +  ss_arg3 = 3;
> +  ss_arg4 = 4;
> +  ss_arg5 = 5;
> +  ss_arg6 = 6;
> +  ss_arg7 = 7;
> +  ss_arg8 = 8;
> +  vss_expected_result = (vector signed short int) {1, 2, 3, 4, 5, 6, 7, 8};
> +  test_vec_init_v8hi (ss_arg1, ss_arg2, ss_arg3, ss_arg4,
> +		      ss_arg5, ss_arg6, ss_arg7, ss_arg8,
> +		      vss_expected_result);
> +
> +  vsc_arg = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> +				  14, 15, 16};
> +  sc_arg1 = 40;
> +  vsc_expected_result = (vector signed char) {1, 2, 3, 40, 5, 6, 7, 8, 9,
> +					      10, 11, 12, 13, 14, 15, 16};
> +  test_vec_set_v16qi (vsc_arg, sc_arg1, vsc_expected_result);
> +
> +  vf_arg = (vector float) {1.0, 2.0, 3.0, 4.0};
> +  sf_arg1 = 10.0;
> +  vf_expected_result = (vector float) {10.0, 2.0, 3.0, 4.0};
> +  test_vec_set_v4sf (vf_arg, sf_arg1, vf_expected_result);
> +
> +  vsi_arg = (vector signed int) {1, 2, 3, 4};
> +  si_arg1 = 20;
> +  vsi_expected_result = (vector signed int) {1, 20, 3, 4}; 
> +  test_vec_set_v4si (vsi_arg, si_arg1, vsi_expected_result);
> +
> +  vss_arg = (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8};
> +  ss_arg1 = 30;
> +  vss_expected_result = (vector signed short) {1, 2, 30, 4, 5, 6, 7, 8}; 
> +  test_vec_set_v8hi (vss_arg, ss_arg1, vss_expected_result);
> +}
> +
> +/* { dg-final { scan-assembler-times "xvcvspsxws" 1 } } */
> +/* { dg-final { scan-assembler-times "xvcvspuxws" 1 } } */
> +/* { dg-final { scan-assembler-times "xvcvsxwsp" 1 } } */
> +/* { dg-final { scan-assembler-times "xvcvuxwsp" 1 } } */
> +/* { dg-final { scan-assembler-times "xvrsqrtesp" 1 } } */
> +/* { dg-final { scan-assembler-times "lvsl" 1 } } */
> +/* { dg-final { scan-assembler-times "xxsel" 4 } } */