Re: [PATCH] RISC-V: branch-(not)equals-zero compares against $zero

[Jeff Law <jeffreyalaw@gmail.com>]

On 11/8/22 12:55, Philipp Tomsich wrote:
> If we are testing a register or a paradoxical subreg (i.e. anything that is not
> a partial subreg) for equality/non-equality with zero, we can generate a branch
> that compares against $zero.  This will work for QI, HI, SI and DImode, so we
> enable this for ANYI.
>
> 2020-08-30  gcc/ChangeLog:
>
> 	* config/riscv/riscv.md (*branch<mode>_equals_zero): Added pattern.

I've gone back an forth on this a few times.  As you know, I hate 
subregs in the target descriptions and I guess I need to extend that to 
querying if something is a subreg or not rather than just subregs 
appearing in the RTL.


Presumably the idea behind rejecting partial subregs is the bits outside 
the partial is unspecified, but that's also going to be true if we're 
looking at a hardreg in QImode (for example) irrespective of it being 
wrapped in a subreg.


I don't doubt it works the vast majority of the time, but I haven't been 
able to convince myself it'll work all the time.  How do we ensure that 
the bits outside the mode are zero?  I've been bitten by this kind of 
problem before, and it's safe to say it was exceedingly painful to find.


Jeff