From: 钟居哲 <juzhe.zhong@rivai.ai>
To: 钟居哲 <juzhe.zhong@rivai.ai>, gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>, palmer <palmer@dabbelt.com>,
"Jeff Law" <jeffreyalaw@gmail.com>
Subject: Re: [PATCH 0/3] RISC-V: Basic enable RVV auto-vectorizaiton
Date: Thu, 20 Apr 2023 00:45:33 +0800 [thread overview]
Message-ID: <4378ED7294F8EA73+2023042000453280642230@rivai.ai> (raw)
In-Reply-To: <20230419163634.1030144-1-juzhe.zhong@rivai.ai>
[-- Attachment #1: Type: text/plain, Size: 5733 bytes --]
Sorry for sending messy patches.
Ignore those messy patches and these following patches are the real patches:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616222.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616225.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616223.html
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616224.html
Thanks.
juzhe.zhong@rivai.ai
From: juzhe.zhong
Date: 2023-04-20 00:36
To: gcc-patches
CC: kito.cheng; palmer; jeffreyalaw; Ju-Zhe Zhong
Subject: [PATCH 0/3] RISC-V: Basic enable RVV auto-vectorizaiton
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
PATCH 1: Add compile option for RVV auto-vectorization.
PATCH 2: Enable basic RVV auto-vectorization.
PATCH 3: Add sanity testcases.
*** BLURB HERE ***
Ju-Zhe Zhong (3):
RISC-V: Add auto-vectorization compile option for RVV
RISC-V: Enable basic auto-vectorization for RVV
RISC-V: Add sanity testcases for RVV auto-vectorization
gcc/config/riscv/autovec.md | 49 ++++++++
gcc/config/riscv/riscv-opts.h | 15 +++
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 53 +++++++++
gcc/config/riscv/riscv.cc | 24 +++-
gcc/config/riscv/riscv.opt | 37 ++++++
gcc/config/riscv/vector.md | 4 +-
.../rvv/autovec/partial/single_rgroup-1.c | 8 ++
.../rvv/autovec/partial/single_rgroup-1.h | 106 ++++++++++++++++++
.../rvv/autovec/partial/single_rgroup_run-1.c | 19 ++++
.../gcc.target/riscv/rvv/autovec/template-1.h | 68 +++++++++++
.../gcc.target/riscv/rvv/autovec/v-1.c | 4 +
.../gcc.target/riscv/rvv/autovec/v-2.c | 6 +
.../gcc.target/riscv/rvv/autovec/zve32f-1.c | 4 +
.../gcc.target/riscv/rvv/autovec/zve32f-2.c | 5 +
.../gcc.target/riscv/rvv/autovec/zve32f-3.c | 6 +
.../riscv/rvv/autovec/zve32f_zvl128b-1.c | 4 +
.../riscv/rvv/autovec/zve32f_zvl128b-2.c | 6 +
.../gcc.target/riscv/rvv/autovec/zve32x-1.c | 4 +
.../gcc.target/riscv/rvv/autovec/zve32x-2.c | 6 +
.../gcc.target/riscv/rvv/autovec/zve32x-3.c | 6 +
.../riscv/rvv/autovec/zve32x_zvl128b-1.c | 5 +
.../riscv/rvv/autovec/zve32x_zvl128b-2.c | 6 +
.../gcc.target/riscv/rvv/autovec/zve64d-1.c | 4 +
.../gcc.target/riscv/rvv/autovec/zve64d-2.c | 4 +
.../gcc.target/riscv/rvv/autovec/zve64d-3.c | 6 +
.../riscv/rvv/autovec/zve64d_zvl128b-1.c | 4 +
.../riscv/rvv/autovec/zve64d_zvl128b-2.c | 6 +
.../gcc.target/riscv/rvv/autovec/zve64f-1.c | 4 +
.../gcc.target/riscv/rvv/autovec/zve64f-2.c | 4 +
.../gcc.target/riscv/rvv/autovec/zve64f-3.c | 6 +
.../riscv/rvv/autovec/zve64f_zvl128b-1.c | 4 +
.../riscv/rvv/autovec/zve64f_zvl128b-2.c | 6 +
.../gcc.target/riscv/rvv/autovec/zve64x-1.c | 4 +
.../gcc.target/riscv/rvv/autovec/zve64x-2.c | 4 +
.../gcc.target/riscv/rvv/autovec/zve64x-3.c | 6 +
.../riscv/rvv/autovec/zve64x_zvl128b-1.c | 4 +
.../riscv/rvv/autovec/zve64x_zvl128b-2.c | 6 +
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 16 +++
39 files changed, 532 insertions(+), 2 deletions(-)
create mode 100644 gcc/config/riscv/autovec.md
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/template-1.h
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32f_zvl128b-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve32x_zvl128b-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c
--
2.36.3
next prev parent reply other threads:[~2023-04-19 16:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 16:36 juzhe.zhong
2023-04-19 16:36 ` [PATCH 1/3] RISC-V: Add auto-vectorization compile option for RVV juzhe.zhong
2023-04-20 11:08 ` Richard Biener
2023-04-26 3:00 ` Jeff Law
2023-04-19 16:36 ` [PATCH 2/3] RISC-V: Enable basic auto-vectorization " juzhe.zhong
2023-04-19 16:36 ` [PATCH 3/3] RISC-V: Add sanity testcases for RVV auto-vectorization juzhe.zhong
2023-04-19 16:45 ` 钟居哲 [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-04-19 16:36 [PATCH 0/3] RISC-V: Basic enable RVV auto-vectorizaiton juzhe.zhong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=4378ED7294F8EA73+2023042000453280642230@rivai.ai \
--to=juzhe.zhong@rivai.ai \
--cc=gcc-patches@gcc.gnu.org \
--cc=jeffreyalaw@gmail.com \
--cc=kito.cheng@gmail.com \
--cc=palmer@dabbelt.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).