From: Jeff Law <jeffreyalaw@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org
Cc: Kito Cheng <kito.cheng@gmail.com>,
Jeff Law <jlaw@ventanamicro.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Palmer Dabbelt <palmer@rivosinc.com>,
Vineet Gupta <vineetg@rivosinc.com>
Subject: Re: [PATCH v2] RISC-V: No extensions for SImode min/max against safe constant
Date: Fri, 18 Nov 2022 13:11:23 -0700 [thread overview]
Message-ID: <44c463f0-5ef7-abc7-bc9b-e2c195394086@gmail.com> (raw)
In-Reply-To: <20221109000631.2814859-1-philipp.tomsich@vrull.eu>
On 11/8/22 17:06, Philipp Tomsich wrote:
> Optimize the common case of a SImode min/max against a constant
> that is safe both for sign- and zero-extension.
> E.g., consider the case
> int f(unsigned int* a)
> {
> const int C = 1000;
> return *a * 3 > C ? C : *a * 3;
> }
> where the constant C will yield the same result in DImode whether
> sign- or zero-extended.
>
> This should eventually go away once the lowering to RTL smartens up
> and considers the precision/signedness and the value-ranges of the
> operands to MIN_EXPR nad MAX_EXPR.
>
> gcc/ChangeLog:
>
> * config/riscv/bitmanip.md (*minmax): Additional pattern for
> min/max against constants that are extension-invariant.
> * config/riscv/iterators.md (minmax_optab): Add an iterator
> that has only min and max rtl.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zbb-min-max-02.c: New test.
Ok
jeff
next prev parent reply other threads:[~2022-11-18 20:11 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-09 0:06 Philipp Tomsich
2022-11-18 20:11 ` Jeff Law [this message]
2022-11-18 20:24 ` Philipp Tomsich
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