From: Jeff Law <jeffreyalaw@gmail.com>
To: "Maciej W. Rozycki" <macro@embecosm.com>
Cc: Kito Cheng <kito.cheng@gmail.com>,
GCC Patches <gcc-patches@gcc.gnu.org>,
Andrew Waterman <andrew@sifive.com>
Subject: Re: [PATCH v2] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU
Date: Mon, 28 Nov 2022 11:07:26 -0700 [thread overview]
Message-ID: <486923d1-de21-4069-3aee-d9367fc4e5f9@gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.20.2211281635580.463@tpp.orcam.me.uk>
On 11/28/22 10:44, Maciej W. Rozycki wrote:
>
>> Your patch is probably still useful. I think Kito's only concern was to make
>> sure we don't have the ANDI instruction in addition to not having the SEXT
>> instruction. So still approved for trunk, just update the testcases to make
>> sure we don't have the ANDI too.
>
> Given the false negatives how about getting a bit stricter and also
> checking there's nothing following the XORI instruction, like here?
>
> It might be an overkill to have a check both for the sequence and for the
> absence of ANDI or SEXT.W as well, but I'd rather have them both out of an
> abundance of caution.
Sure. That works for me as well. OK for the trunk.
Interestingly enough Raphael and I are looking at a case where Roger's
patch is causing poorer code generation. Given what we're finding as we
work through the other case, I won't be surprised if we find multiple
cases where RISC-V is generating poorer code after that patch, even
though it's a perfectly sensible patch.
jeff
next prev parent reply other threads:[~2022-11-28 18:07 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-03 9:54 [PATCH] " Maciej W. Rozycki
2022-08-11 3:26 ` Kito Cheng
2022-08-12 22:01 ` Maciej W. Rozycki
2022-11-25 14:07 ` [PING][PATCH] " Maciej W. Rozycki
2022-11-28 14:50 ` Jeff Law
2022-11-28 15:38 ` Maciej W. Rozycki
2022-11-28 16:15 ` Jeff Law
2022-11-28 17:44 ` [PATCH v2] " Maciej W. Rozycki
2022-11-28 18:07 ` Jeff Law [this message]
2022-11-28 19:41 ` Maciej W. Rozycki
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