Re: [PATCH v2] RISC-V: Avoid redundant sign-extension for SImode SGE, SGEU, SLE, SLEU

["Maciej W. Rozycki" <macro@embecosm.com>]

On Mon, 28 Nov 2022, Jeff Law wrote:

> >   Given the false negatives how about getting a bit stricter and also
> > checking there's nothing following the XORI instruction, like here?
> > 
> >   It might be an overkill to have a check both for the sequence and for the
> > absence of ANDI or SEXT.W as well, but I'd rather have them both out of an
> > abundance of caution.
> Sure.  That works for me as well.  OK for the trunk.

 I have committed it then.  Thank you for your review.

> Interestingly enough Raphael and I are looking at a case where Roger's patch
> is causing poorer code generation.  Given what we're finding as we work
> through the other case, I won't be surprised if we find multiple cases where
> RISC-V is generating poorer code after that patch, even though it's a
> perfectly sensible patch.

 I think it would make sense to run RISC-V performance evaluation w/ and 
w/o Roger's applied.  Sadly I am somewhat resource-constrained right now 
and won't be able to do that anytime soon, but hopefully there's enough 
RISC-V hardware available now for someone to pick it up.

  Maciej