Re: [PATCH v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602]

[Jeff Law <jeffreyalaw@gmail.com>]

[-- Attachment #1: Type: text/plain, Size: 1718 bytes --]



On 12/9/22 11:25, Raphael Moreira Zinsly wrote:
> Changes since v1:
> 	- Fixed formatting issues.
> 	- Added a name to the define_insn_and_split pattern.
> 	- Set the target on the 'dg-do compile' in pr106602.c.
> 	- Removed the rv32 restriction in pr95632.c.
> 
> -- >8 --
> 
> Due to RISC-V limitations on operations with big constants combine
> is failing to match such operations and is not being able to
> produce optimal code as it keeps splitting them.  By pretending we
> can do those operations we can get more opportunities for
> simplification of surrounding instructions.
> 
> 2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
> 	    Jeff Law  <jlaw@ventanamicro.com>
> 
> gcc/Changelog:
> 	PR target/95632
> 	PR target/106602
> 	* config/riscv/riscv.md: New pattern to simulate complex
> 	const_int loads.
> 
> gcc/testsuite/ChangeLog:
> 	* gcc.target/riscv/pr95632.c: New test.
> 	* gcc.target/riscv/pr106602.c: New test.
Here's the final version of the patch that addresses these two BZs.

This version tightens slightly the condition for the new pattern so that 
it doesn't match two special cases.

In particular, we avoid certain constants which are used in 
define_splits where the constant load feeds a logical AND which can 
ultimately be implemented via a pair of shifts.

Those cases are 3->2 splits on the trunk.  If we allowed those constants 
in the new pattern, then we'd need to support 2->2 splits in combine.c 
which is a non-starter.

Bootstrapped and regression tested on riscv64-linux-gnu.  I also 
compared resultant assembly code with/without this change for all the 
source files in the compiler natively to look for further regressions.

Committed to the trunk,
Jeff

[-- Attachment #2: P --]
[-- Type: text/plain, Size: 2626 bytes --]

commit 2e886eef7f2b5aadb00171af868f0895b647c3a4
Author: Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
Date:   Tue Dec 27 18:29:25 2022 -0500

    RISC-V: Produce better code with complex constants [PR95632] [PR106602]
    
    gcc/Changelog:
            PR target/95632
            PR target/106602
            * config/riscv/riscv.md: New pattern to simulate complex
            const_int loads.
    
    gcc/testsuite/ChangeLog:
            * gcc.target/riscv/pr95632.c: New test.
            * gcc.target/riscv/pr106602.c: New test.

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a8bb331f25c..020833b9206 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1670,6 +1670,23 @@ (define_split
 		      MAX_MACHINE_MODE, &operands[3], TRUE);
 })
 
+;; Pretend to have the ability to load complex const_int in order to get
+;; better code generation around them.
+;;
+;; But avoid constants that are special cased elsewhere.
+(define_insn_and_split "*mvconst_internal"
+  [(set (match_operand:GPR 0 "register_operand" "=r")
+        (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
+  "!(p2m1_shift_operand (operands[1]) || high_mask_shift_operand (operands[1]))"
+  "#"
+  "&& 1"
+  [(const_int 0)]
+{
+  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
+                      <MODE>mode, TRUE);
+  DONE;
+})
+
 ;; 64-bit integer moves
 
 (define_expand "movdi"
diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602.c
new file mode 100644
index 00000000000..825b1a143b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr106602.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { riscv64*-*-* } } } */
+/* { dg-options "-O2" } */
+
+unsigned long
+foo2 (unsigned long a)
+{
+  return (unsigned long)(unsigned int) a << 6;
+}
+
+/* { dg-final { scan-assembler-times "slli\t" 1 } } */
+/* { dg-final { scan-assembler-times "srli\t" 1 } } */
+/* { dg-final { scan-assembler-not "\tli\t" } } */
+/* { dg-final { scan-assembler-not "addi\t" } } */
+/* { dg-final { scan-assembler-not "and\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/pr95632.c b/gcc/testsuite/gcc.target/riscv/pr95632.c
new file mode 100644
index 00000000000..b865c2f2e97
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr95632.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+unsigned short
+foo (unsigned short crc)
+{
+  crc ^= 0x4002;
+  crc >>= 1;
+  crc |= 0x8000;
+
+  return crc;
+}
+
+/* { dg-final { scan-assembler-times "srli\t" 1 } } */
+/* { dg-final { scan-assembler-not "slli\t" } } */