Re: [PATCH v2] RISC-V: Produce better code with complex constants [PR95632] [PR106602]

[Andrew Pinski <pinskia@gmail.com>]

On Fri, Dec 9, 2022 at 10:25 AM Raphael Moreira Zinsly
<rzinsly@ventanamicro.com> wrote:
>
> Changes since v1:
>         - Fixed formatting issues.
>         - Added a name to the define_insn_and_split pattern.
>         - Set the target on the 'dg-do compile' in pr106602.c.
>         - Removed the rv32 restriction in pr95632.c.
>
> -- >8 --
>
> Due to RISC-V limitations on operations with big constants combine
> is failing to match such operations and is not being able to
> produce optimal code as it keeps splitting them.  By pretending we
> can do those operations we can get more opportunities for
> simplification of surrounding instructions.
>
> 2022-12-06  Raphael Moreira Zinsly  <rzinsly@ventanamicro.com>
>             Jeff Law  <jlaw@ventanamicro.com>
>
> gcc/Changelog:
>         PR target/95632
>         PR target/106602
>         * config/riscv/riscv.md: New pattern to simulate complex
>         const_int loads.
>
> gcc/testsuite/ChangeLog:
>         * gcc.target/riscv/pr95632.c: New test.
>         * gcc.target/riscv/pr106602.c: New test.
> ---
>  gcc/config/riscv/riscv.md                 | 15 +++++++++++++++
>  gcc/testsuite/gcc.target/riscv/pr106602.c | 14 ++++++++++++++
>  gcc/testsuite/gcc.target/riscv/pr95632.c  | 15 +++++++++++++++
>  3 files changed, 44 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr106602.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr95632.c
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index df57e2b0b4a..b0daa4b19eb 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -1667,6 +1667,21 @@
>                       MAX_MACHINE_MODE, &operands[3], TRUE);
>  })
>
> +;; Pretend to have the ability to load complex const_int in order to get
> +;; better code generation around them.
> +(define_insn_and_split "*mvconst_internal"
> +  [(set (match_operand:GPR 0 "register_operand" "=r")
> +    (match_operand:GPR 1 "splittable_const_int_operand" "i"))]
> +  "cse_not_expected"

This is just way broken. This should be combined with the normal move
instructions and just be a define_split.
See PR 108892 for a testcase which shows this breaking how the
register allocator thinks it should work.

Thanks,
Andrew

> +  "#"
> +  "&& 1"
> +  [(const_int 0)]
> +{
> +  riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),
> +                     <MODE>mode, TRUE);
> +  DONE;
> +})
> +
>  ;; 64-bit integer moves
>
>  (define_expand "movdi"
> diff --git a/gcc/testsuite/gcc.target/riscv/pr106602.c b/gcc/testsuite/gcc.target/riscv/pr106602.c
> new file mode 100644
> index 00000000000..825b1a143b5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr106602.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile { target { riscv64*-*-* } } } */
> +/* { dg-options "-O2" } */
> +
> +unsigned long
> +foo2 (unsigned long a)
> +{
> +  return (unsigned long)(unsigned int) a << 6;
> +}
> +
> +/* { dg-final { scan-assembler-times "slli\t" 1 } } */
> +/* { dg-final { scan-assembler-times "srli\t" 1 } } */
> +/* { dg-final { scan-assembler-not "\tli\t" } } */
> +/* { dg-final { scan-assembler-not "addi\t" } } */
> +/* { dg-final { scan-assembler-not "and\t" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr95632.c b/gcc/testsuite/gcc.target/riscv/pr95632.c
> new file mode 100644
> index 00000000000..b865c2f2e97
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr95632.c
> @@ -0,0 +1,15 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +unsigned short
> +foo (unsigned short crc)
> +{
> +  crc ^= 0x4002;
> +  crc >>= 1;
> +  crc |= 0x8000;
> +
> +  return crc;
> +}
> +
> +/* { dg-final { scan-assembler-times "srli\t" 1 } } */
> +/* { dg-final { scan-assembler-not "slli\t" } } */
> --
> 2.38.1
>