From: Jeff Law <jeffreyalaw@gmail.com>
To: Philipp Tomsich <philipp.tomsich@vrull.eu>, gcc-patches@gcc.gnu.org
Cc: Palmer Dabbelt <palmer@rivosinc.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Vineet Gupta <vineetg@rivosinc.com>,
Jeff Law <jlaw@ventanamicro.com>,
Kito Cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH] RISC-V: Optimize branches testing a bit-range or a shifted immediate
Date: Fri, 18 Nov 2022 12:30:34 -0700 [thread overview]
Message-ID: <5799b07e-c4ae-4511-0b23-a24330802455@gmail.com> (raw)
In-Reply-To: <20221108204625.2794920-1-philipp.tomsich@vrull.eu>
On 11/8/22 13:46, Philipp Tomsich wrote:
> gcc/ChangeLog:
>
> * config/riscv/predicates.md (shifted_const_arith_operand):
> (uimm_extra_bit_operand):
> * config/riscv/riscv.md (*branch<ANYI:mode>_shiftedarith_equals_zero):
> (*branch<ANYI:mode>_shiftedmask_equals_zero):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/branch-1.c: New test.
Nice... It seems so obvious, but I'm not offhand aware of other ports
doing this, though many could likely benefit.
OK
jeff
next prev parent reply other threads:[~2022-11-18 19:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 20:46 Philipp Tomsich
2022-11-18 19:30 ` Jeff Law [this message]
2022-11-18 19:55 ` Philipp Tomsich
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