* [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
@ 2023-05-31 11:32 juzhe.zhong
2023-05-31 11:55 ` Robin Dapp
0 siblings, 1 reply; 6+ messages in thread
From: juzhe.zhong @ 2023-05-31 11:32 UTC (permalink / raw)
To: gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw, rdapp.gcc,
Juzhe-Zhong
From: Juzhe-Zhong <juzhe.zhong@rivai.ai>
The approach is quite simple and obvious, changing extension pattern into define_insn_and_split
will make combine PASS combine into widen operations naturally.
gcc/ChangeLog:
* config/riscv/autovec.md (<optab><v_double_trunc><mode>2): Change expand into define_insn_and_split.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/rvv.exp:
* gcc.target/riscv/rvv/autovec/widen/widen-1.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen-2.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen-3.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen-4.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: New test.
* gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: New test.
---
gcc/config/riscv/autovec.md | 13 ++++---
.../riscv/rvv/autovec/widen/widen-1.c | 27 +++++++++++++++
.../riscv/rvv/autovec/widen/widen-2.c | 27 +++++++++++++++
.../riscv/rvv/autovec/widen/widen-3.c | 27 +++++++++++++++
.../riscv/rvv/autovec/widen/widen-4.c | 23 +++++++++++++
.../riscv/rvv/autovec/widen/widen_run-1.c | 34 +++++++++++++++++++
.../riscv/rvv/autovec/widen/widen_run-2.c | 34 +++++++++++++++++++
.../riscv/rvv/autovec/widen/widen_run-3.c | 34 +++++++++++++++++++
.../riscv/rvv/autovec/widen/widen_run-4.c | 31 +++++++++++++++++
gcc/testsuite/gcc.target/riscv/rvv/rvv.exp | 13 +++++++
10 files changed, 259 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4834bb4b412..e96de60123b 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -401,16 +401,21 @@
;; - vsext.vf[2|4|8]
;; -------------------------------------------------------------------------
-(define_expand "<optab><v_double_trunc><mode>2"
- [(set (match_operand:VWEXTI 0 "register_operand")
+(define_insn_and_split "<optab><v_double_trunc><mode>2"
+ [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
(any_extend:VWEXTI
- (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand")))]
+ (match_operand:<V_DOUBLE_TRUNC> 1 "register_operand" "vr")))]
"TARGET_VECTOR"
+ "#"
+ "&& can_create_pseudo_p ()"
+ [(const_int 0)]
{
insn_code icode = code_for_pred_vf2 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::RVV_UNOP, operands);
DONE;
-})
+}
+ [(set_attr "type" "vext")
+ (set_attr "mode" "<MODE>")])
(define_expand "<optab><v_quad_trunc><mode>2"
[(set (match_operand:VQEXTI 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c
new file mode 100644
index 00000000000..00edecab089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwadd_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \
+ TYPE2 *__restrict a, \
+ TYPE2 *__restrict b, \
+ int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = (TYPE1) a[i] + (TYPE1) b[i]; \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (int16_t, int8_t) \
+ TEST_TYPE (uint16_t, uint8_t) \
+ TEST_TYPE (int32_t, int16_t) \
+ TEST_TYPE (uint32_t, uint16_t) \
+ TEST_TYPE (int64_t, int32_t) \
+ TEST_TYPE (uint64_t, uint32_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwadd\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvwaddu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c
new file mode 100644
index 00000000000..4d370f583b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwsub_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \
+ TYPE2 *__restrict a, \
+ TYPE2 *__restrict b, \
+ int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = (TYPE1) a[i] - (TYPE1) b[i]; \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (int16_t, int8_t) \
+ TEST_TYPE (uint16_t, uint8_t) \
+ TEST_TYPE (int32_t, int16_t) \
+ TEST_TYPE (uint32_t, uint16_t) \
+ TEST_TYPE (int64_t, int32_t) \
+ TEST_TYPE (uint64_t, uint32_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwsub\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvwsubu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c
new file mode 100644
index 00000000000..609a5c09f70
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-3.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2) \
+ __attribute__ ((noipa)) void vwmul_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \
+ TYPE2 *__restrict a, \
+ TYPE2 *__restrict b, \
+ int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = (TYPE1) a[i] * (TYPE1) b[i]; \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (int16_t, int8_t) \
+ TEST_TYPE (uint16_t, uint8_t) \
+ TEST_TYPE (int32_t, int16_t) \
+ TEST_TYPE (uint32_t, uint16_t) \
+ TEST_TYPE (int64_t, int32_t) \
+ TEST_TYPE (uint64_t, uint32_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwmul\.vv} 3 } } */
+/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c
new file mode 100644
index 00000000000..c29a74c4f8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen-4.c
@@ -0,0 +1,23 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable" } */
+
+#include <stdint-gcc.h>
+
+#define TEST_TYPE(TYPE1, TYPE2, TYPE3) \
+ __attribute__ ((noipa)) void vwmul_##TYPE1_##TYPE2 (TYPE1 *__restrict dst, \
+ TYPE2 *__restrict a, \
+ TYPE3 *__restrict b, \
+ int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = (TYPE1) a[i] * (TYPE1) b[i]; \
+ }
+
+#define TEST_ALL() \
+ TEST_TYPE (int16_t, int8_t, uint8_t) \
+ TEST_TYPE (int32_t, int16_t, uint16_t) \
+ TEST_TYPE (int64_t, int32_t, uint32_t)
+
+TEST_ALL ()
+
+/* { dg-final { scan-assembler-times {\tvwmulsu\.vv} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
new file mode 100644
index 00000000000..6cdeb571711
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-1.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include <assert.h>
+#include "widen-1.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ } \
+ vwadd_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] == ((TYPE1) a##TYPE2[i] + (TYPE1) b##TYPE2[i]));
+
+#define RUN_ALL() \
+ RUN (int16_t, int8_t, -128) \
+ RUN (uint16_t, uint8_t, 255) \
+ RUN (int32_t, int16_t, -32768) \
+ RUN (uint32_t, uint16_t, 65535) \
+ RUN (int64_t, int32_t, -2147483648) \
+ RUN (uint64_t, uint32_t, 4294967295)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
new file mode 100644
index 00000000000..84baa515610
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-2.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include <assert.h>
+#include "widen-2.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ } \
+ vwsub_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] == ((TYPE1) a##TYPE2[i] - (TYPE1) b##TYPE2[i]));
+
+#define RUN_ALL() \
+ RUN (int16_t, int8_t, -128) \
+ RUN (uint16_t, uint8_t, 255) \
+ RUN (int32_t, int16_t, -32768) \
+ RUN (uint32_t, uint16_t, 65535) \
+ RUN (int64_t, int32_t, -2147483648) \
+ RUN (uint64_t, uint32_t, 4294967295)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
new file mode 100644
index 00000000000..beb0cc2b58b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-3.c
@@ -0,0 +1,34 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include <assert.h>
+#include "widen-3.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE2 b##TYPE2[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE2[i] = LIMIT + i & 1964; \
+ } \
+ vwmul_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE2, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] == ((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE2[i]));
+
+#define RUN_ALL() \
+ RUN (int16_t, int8_t, -128) \
+ RUN (uint16_t, uint8_t, 255) \
+ RUN (int32_t, int16_t, -32768) \
+ RUN (uint32_t, uint16_t, 65535) \
+ RUN (int64_t, int32_t, -2147483648) \
+ RUN (uint64_t, uint32_t, 4294967295)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
new file mode 100644
index 00000000000..a14539f72ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/widen_run-4.c
@@ -0,0 +1,31 @@
+/* { dg-do run { target { riscv_vector } } } */
+/* { dg-additional-options "--param=riscv-autovec-preference=scalable" } */
+
+#include <assert.h>
+#include "widen-4.c"
+
+#define SZ 512
+
+#define RUN(TYPE1, TYPE2, TYPE3, LIMIT) \
+ TYPE2 a##TYPE2[SZ]; \
+ TYPE3 b##TYPE3[SZ]; \
+ TYPE1 dst##TYPE1[SZ]; \
+ for (int i = 0; i < SZ; i++) \
+ { \
+ a##TYPE2[i] = LIMIT + i % 8723; \
+ b##TYPE3[i] = LIMIT + i & 1964; \
+ } \
+ vwmul_##TYPE1_##TYPE2 (dst##TYPE1, a##TYPE2, b##TYPE3, SZ); \
+ for (int i = 0; i < SZ; i++) \
+ assert (dst##TYPE1[i] == ((TYPE1) a##TYPE2[i] * (TYPE1) b##TYPE3[i]));
+
+#define RUN_ALL() \
+ RUN (int16_t, int8_t, uint8_t, -128) \
+ RUN (int32_t, int16_t, uint16_t, -32768) \
+ RUN (int64_t, int32_t, uint32_t, -2147483648)
+
+int
+main ()
+{
+ RUN_ALL ()
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
index bf03570b9cc..5e69235a268 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp
@@ -73,6 +73,19 @@ foreach op $AUTOVEC_TEST_OPTS {
"" "$op"
}
+# widening operation only test on LMUL < 8
+set AUTOVEC_TEST_OPTS [list \
+ {-ftree-vectorize -O3 --param riscv-autovec-lmul=m1} \
+ {-ftree-vectorize -O3 --param riscv-autovec-lmul=m2} \
+ {-ftree-vectorize -O3 --param riscv-autovec-lmul=m4} \
+ {-ftree-vectorize -O2 --param riscv-autovec-lmul=m1} \
+ {-ftree-vectorize -O2 --param riscv-autovec-lmul=m2} \
+ {-ftree-vectorize -O2 --param riscv-autovec-lmul=m4} ]
+foreach op $AUTOVEC_TEST_OPTS {
+ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/widen/*.\[cS\]]] \
+ "" "$op"
+}
+
# VLS-VLMAX tests
dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vls-vlmax/*.\[cS\]]] \
"-std=c99 -O3 -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax" $CFLAGS
--
2.36.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
2023-05-31 11:32 [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization juzhe.zhong
@ 2023-05-31 11:55 ` Robin Dapp
2023-05-31 12:58 ` Jeff Law
0 siblings, 1 reply; 6+ messages in thread
From: Robin Dapp @ 2023-05-31 11:55 UTC (permalink / raw)
To: juzhe.zhong, gcc-patches
Cc: rdapp.gcc, kito.cheng, kito.cheng, palmer, palmer, jeffreyalaw
Hi Juzhe,
> The approach is quite simple and obvious, changing extension pattern
> into define_insn_and_split will make combine PASS combine into widen
> operations naturally.
looks good to me. Tiny nit: I would add a comment above the patterns
to clarify why insn_and_split instead of expand. Something like "to help
combine match...", no need for a V2 though.
Regards
Robin
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
2023-05-31 11:55 ` Robin Dapp
@ 2023-05-31 12:58 ` Jeff Law
2023-05-31 13:23 ` 钟居哲
0 siblings, 1 reply; 6+ messages in thread
From: Jeff Law @ 2023-05-31 12:58 UTC (permalink / raw)
To: Robin Dapp, juzhe.zhong, gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer
On 5/31/23 05:55, Robin Dapp wrote:
> Hi Juzhe,
>
>> The approach is quite simple and obvious, changing extension pattern
>> into define_insn_and_split will make combine PASS combine into widen
>> operations naturally.
>
> looks good to me. Tiny nit: I would add a comment above the patterns
> to clarify why insn_and_split instead of expand. Something like "to help
> combine match...", no need for a V2 though.
OK with that change.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Re: [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
2023-05-31 12:58 ` Jeff Law
@ 2023-05-31 13:23 ` 钟居哲
2023-05-31 13:54 ` Jeff Law
2023-05-31 14:06 ` Li, Pan2
0 siblings, 2 replies; 6+ messages in thread
From: 钟居哲 @ 2023-05-31 13:23 UTC (permalink / raw)
To: Jeff Law, rdapp.gcc, gcc-patches; +Cc: kito.cheng, kito.cheng, palmer, palmer
[-- Attachment #1: Type: text/plain, Size: 881 bytes --]
I have sent V2 withing adding commen:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620243.html
Could you take a look at it?
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-05-31 20:58
To: Robin Dapp; juzhe.zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer
Subject: Re: [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
On 5/31/23 05:55, Robin Dapp wrote:
> Hi Juzhe,
>
>> The approach is quite simple and obvious, changing extension pattern
>> into define_insn_and_split will make combine PASS combine into widen
>> operations naturally.
>
> looks good to me. Tiny nit: I would add a comment above the patterns
> to clarify why insn_and_split instead of expand. Something like "to help
> combine match...", no need for a V2 though.
OK with that change.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
2023-05-31 13:23 ` 钟居哲
@ 2023-05-31 13:54 ` Jeff Law
2023-05-31 14:06 ` Li, Pan2
1 sibling, 0 replies; 6+ messages in thread
From: Jeff Law @ 2023-05-31 13:54 UTC (permalink / raw)
To: 钟居哲, rdapp.gcc, gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer
On 5/31/23 07:23, 钟居哲 wrote:
> I have sent V2 withing adding commen:
> https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620243.html
> <https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620243.html>
> Could you take a look at it?
I'd probably remove "PASS" from that comment. I don't think you need to
post a V3. Just remove that word from the comment and commit.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: Re: [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
2023-05-31 13:23 ` 钟居哲
2023-05-31 13:54 ` Jeff Law
@ 2023-05-31 14:06 ` Li, Pan2
1 sibling, 0 replies; 6+ messages in thread
From: Li, Pan2 @ 2023-05-31 14:06 UTC (permalink / raw)
To: 钟居哲, Jeff Law, rdapp.gcc, gcc-patches
Cc: kito.cheng, kito.cheng, palmer, palmer
Committed with that change, thanks Jeff.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel.com@gcc.gnu.org> On Behalf Of ???
Sent: Wednesday, May 31, 2023 9:24 PM
To: Jeff Law <jeffreyalaw@gmail.com>; rdapp.gcc <rdapp.gcc@gmail.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: kito.cheng <kito.cheng@gmail.com>; kito.cheng <kito.cheng@sifive.com>; palmer <palmer@dabbelt.com>; palmer <palmer@rivosinc.com>
Subject: Re: Re: [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
I have sent V2 withing adding commen:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/620243.html
Could you take a look at it?
juzhe.zhong@rivai.ai
From: Jeff Law
Date: 2023-05-31 20:58
To: Robin Dapp; juzhe.zhong; gcc-patches
CC: kito.cheng; kito.cheng; palmer; palmer
Subject: Re: [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization
On 5/31/23 05:55, Robin Dapp wrote:
> Hi Juzhe,
>
>> The approach is quite simple and obvious, changing extension pattern
>> into define_insn_and_split will make combine PASS combine into widen
>> operations naturally.
>
> looks good to me. Tiny nit: I would add a comment above the patterns
> to clarify why insn_and_split instead of expand. Something like "to help
> combine match...", no need for a V2 though.
OK with that change.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-05-31 14:06 UTC | newest]
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2023-05-31 11:32 [PATCH] RISC-V: Add vwadd<u>/vwsub<u>/vwmul<u>/vwmulsu.vv lowering optimizaiton for RVV auto-vectorization juzhe.zhong
2023-05-31 11:55 ` Robin Dapp
2023-05-31 12:58 ` Jeff Law
2023-05-31 13:23 ` 钟居哲
2023-05-31 13:54 ` Jeff Law
2023-05-31 14:06 ` Li, Pan2
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