* [PATCH-3, rs6000] Change mode and insn condition for scalar insert exp instruction
@ 2023-01-04 6:17 HAO CHEN GUI
2023-04-24 5:30 ` HAO CHEN GUI
2023-05-08 6:33 ` Kewen.Lin
0 siblings, 2 replies; 3+ messages in thread
From: HAO CHEN GUI @ 2023-01-04 6:17 UTC (permalink / raw)
To: gcc-patches; +Cc: Segher Boessenkool, David, Kewen.Lin, Peter Bergner
Hi,
This patch changes the mode of exponent to GPR in scalar insert exp
pattern, as the exponent can be put into a 32-bit register. Also the
condition check is changed from TARGET_64BIT to TARGET_POWERPC64.
The test cases are modified according to the changes of expand pattern.
Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
Is this okay for trunk? Any recommendations? Thanks a lot.
Gui Haochen
ChangeLog
2023-01-03 Haochen Gui <guihaoc@linux.ibm.com>
gcc/
* config/rs6000/rs6000-builtins.def
(__builtin_vsx_scalar_insert_exp): Replace bif-pattern from xsiexpdp
to xsiexpdp_di.
(__builtin_vsx_scalar_insert_exp_dp): Replace bif-pattern from
xsiexpdpf to xsiexpdpf_di.
* config/rs6000/vsx.md (xsiexpdp): Rename to...
(xsiexpdp_<mode>): ..., set the mode of second operand to GPR and
replace TARGET_64BIT with TARGET_POWERPC64.
(xsiexpdpf): Rename to...
(xsiexpdpf_<mode>): ..., set the mode of second operand to GPR and
replace TARGET_64BIT with TARGET_POWERPC64.
gcc/testsuite/
* gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Replace lp64 check
with has_arch_ppc64.
* gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise.
* gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise.
patch.diff
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index 25647b7bdd2..b1b5002d7d9 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2854,10 +2854,10 @@
const double __builtin_vsx_scalar_insert_exp (unsigned long long, \
unsigned long long);
- VSIEDP xsiexpdp {}
+ VSIEDP xsiexpdp_di {}
const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long);
- VSIEDPF xsiexpdpf {}
+ VSIEDPF xsiexpdpf_di {}
pure vsc __builtin_vsx_xl_len_r (void *, signed long);
XL_LEN_R xl_len_r {}
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 27e03a4cf6c..3376090cc6f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5137,22 +5137,22 @@ (define_insn "xsiexpqp_<mode>"
[(set_attr "type" "vecmove")])
;; VSX Scalar Insert Exponent Double-Precision
-(define_insn "xsiexpdp"
+(define_insn "xsiexpdp_<mode>"
[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:DI 1 "register_operand" "r")
- (match_operand:DI 2 "register_operand" "r")]
+ (match_operand:GPR 2 "register_operand" "r")]
UNSPEC_VSX_SIEXPDP))]
- "TARGET_P9_VECTOR && TARGET_64BIT"
+ "TARGET_P9_VECTOR && TARGET_POWERPC64"
"xsiexpdp %x0,%1,%2"
[(set_attr "type" "fpsimple")])
;; VSX Scalar Insert Exponent Double-Precision Floating Point Argument
-(define_insn "xsiexpdpf"
+(define_insn "xsiexpdpf_<mode>"
[(set (match_operand:DF 0 "vsx_register_operand" "=wa")
(unspec:DF [(match_operand:DF 1 "register_operand" "r")
- (match_operand:DI 2 "register_operand" "r")]
+ (match_operand:GPR 2 "register_operand" "r")]
UNSPEC_VSX_SIEXPDP))]
- "TARGET_P9_VECTOR && TARGET_64BIT"
+ "TARGET_P9_VECTOR && TARGET_POWERPC64"
"xsiexpdp %x0,%1,%2"
[(set_attr "type" "fpsimple")])
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
index d8243258a67..88d77564158 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
index 8260b107178..2f219ddc83a 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
index 384fc9cc675..9eade34d9ad 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target p9vector_hw } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
index 0e004224277..674fba951ae 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
@@ -1,7 +1,7 @@
/* { dg-do run { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target p9vector_hw } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
index 3ecbe3318e8..afa2b83f2d2 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
index 1699c67a2f1..6dc06dd34ea 100644
--- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
@@ -1,7 +1,7 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-require-effective-target lp64 } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-mdejagnu-cpu=power8" } */
+/* { dg-require-effective-target has_arch_ppc64 } */
/* This test should succeed only on 64-bit configurations. */
#include <altivec.h>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH-3, rs6000] Change mode and insn condition for scalar insert exp instruction
2023-01-04 6:17 [PATCH-3, rs6000] Change mode and insn condition for scalar insert exp instruction HAO CHEN GUI
@ 2023-04-24 5:30 ` HAO CHEN GUI
2023-05-08 6:33 ` Kewen.Lin
1 sibling, 0 replies; 3+ messages in thread
From: HAO CHEN GUI @ 2023-04-24 5:30 UTC (permalink / raw)
To: gcc-patches; +Cc: Segher Boessenkool, David, Kewen.Lin, Peter Bergner
Hi,
Gently ping this.
https://gcc.gnu.org/pipermail/gcc-patches/2023-January/609371.html
Thanks
Gui Haochen
在 2023/1/4 14:17, HAO CHEN GUI 写道:
> Hi,
> This patch changes the mode of exponent to GPR in scalar insert exp
> pattern, as the exponent can be put into a 32-bit register. Also the
> condition check is changed from TARGET_64BIT to TARGET_POWERPC64.
>
> The test cases are modified according to the changes of expand pattern.
>
> Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
> Is this okay for trunk? Any recommendations? Thanks a lot.
>
> Gui Haochen
>
> ChangeLog
> 2023-01-03 Haochen Gui <guihaoc@linux.ibm.com>
>
> gcc/
> * config/rs6000/rs6000-builtins.def
> (__builtin_vsx_scalar_insert_exp): Replace bif-pattern from xsiexpdp
> to xsiexpdp_di.
> (__builtin_vsx_scalar_insert_exp_dp): Replace bif-pattern from
> xsiexpdpf to xsiexpdpf_di.
> * config/rs6000/vsx.md (xsiexpdp): Rename to...
> (xsiexpdp_<mode>): ..., set the mode of second operand to GPR and
> replace TARGET_64BIT with TARGET_POWERPC64.
> (xsiexpdpf): Rename to...
> (xsiexpdpf_<mode>): ..., set the mode of second operand to GPR and
> replace TARGET_64BIT with TARGET_POWERPC64.
>
> gcc/testsuite/
> * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Replace lp64 check
> with has_arch_ppc64.
> * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise.
> * gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise.
> * gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise.
> * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise.
> * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise.
>
> patch.diff
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index 25647b7bdd2..b1b5002d7d9 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2854,10 +2854,10 @@
>
> const double __builtin_vsx_scalar_insert_exp (unsigned long long, \
> unsigned long long);
> - VSIEDP xsiexpdp {}
> + VSIEDP xsiexpdp_di {}
>
> const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long);
> - VSIEDPF xsiexpdpf {}
> + VSIEDPF xsiexpdpf_di {}
>
> pure vsc __builtin_vsx_xl_len_r (void *, signed long);
> XL_LEN_R xl_len_r {}
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 27e03a4cf6c..3376090cc6f 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -5137,22 +5137,22 @@ (define_insn "xsiexpqp_<mode>"
> [(set_attr "type" "vecmove")])
>
> ;; VSX Scalar Insert Exponent Double-Precision
> -(define_insn "xsiexpdp"
> +(define_insn "xsiexpdp_<mode>"
> [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
> (unspec:DF [(match_operand:DI 1 "register_operand" "r")
> - (match_operand:DI 2 "register_operand" "r")]
> + (match_operand:GPR 2 "register_operand" "r")]
> UNSPEC_VSX_SIEXPDP))]
> - "TARGET_P9_VECTOR && TARGET_64BIT"
> + "TARGET_P9_VECTOR && TARGET_POWERPC64"
> "xsiexpdp %x0,%1,%2"
> [(set_attr "type" "fpsimple")])
>
> ;; VSX Scalar Insert Exponent Double-Precision Floating Point Argument
> -(define_insn "xsiexpdpf"
> +(define_insn "xsiexpdpf_<mode>"
> [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
> (unspec:DF [(match_operand:DF 1 "register_operand" "r")
> - (match_operand:DI 2 "register_operand" "r")]
> + (match_operand:GPR 2 "register_operand" "r")]
> UNSPEC_VSX_SIEXPDP))]
> - "TARGET_P9_VECTOR && TARGET_64BIT"
> + "TARGET_P9_VECTOR && TARGET_POWERPC64"
> "xsiexpdp %x0,%1,%2"
> [(set_attr "type" "fpsimple")])
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> index d8243258a67..88d77564158 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
> index 8260b107178..2f219ddc83a 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-options "-mdejagnu-cpu=power8" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> index 384fc9cc675..9eade34d9ad 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target p9vector_hw } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> index 0e004224277..674fba951ae 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target p9vector_hw } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> index 3ecbe3318e8..afa2b83f2d2 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
> index 1699c67a2f1..6dc06dd34ea 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-options "-mdejagnu-cpu=power8" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH-3, rs6000] Change mode and insn condition for scalar insert exp instruction
2023-01-04 6:17 [PATCH-3, rs6000] Change mode and insn condition for scalar insert exp instruction HAO CHEN GUI
2023-04-24 5:30 ` HAO CHEN GUI
@ 2023-05-08 6:33 ` Kewen.Lin
1 sibling, 0 replies; 3+ messages in thread
From: Kewen.Lin @ 2023-05-08 6:33 UTC (permalink / raw)
To: HAO CHEN GUI; +Cc: Segher Boessenkool, David, Peter Bergner, gcc-patches
Hi Haochen,
on 2023/1/4 14:17, HAO CHEN GUI wrote:
> Hi,
> This patch changes the mode of exponent to GPR in scalar insert exp
> pattern, as the exponent can be put into a 32-bit register. Also the
> condition check is changed from TARGET_64BIT to TARGET_POWERPC64.
>
> The test cases are modified according to the changes of expand pattern.
>
> Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
> Is this okay for trunk? Any recommendations? Thanks a lot.
>
This patch is OK for trunk, thanks!
BR,
Kewen
> Gui Haochen
>
> ChangeLog
> 2023-01-03 Haochen Gui <guihaoc@linux.ibm.com>
>
> gcc/
> * config/rs6000/rs6000-builtins.def
> (__builtin_vsx_scalar_insert_exp): Replace bif-pattern from xsiexpdp
> to xsiexpdp_di.
> (__builtin_vsx_scalar_insert_exp_dp): Replace bif-pattern from
> xsiexpdpf to xsiexpdpf_di.
> * config/rs6000/vsx.md (xsiexpdp): Rename to...
> (xsiexpdp_<mode>): ..., set the mode of second operand to GPR and
> replace TARGET_64BIT with TARGET_POWERPC64.
> (xsiexpdpf): Rename to...
> (xsiexpdpf_<mode>): ..., set the mode of second operand to GPR and
> replace TARGET_64BIT with TARGET_POWERPC64.
>
> gcc/testsuite/
> * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Replace lp64 check
> with has_arch_ppc64.
> * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise.
> * gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise.
> * gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise.
> * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise.
> * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise.
>
> patch.diff
> diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
> index 25647b7bdd2..b1b5002d7d9 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -2854,10 +2854,10 @@
>
> const double __builtin_vsx_scalar_insert_exp (unsigned long long, \
> unsigned long long);
> - VSIEDP xsiexpdp {}
> + VSIEDP xsiexpdp_di {}
>
> const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long);
> - VSIEDPF xsiexpdpf {}
> + VSIEDPF xsiexpdpf_di {}
>
> pure vsc __builtin_vsx_xl_len_r (void *, signed long);
> XL_LEN_R xl_len_r {}
> diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
> index 27e03a4cf6c..3376090cc6f 100644
> --- a/gcc/config/rs6000/vsx.md
> +++ b/gcc/config/rs6000/vsx.md
> @@ -5137,22 +5137,22 @@ (define_insn "xsiexpqp_<mode>"
> [(set_attr "type" "vecmove")])
>
> ;; VSX Scalar Insert Exponent Double-Precision
> -(define_insn "xsiexpdp"
> +(define_insn "xsiexpdp_<mode>"
> [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
> (unspec:DF [(match_operand:DI 1 "register_operand" "r")
> - (match_operand:DI 2 "register_operand" "r")]
> + (match_operand:GPR 2 "register_operand" "r")]
> UNSPEC_VSX_SIEXPDP))]
> - "TARGET_P9_VECTOR && TARGET_64BIT"
> + "TARGET_P9_VECTOR && TARGET_POWERPC64"
> "xsiexpdp %x0,%1,%2"
> [(set_attr "type" "fpsimple")])
>
> ;; VSX Scalar Insert Exponent Double-Precision Floating Point Argument
> -(define_insn "xsiexpdpf"
> +(define_insn "xsiexpdpf_<mode>"
> [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
> (unspec:DF [(match_operand:DF 1 "register_operand" "r")
> - (match_operand:DI 2 "register_operand" "r")]
> + (match_operand:GPR 2 "register_operand" "r")]
> UNSPEC_VSX_SIEXPDP))]
> - "TARGET_P9_VECTOR && TARGET_64BIT"
> + "TARGET_P9_VECTOR && TARGET_POWERPC64"
> "xsiexpdp %x0,%1,%2"
> [(set_attr "type" "fpsimple")])
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> index d8243258a67..88d77564158 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
> index 8260b107178..2f219ddc83a 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-options "-mdejagnu-cpu=power8" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> index 384fc9cc675..9eade34d9ad 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target p9vector_hw } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> index 0e004224277..674fba951ae 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c
> @@ -1,7 +1,7 @@
> /* { dg-do run { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target p9vector_hw } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> index 3ecbe3318e8..afa2b83f2d2 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-3.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-options "-mdejagnu-cpu=power9" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
> index 1699c67a2f1..6dc06dd34ea 100644
> --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
> +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-4.c
> @@ -1,7 +1,7 @@
> /* { dg-do compile { target { powerpc*-*-* } } } */
> -/* { dg-require-effective-target lp64 } */
> /* { dg-require-effective-target powerpc_p9vector_ok } */
> /* { dg-options "-mdejagnu-cpu=power8" } */
> +/* { dg-require-effective-target has_arch_ppc64 } */
>
> /* This test should succeed only on 64-bit configurations. */
> #include <altivec.h>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-05-08 6:33 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-01-04 6:17 [PATCH-3, rs6000] Change mode and insn condition for scalar insert exp instruction HAO CHEN GUI
2023-04-24 5:30 ` HAO CHEN GUI
2023-05-08 6:33 ` Kewen.Lin
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